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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498f0be0esm122123665ad.96.2025.10.28.09.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 09:51:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/5] clk: renesas: r9a09g077: Propagate rate changes to parent clocks Date: Tue, 28 Oct 2025 16:51:23 +0000 Message-ID: <20251028165127.991351-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the CLK_SET_RATE_PARENT flag to divider clock registration so that rate changes can propagate to parent clocks when needed. This allows the CPG divider clocks to request rate adjustments from their parent, ensuring correct frequency scaling and improved flexibility in clock rate selection. Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1-v2: - New patch --- drivers/clk/renesas/r9a09g077-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 8b7e84a4c307..1cb33c12234e 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -221,7 +221,7 @@ r9a09g077_cpg_div_clk_register(struct device *dev, =20 if (core->dtable) clk_hw =3D clk_hw_register_divider_table(dev, core->name, - parent_name, 0, + parent_name, CLK_SET_RATE_PARENT, addr, GET_SHIFT(core->conf), GET_WIDTH(core->conf), @@ -230,7 +230,7 @@ r9a09g077_cpg_div_clk_register(struct device *dev, &pub->rmw_lock); else clk_hw =3D clk_hw_register_divider(dev, core->name, - parent_name, 0, + parent_name, CLK_SET_RATE_PARENT, addr, GET_SHIFT(core->conf), GET_WIDTH(core->conf), --=20 2.43.0 From nobody Mon Feb 9 16:12:29 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03E1934889B for ; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498f0be0esm122123665ad.96.2025.10.28.09.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 09:51:57 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/5] clk: renesas: r9a09g077: Remove stray blank line Date: Tue, 28 Oct 2025 16:51:24 +0000 Message-ID: <20251028165127.991351-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Remove an unnecessary blank line at the end of r9a09g077_cpg_div_clk_register() to tidy up the code. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1-v2: - New patch --- drivers/clk/renesas/r9a09g077-cpg.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 1cb33c12234e..666fc16b9a81 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -240,7 +240,6 @@ r9a09g077_cpg_div_clk_register(struct device *dev, return ERR_CAST(clk_hw); =20 return clk_hw->clk; - } =20 static struct clk * __init --=20 2.43.0 From nobody Mon Feb 9 16:12:29 2026 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A83F63469E7 for ; Tue, 28 Oct 2025 16:52:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761670328; cv=none; b=bOQbc5PgqnEA3vOgRUNQIwvLfS+N+NELGTEDsz7wM34YyTXz2wc8MqufEYD4mXKRSVZzs/y7qVYrlzuiEg3WOsLfZH63Y6BG7NvmRwOLpgnysnnaD5o0+sIhP0cY/aoeGMHkXA9fhTvbPeIhfESsBKlSWdTZHocuVDR8CzJNUQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761670328; c=relaxed/simple; bh=uAi2FHcWsJ3GX+mStHxzc2rrz7IQpZYtqIP74XffftE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i48BQKBXeXm5hev29J9syGUeGYxLqaAeXo2GHgrWMBOgVq7IxTmHByx3VeAF2aOuMWmlwPmhEIH6JMiq7bhOvvIl6oZNkM4QFuTqQ4TDEGjyB81NyvNn8l2aQvNxn1aQMd+CzwwNe/t/RLC9MWY9AuM/U75OlpwVxm4sKDIppA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VBDswHIi; arc=none smtp.client-ip=209.85.215.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VBDswHIi" Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-b6cfffbb1e3so4528506a12.3 for ; Tue, 28 Oct 2025 09:52:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1761670325; x=1762275125; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ozhuagEONZfNxkbetsUDydMVsoqSUlAvk99bJ1oqkyE=; b=VBDswHIikAYS2q0DgNT6jElJeM8Tn4FQ7TG5FDNH5dlPJSmbWYSFpH+8UzamC+Grwa 7zECYJ6zkBJ5LL7jKlSo5sSMtHNuZ9YBWMa+IycOp9PX/ye9nig7879/XMRyii81g2e8 Z+ujwtzreE3lvFkPAyeTdgpELJ1RmsG0O9quDHapWU44hV8/rYLKmtEOT2W8c7DxE1W2 MiD7VqliDv+qqrkTQCYQP8oGjJHElrxEqAqMwJ7a1UMBLnhUMYY1KDDAYLygJhU6Tark j5tLzCQhMReRF3B7Ic5WWJ5+dzYX+XUMyONO8bw/OJ2iwHknj4fz2RxBg+0co99nzPRR Z99w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761670325; x=1762275125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ozhuagEONZfNxkbetsUDydMVsoqSUlAvk99bJ1oqkyE=; b=t6wsmXjamAEDCkMuZKbU1YKL/rOlKi6xhq9XFIH+jiu51SMmZsekSG7vvgSySR6bgq WUMSv+CnzgPUOocpKUDqDGXpSsjfTNetI1AV67D5YzUkxzyu8u7ly/nOek6DhUAtCKMW chb9hcXNMofaPYRrpbydm0aExFQo8l8RyP18pULMChZFdANsv0sej1deGfcDGdwJYriF OWG9aylulalor9+1PhnzZomibu1+3FGrg3OmEDT1QAan5iHwk7xysnQrnffR2oVxzIJm IDVA+GjxRLBVImPUsh1a5QmLYhUHAgJDEy4K+fkGw2H7qye+HKsP6VxBadnSaSI9/iEt 9cTQ== X-Forwarded-Encrypted: i=1; AJvYcCXLPM+v0OyVE9XUhShDYWy3FIOgVxBVgTWEcJOVL7uRAOvPTIZ0Gbx/IpMiDjxFsToG68g6YDN5Wi6JHlM=@vger.kernel.org X-Gm-Message-State: AOJu0Yyt1NZARWoTcFqoC8MQQcG2HDGMcP+Nwuo+wNLOzMI4TRKaWIkk k8kevQwvZo+1uEwD/wgMMRhSATxr+e+HbnlYgZQs22Ui6EyK9Ky/cHno X-Gm-Gg: ASbGncttvoFW7C8+srgUJMjxw7SSyd9+MgLCPHbv6RsFAHKLErl+AWJpGjvBNvph3HM Ur9C4+T1+forujKD10ZnIfN02FAZ5j1G3BEeLhNzYDqk8ICZL6WsAikBrLAMCblPI+u//yGsqsv LzrzUnxEeQdQgIq/L+GtKIHEaWJ7xCS4R4ePc3KYl4sCeSgWHXUy56+bwYqQufNQ7qTwrEjuYVC vpDL+AyoDoszEeb5TpZ/VsryAbjD8nBeSCfqIEQ4F5k5PRdnCY4bIkYenQ/qqRMS5r7zCtGhN4c VsYaQ8/lbECIaZxRGm6Byk+jTuFG0IRh4IwWlOzZ0N6znSIZITrKkAe4BHtEF9Wq+OHdGA5nImJ P1WBa1+LzhtMbeXEhBV559i7RiYOVltC5+Hb+LS1UhzUL0rk2USWyIPiJLlHN6247ttvbIvlonX iiU5l6MR/vrbPuCCCVjyX5jA== X-Google-Smtp-Source: AGHT+IH8qFlYrrL24sCRWgUP6EN5lsSkXhcAlMQevGU1F8wGdL4QnVY/o2LpJYNhO1zLzXrVH+kFBQ== X-Received: by 2002:a17:902:d2c1:b0:292:dca8:c140 with SMTP id d9443c01a7336-294cb6739b3mr50494845ad.44.1761670324753; Tue, 28 Oct 2025 09:52:04 -0700 (PDT) Received: from iku.. ([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498f0be0esm122123665ad.96.2025.10.28.09.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 09:52:04 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/5] clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration Date: Tue, 28 Oct 2025 16:51:25 +0000 Message-ID: <20251028165127.991351-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Convert the divider clock registration in the R9A09G077 CPG driver to use device-managed (devm_) helper functions. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1-v2: - New patch --- drivers/clk/renesas/r9a09g077-cpg.c | 30 +++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 666fc16b9a81..b46167d42084 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -220,21 +220,23 @@ r9a09g077_cpg_div_clk_register(struct device *dev, parent_name =3D __clk_get_name(parent); =20 if (core->dtable) - clk_hw =3D clk_hw_register_divider_table(dev, core->name, - parent_name, CLK_SET_RATE_PARENT, - addr, - GET_SHIFT(core->conf), - GET_WIDTH(core->conf), - core->flag, - core->dtable, - &pub->rmw_lock); + clk_hw =3D devm_clk_hw_register_divider_table(dev, core->name, + parent_name, + CLK_SET_RATE_PARENT, + addr, + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, + core->dtable, + &pub->rmw_lock); else - clk_hw =3D clk_hw_register_divider(dev, core->name, - parent_name, CLK_SET_RATE_PARENT, - addr, - GET_SHIFT(core->conf), - GET_WIDTH(core->conf), - core->flag, &pub->rmw_lock); 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498f0be0esm122123665ad.96.2025.10.28.09.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 09:52:10 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Conor Dooley Subject: [PATCH v2 4/5] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Date: Tue, 28 Oct 2025 16:51:26 +0000 Message-ID: <20251028165127.991351-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock definitions for XSPI0/1 to both R9A09G077 and R9A09G087 SoCs. These definitions are required for describing XSPI devices in DT Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v1-v2: - Added Acked-by and Reviewed-by tags --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 2 ++ include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..9eaedca6a616 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..606468ac49a4 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ --=20 2.43.0 From nobody Mon Feb 9 16:12:29 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9EE34B419 for ; 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([2401:4900:1c06:77f0:168f:479e:bf92:ce93]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498f0be0esm122123665ad.96.2025.10.28.09.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 09:52:16 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 5/5] clk: renesas: r9a09g077: Add xSPI core and module clocks Date: Tue, 28 Oct 2025 16:51:27 +0000 Message-ID: <20251028165127.991351-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251028165127.991351-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add core clocks and module clock definitions required by the xSPI (Expanded SPI) IP on the R9A09G077 SoC. Define the new SCKCR fields FSELXSPI0/FSELXSPI1 and DIVSEL_XSPI0/1 and add two new core clocks XSPI_CLK0 and XSPI_CLK1. The xSPI block uses PCLKH as its bus clock (use as module clock parent) while the operation clock (XSPI_CLKn) is derived from PLL4. To support this arrangement provide mux/div selectors and divider tables for the supported XSPI operating rates. Add CLK_TYPE_RZT2H_FSELXSPI to implement a custom divider/mux clock where the determine_rate() callback enforces the hardware constraint: when the parent output is 600MHz only dividers 8 and 16 are valid, whereas for 800MHz operation the full divider set (6,8,16,32,64) may be used. The custom determine_rate() picks the best parent/divider pair to match the requested rate and programs the appropriate SCKCR fields. Signed-off-by: Lad Prabhakar --- v1->v2: - Added custom divider clock type for XSPI clocks to enforce hardware constraints on supported operating rates. --- drivers/clk/renesas/r9a09g077-cpg.c | 155 +++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index b46167d42084..678dc36461c0 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include =20 #include #include @@ -54,12 +56,19 @@ #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2) #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2) =20 +#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3) +#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3) +#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1) +#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1) #define SEL_PLL CONF_PACK(SCKCR, 22, 1) =20 +#define DIVSELXSPI_RATE_600MHZ 600000000UL +#define DIVSELXSPI_RATE_800MHZ 800000000UL =20 enum rzt2h_clk_types { CLK_TYPE_RZT2H_DIV =3D CLK_TYPE_CUSTOM, /* Clock with divider */ CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */ + CLK_TYPE_RZT2H_FSELXSPI, }; =20 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ @@ -69,10 +78,13 @@ enum rzt2h_clk_types { DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf =3D _conf, \ .parent_names =3D _parent_names, .num_parents =3D _num_parents, \ .flag =3D 0, .mux_flags =3D _mux_flags) +#define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf =3D _conf, \ + .parent =3D _parent, .dtable =3D _dtable, .flag =3D 0) =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G077_ETCLKE, + LAST_DT_CORE_CLK =3D R9A09G077_XSPI_CLK1, =20 /* External Input Clocks */ CLK_EXTAL, @@ -88,12 +100,16 @@ enum clk_ids { CLK_SEL_CLK_PLL2, CLK_SEL_CLK_PLL4, CLK_PLL4D1, + CLK_PLL4D1_DIV3, + CLK_PLL4D1_DIV4, CLK_SCI0ASYNC, CLK_SCI1ASYNC, CLK_SCI2ASYNC, CLK_SCI3ASYNC, CLK_SCI4ASYNC, CLK_SCI5ASYNC, + CLK_DIVSELXSPI0_SCKCR, + CLK_DIVSELXSPI1_SCKCR, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -105,6 +121,15 @@ static const struct clk_div_table dtable_1_2[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_6_8_16_32_64[] =3D { + {6, 64}, + {5, 32}, + {4, 16}, + {3, 8}, + {2, 6}, + {0, 0}, +}; + static const struct clk_div_table dtable_24_25_30_32[] =3D { {0, 32}, {1, 30}, @@ -119,6 +144,7 @@ static const char * const sel_clk_pll0[] =3D { ".loco",= ".pll0" }; static const char * const sel_clk_pll1[] =3D { ".loco", ".pll1" }; static const char * const sel_clk_pll2[] =3D { ".loco", ".pll2" }; static const char * const sel_clk_pll4[] =3D { ".loco", ".pll4" }; +static const char * const sel_clk_pll4d1_div3_div4[] =3D { ".pll4d1_div3",= ".pll4d1_div4" }; =20 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst =3D { /* External Clock Inputs */ @@ -154,6 +180,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[]= __initconst =3D { DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC, dtable_24_25_30_32), =20 + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), + DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0, + sel_clk_pll4d1_div3_div4, + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0), + DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1, + sel_clk_pll4d1_div3_div4, + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0), + /* Core output clk */ DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0, dtable_1_2), @@ -178,9 +213,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[]= __initconst =3D { DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1), DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1), DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1), + DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR, + FSELXSPI0, dtable_6_8_16_32_64), + DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR, + FSELXSPI1, dtable_6_8_16_32_64), }; =20 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =3D { + DEF_MOD("xspi0", 4, R9A09G077_CLK_PCLKH), + DEF_MOD("xspi1", 5, R9A09G077_CLK_PCLKH), DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC), DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC), DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC), @@ -264,6 +305,116 @@ r9a09g077_cpg_mux_clk_register(struct device *dev, return clk_hw->clk; } =20 +static int r9a09g077_cpg_fselxspi_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider *divider =3D to_clk_divider(hw); + unsigned long parent_rate, best =3D 0, now; + const struct clk_div_table *clkt; + unsigned long rate =3D req->rate; + int div =3D 0; + + if (!rate) + rate =3D 1; + + for (clkt =3D divider->table; clkt->div; clkt++) { + parent_rate =3D clk_hw_round_rate(req->best_parent_hw, rate * clkt->div); + /* + * DIVSELXSPIx supports 800MHz and 600MHz operation. + * When the parent_rate is 600MHz, only dividers of 8 and 16 + * are supported otherwise dividers of 6, 8, 16, 32, 64 are supported. + * This check ensures that FSELXSPIx is set correctly. + */ + if (parent_rate =3D=3D DIVSELXSPI_RATE_600MHZ && + (clkt->div !=3D 8 && clkt->div !=3D 16)) + continue; + now =3D DIV_ROUND_UP_ULL((u64)parent_rate, clkt->div); + if (abs(rate - now) < abs(rate - best)) { + div =3D clkt->div; + best =3D now; + req->best_parent_rate =3D parent_rate; + } + } + + if (!div) { + u8 maxdiv =3D 0; + + req->best_parent_rate =3D clk_hw_round_rate(req->best_parent_hw, 1); + /* + * If DIVSELXSPIx is set to 800MHz set the maximum divider + * or else fall back to divider of 16 which is a maximum + * supported divider for 600MHz operation. + */ + if (req->best_parent_rate =3D=3D DIVSELXSPI_RATE_800MHZ) { + for (clkt =3D divider->table; clkt->div; clkt++) { + if (clkt->div > maxdiv) + maxdiv =3D clkt->div; + } + div =3D maxdiv; + } else { + div =3D 16; + } + } + + req->rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} + +static struct clk * __init +r9a09g077_cpg_fselxspi_div_clk_register(struct device *dev, + const struct cpg_core_clk *core, + void __iomem *addr, + struct cpg_mssr_pub *pub) +{ + static struct clk_ops *xspi_div_ops; + struct clk_init_data init =3D {}; + const struct clk *parent; + const char *parent_name; + struct clk_divider *div; + struct clk_hw *hw; + int ret; + + parent =3D pub->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + div =3D devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + if (!xspi_div_ops) { + xspi_div_ops =3D devm_kzalloc(dev, sizeof(*xspi_div_ops), GFP_KERNEL); + if (!xspi_div_ops) + return ERR_PTR(-ENOMEM); + memcpy(xspi_div_ops, &clk_divider_ops, + sizeof(const struct clk_ops)); + xspi_div_ops->determine_rate =3D r9a09g077_cpg_fselxspi_determine_rate; + } + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D xspi_div_ops; + init.flags =3D CLK_SET_RATE_PARENT; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + div->reg =3D addr; + div->shift =3D GET_SHIFT(core->conf); + div->width =3D GET_WIDTH(core->conf); + div->flags =3D core->flag; + div->lock =3D &pub->rmw_lock; + div->hw.init =3D &init; + div->table =3D core->dtable; + + hw =3D &div->hw; + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw->clk; +} + static struct clk * __init r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *= core, const struct cpg_mssr_info *info, @@ -278,6 +429,8 @@ r9a09g077_cpg_clk_register(struct device *dev, const st= ruct cpg_core_clk *core, return r9a09g077_cpg_div_clk_register(dev, core, addr, pub); case CLK_TYPE_RZT2H_MUX: return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub); + case CLK_TYPE_RZT2H_FSELXSPI: + return r9a09g077_cpg_fselxspi_div_clk_register(dev, core, addr, pub); default: return ERR_PTR(-EINVAL); } --=20 2.43.0