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Tue, 28 Oct 2025 08:57:24 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , Subject: [PATCH v5 3/3] spi: tegra210-quad: Check hardware status on timeout Date: Tue, 28 Oct 2025 15:57:03 +0000 Message-ID: <20251028155703.4151791-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251028155703.4151791-1-va@nvidia.com> References: <20251028155703.4151791-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|MW4PR12MB7032:EE_ X-MS-Office365-Filtering-Correlation-Id: 39e6e66e-a37a-4653-1ac2-08de163abe9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gNcdp7W7FO9CCMK0L7Xidi2pS0jbrawBNyXG5McSbAfzg2xO/mzjwZSHcWsf?= =?us-ascii?Q?tgISxPMfr70bu+zl9IzXbYpV06kQ9HklDWX0lNPjlUlCbcGe6ewiVTykG7Je?= =?us-ascii?Q?HFF7CKInZXATB3N19SW06BBya9UF8HVmt0GV7TprojECLWJbQ2EM+Z067eap?= =?us-ascii?Q?wPTLkWkw6bGND8cqB5kBwxwrWAl/tLQOIcVpi2eRjd/F8hYoNrWS/I18wq/r?= =?us-ascii?Q?3wfpWollpriuB5LPoDKNSvj1jYNvxJt2yUbEkbB2AHSEDEit0fZV635qb3lT?= =?us-ascii?Q?MwJ8JibRhqD3K15Og5yCNElZklyXiPzP+6mVJYMw4k1fFj2vzgobVhzqrp/X?= =?us-ascii?Q?a8nqsRnsFGAlil4DXkyDEV/Tui+vY0prxb7seKioNol1Wp2wNu2yxRzl+9B4?= =?us-ascii?Q?jhrzOLTjuIDRjejgll6atnbbwowezVkWGH0LN/RiN2jAgKTofuDfVAdt8LDs?= =?us-ascii?Q?w+3QS+C1rEUQUh966ZWzgwKrd6RRXPyYDIvUzH4nS1xeiPhrF+tZf0s8LLRa?= =?us-ascii?Q?5Zb/ACFCmQ51edyfl7XJvGS24GtysvA/j+OYrAx2YnvhdiQhvtBBggFnIN2U?= =?us-ascii?Q?vavuiuDaP+um3lNc5yGBzxbNuHIu5eHLnFHKGbPeU9RRI+zyrBGfX+3l98ff?= =?us-ascii?Q?1Wl1mbJ4Up0Dlt8EFpYFnus49j50hWHlc+Eo4aigC5bhjTn+QgWcBkTQzCKw?= =?us-ascii?Q?oPeLNb0YeVMduTCdzu41bxAqr0urvI5HJwlDrc7td9mwDOYjNaSJMTV7Ggs8?= =?us-ascii?Q?IO6QLdNH1Z2jMWB56uInPlXe/AgqPPcP2hrsys82z7F+V56AWUN4QqriWkTg?= =?us-ascii?Q?JONDo0zd6i0Wq9RErPG2FgoZL+Slrjlgt2RecU1N+WiCEw4UKN0HdLdioK9+?= =?us-ascii?Q?IUu0uJ0gOwhz6G9muUnE/8yeN8HtdM6lFr8gp4YuVIIw5BEPImmoXCnS0j0H?= =?us-ascii?Q?mco7lg3WbU6efCcKlEsSiZKdY4kve/I9Z8cARE+YRKxqOtEQHIL7nzHAwcSp?= =?us-ascii?Q?TKCUsH05wVP3+8h6mLHE70DXhx3UVHA4pX1SY/yMBGopwu+eIgZoWYo5V+9+?= =?us-ascii?Q?FyWqDsF41phof8iMtjA7ijVOst9ZFYV/0a4Cvh2c0mjVBhk5FJ1qYYQRk1dF?= =?us-ascii?Q?og21Y9hDrDTOEOeRXwxmUcoUL6JXuIRvRtFmU4WGwpNuif4q1TwzJdILgMQx?= =?us-ascii?Q?TDpTbAVvdPd68BVzImBvKrBNWvp9ARlM5T2PBNGddxp+E0Jv4xrOoYM3og9O?= =?us-ascii?Q?G9Jb2IOpD/zGlQVRbWbkYRRebSTh7JrNnsXKKqgVIf64RuPE8060dNR7HeBT?= =?us-ascii?Q?agQ2IRJ+bHbkX1KwqA2Xw1TcEackRej0sGqqilYALvrRrAu85+x8Oh3AQcM4?= =?us-ascii?Q?0gTt5LpG/AoNv/+SNSK6Mzui3vFwnLyk8r9V1jlMa+UqlY7K+oq4E7qbFO2j?= =?us-ascii?Q?3fJdXWp4ktzILUf+kOuT7w3UyXGv1Cl8mue1FQsfMA7CFkvVqfCMg3Hg2H2K?= =?us-ascii?Q?APHNEnu5nsyRirKyIp7N8VRH4JeBENv2/yiF2AbzssZEQqy9gVtDpFDUKREE?= =?us-ascii?Q?YukokPQuBL18RbsgY/w=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 15:57:49.4170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39e6e66e-a37a-4653-1ac2-08de163abe9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7032 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Under high system load, QSPI interrupts can be delayed or blocked on the target CPU, causing wait_for_completion_timeout() to report failure even though the hardware successfully completed the transfer. When a timeout occurs, check the QSPI_RDY bit in QSPI_TRANS_STATUS to determine if the hardware actually completed the transfer. If so, manually invoke the completion handler to process the transfer successfully instead of failing it. This distinguishes lost/delayed interrupts from real hardware timeouts, preventing unnecessary failures of transfers that completed successfully. Signed-off-by: Vishwaroop A Acked-by: Thierry Reding --- drivers/spi/spi-tegra210-quad.c | 100 +++++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 20 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index 69defb4ffe49..cdc3cb7c01f9 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1048,6 +1048,49 @@ static void tegra_qspi_transfer_end(struct spi_devic= e *spi) tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); } =20 +static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi); +static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi); + +/** + * tegra_qspi_handle_timeout - Handle transfer timeout with hardware check + * @tqspi: QSPI controller instance + * + * When a timeout occurs but hardware has completed the transfer (interrupt + * was lost or delayed), manually trigger transfer completion processing. + * This avoids failing transfers that actually succeeded. + * + * Returns: 0 if transfer was completed, -ETIMEDOUT if real timeout + */ +static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) +{ + irqreturn_t ret; + u32 status; + + /* Check if hardware actually completed the transfer */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + if (!(status & QSPI_RDY)) + return -ETIMEDOUT; + + /* + * Hardware completed but interrupt was lost/delayed. Manually + * process the completion by calling the appropriate handler. + */ + dev_warn_ratelimited(tqspi->dev, + "QSPI interrupt timeout, but transfer complete\n"); + + /* Clear the transfer status */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); + + /* Manually trigger completion handler */ + if (!tqspi->is_curr_dma_xfer) + ret =3D handle_cpu_based_xfer(tqspi); + else + ret =3D handle_dma_based_xfer(tqspi); + + return (ret =3D=3D IRQ_HANDLED) ? 0 : -EIO; +} + static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len) { u32 cmd_config =3D 0; @@ -1177,20 +1220,28 @@ static int tegra_qspi_combined_seq_xfer(struct tegr= a_qspi *tqspi, QSPI_DMA_TIMEOUT); =20 if (WARN_ON_ONCE(ret =3D=3D 0)) { - dev_err_ratelimited(tqspi->dev, - "QSPI Transfer failed with timeout\n"); - - /* Abort transfer by resetting pio/dma bit */ - if (tqspi->is_curr_dma_xfer) - tegra_qspi_dma_stop(tqspi); - else - tegra_qspi_pio_stop(tqspi); - - /* Reset controller if timeout happens */ - tegra_qspi_reset(tqspi); - - ret =3D -EIO; - goto exit; + /* + * Check if hardware completed the transfer + * even though interrupt was lost or delayed. + * If so, process the completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); + + /* Abort transfer by resetting pio/dma bit */ + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + else + tegra_qspi_pio_stop(tqspi); + + /* Reset controller if timeout happens */ + tegra_qspi_reset(tqspi); + + ret =3D -EIO; + goto exit; + } } =20 if (tqspi->tx_status || tqspi->rx_status) { @@ -1281,14 +1332,23 @@ static int tegra_qspi_non_combined_seq_xfer(struct = tegra_qspi *tqspi, ret =3D wait_for_completion_timeout(&tqspi->xfer_completion, QSPI_DMA_TIMEOUT); if (WARN_ON(ret =3D=3D 0)) { - dev_err(tqspi->dev, "transfer timeout\n"); + /* + * Check if hardware completed the transfer even though + * interrupt was lost or delayed. If so, process the + * completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); =20 - if (tqspi->is_curr_dma_xfer) - tegra_qspi_dma_stop(tqspi); + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); =20 - tegra_qspi_handle_error(tqspi); - ret =3D -EIO; - goto complete_xfer; + tegra_qspi_handle_error(tqspi); + ret =3D -EIO; + goto complete_xfer; + } } =20 if (tqspi->tx_status || tqspi->rx_status) { --=20 2.17.1