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Tue, 28 Oct 2025 08:15:37 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , Subject: [PATCH v3 3/3] spi: tegra210-quad: Check hardware status on timeout Date: Tue, 28 Oct 2025 15:15:15 +0000 Message-ID: <20251028151515.4142618-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251028151515.4142618-1-va@nvidia.com> References: <20251028151515.4142618-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D7:EE_|CH2PR12MB9493:EE_ X-MS-Office365-Filtering-Correlation-Id: 19f421e7-88b0-4a94-2667-08de1634eb5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MzSyUWWJyylCNLCBaE0shiNBLqS35N0qI1J2ZNCqZbwh+lH1gRuTAG+awWom?= =?us-ascii?Q?FBU6jDNm1cm42bkUH/6Ejn2I+EGuQ2/IFkr3RX7KO/Rn2aWgeTW2F2A1OoIp?= =?us-ascii?Q?3GgS0j33a/ABDKJ9//nRmsLqOFBu54vgZ/oWRqU68WUTuiMbqq+zdFa+hnIb?= =?us-ascii?Q?us32aPx2v1GvKJxsdvWLh6EhfVTYtodUsCA6uFXCO7YofFo2LENABaam0cro?= =?us-ascii?Q?7xxz7tEZnWJ3EUcF0lPXOt87K8EPvpjUHnJwr2bqnSQl3LT/fqEvYf6n7oCM?= =?us-ascii?Q?hIl3l1OMeO5ZjxSDUB/z0VBT6GchoMMeCiGRrQ7xkA39FKiAhS64Sq/D6r4H?= =?us-ascii?Q?rzI2xmzgPnNL7WlOcLD/ZJ19o0thduRh/oQnrc7xk4zEN50zg4/ygpEXaDeu?= =?us-ascii?Q?++nUJeYZ/epDqV7WCpnk6oJvCPbXrSvPDsB1+hK2+jKa3nl3rVqzLzAC4jgw?= =?us-ascii?Q?XOFxyiPQAD8bUfCOXmI0YVUec7/hXFdUNdGNvrhNq5mwmwNTL8DJqcMhPDkb?= =?us-ascii?Q?8SpsLaGoCYaWthYk1IwqUAa5py6NZAaChfKLE12Q+AixnZinPirQ6IxVlB/c?= =?us-ascii?Q?GvB1caqQJwPz3jAXsUzOd5bCZGCXmKIdHLflWQBFeW68UxT4zPnspFw3GB/p?= =?us-ascii?Q?fu16AEv8KnxeoqR1K/Vjez9geHv2vLeJQBZV1jCW2dyY1dsUCMPorlkeTwpX?= =?us-ascii?Q?02u6Fz6jP9MOKlr/ML0+LFIadqc+VFOUxbZhoq8MzsF8xadpQjWJwvo7bkth?= =?us-ascii?Q?VlTUG9ZJv1VYolSeIFwuiitPgsY0MhF4fmjc9eEizwAUAhzlF7VImIJYP1zj?= =?us-ascii?Q?PKLM7ulLBCEX7i/l5uSIPZJxk1NSnPFZkUohNi1unIY58164aRVcJaHqYM6M?= =?us-ascii?Q?zXdt0qUaLUf0RyhksgJ5SLsFV4bt1vY4ZyTlv790EdKEDKshUEHpbnp7aurf?= =?us-ascii?Q?YihGlZqAIv/niPOrPA2Z0WwKmW7dfu3XieRLsrSFT3IV9Jo4M+ckWlU6E81a?= =?us-ascii?Q?7bBYiajUGQm4V7HGEU4ZLje6K3H/VMs/HYnQGu6KMG/vErcvdyDewVPDHorD?= =?us-ascii?Q?DeVifearnwa9i1Oum9K2NJTIvN0xSGB9XOrLYA43GDIN0ZWIJ7Eq7K77lCh6?= =?us-ascii?Q?jSmrfpiKRmS+ntO04yEXQjLuLNXOnPhJXoSkl70UaK5HZDBDqgdgHkZVMJo6?= =?us-ascii?Q?i1E4t3bKMHSjtfDYpR2gpXkZ5IbiL83ub74QLB1SZ0X/oK/UvbXT1ta715nX?= =?us-ascii?Q?oRQ7eBNfwa12WldqZBliGFpZ4vwrIOep6l/6azAa1KbaDFYHrR0EnroJATe5?= =?us-ascii?Q?vn/5k95ARNxqw0z3uczehLRmDtDFmA7xeCLgeGxQwNPUyjFQdrLwfC8mFGGr?= =?us-ascii?Q?F9tDF7YonkPDiy97E2ckJRcwuUZr3PFh0xHyfey2vf7dJzYdrqGDUT/lFzYi?= =?us-ascii?Q?/uSGuIceKpzdX+o/uBGFsbIB/OXHF+exgcaJ2Ws5yxk9p2VpKQr/8wH6QC8v?= =?us-ascii?Q?KM3PhHXKJGT4bB/5w5aCmGRKpGbDNKQVoRoLbBsH9HdlnJmHIVXewChekYPW?= =?us-ascii?Q?Qi3xSHqZKxBPjij061o=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 15:16:07.4615 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19f421e7-88b0-4a94-2667-08de1634eb5c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9493 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Under high system load, QSPI interrupts can be delayed or blocked on the target CPU, causing wait_for_completion_timeout() to report failure even though the hardware successfully completed the transfer. When a timeout occurs, check the QSPI_RDY bit in QSPI_TRANS_STATUS to determine if the hardware actually completed the transfer. If so, manually invoke the completion handler to process the transfer successfully instead of failing it. This distinguishes lost/delayed interrupts from real hardware timeouts, preventing unnecessary failures of transfers that completed successfully. Change-Id: I5431bf3c13cbf0d32462dd4c0d8e252572939bca Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 100 +++++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 20 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index 69defb4ffe49..cdc3cb7c01f9 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1048,6 +1048,49 @@ static void tegra_qspi_transfer_end(struct spi_devic= e *spi) tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); } =20 +static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi); +static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi); + +/** + * tegra_qspi_handle_timeout - Handle transfer timeout with hardware check + * @tqspi: QSPI controller instance + * + * When a timeout occurs but hardware has completed the transfer (interrupt + * was lost or delayed), manually trigger transfer completion processing. + * This avoids failing transfers that actually succeeded. + * + * Returns: 0 if transfer was completed, -ETIMEDOUT if real timeout + */ +static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) +{ + irqreturn_t ret; + u32 status; + + /* Check if hardware actually completed the transfer */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + if (!(status & QSPI_RDY)) + return -ETIMEDOUT; + + /* + * Hardware completed but interrupt was lost/delayed. Manually + * process the completion by calling the appropriate handler. + */ + dev_warn_ratelimited(tqspi->dev, + "QSPI interrupt timeout, but transfer complete\n"); + + /* Clear the transfer status */ + status =3D tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); + tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); + + /* Manually trigger completion handler */ + if (!tqspi->is_curr_dma_xfer) + ret =3D handle_cpu_based_xfer(tqspi); + else + ret =3D handle_dma_based_xfer(tqspi); + + return (ret =3D=3D IRQ_HANDLED) ? 0 : -EIO; +} + static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len) { u32 cmd_config =3D 0; @@ -1177,20 +1220,28 @@ static int tegra_qspi_combined_seq_xfer(struct tegr= a_qspi *tqspi, QSPI_DMA_TIMEOUT); =20 if (WARN_ON_ONCE(ret =3D=3D 0)) { - dev_err_ratelimited(tqspi->dev, - "QSPI Transfer failed with timeout\n"); - - /* Abort transfer by resetting pio/dma bit */ - if (tqspi->is_curr_dma_xfer) - tegra_qspi_dma_stop(tqspi); - else - tegra_qspi_pio_stop(tqspi); - - /* Reset controller if timeout happens */ - tegra_qspi_reset(tqspi); - - ret =3D -EIO; - goto exit; + /* + * Check if hardware completed the transfer + * even though interrupt was lost or delayed. + * If so, process the completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); + + /* Abort transfer by resetting pio/dma bit */ + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + else + tegra_qspi_pio_stop(tqspi); + + /* Reset controller if timeout happens */ + tegra_qspi_reset(tqspi); + + ret =3D -EIO; + goto exit; + } } =20 if (tqspi->tx_status || tqspi->rx_status) { @@ -1281,14 +1332,23 @@ static int tegra_qspi_non_combined_seq_xfer(struct = tegra_qspi *tqspi, ret =3D wait_for_completion_timeout(&tqspi->xfer_completion, QSPI_DMA_TIMEOUT); if (WARN_ON(ret =3D=3D 0)) { - dev_err(tqspi->dev, "transfer timeout\n"); + /* + * Check if hardware completed the transfer even though + * interrupt was lost or delayed. If so, process the + * completion and continue. + */ + ret =3D tegra_qspi_handle_timeout(tqspi); + if (ret < 0) { + /* Real timeout - clean up and fail */ + dev_err(tqspi->dev, "transfer timeout\n"); =20 - if (tqspi->is_curr_dma_xfer) - tegra_qspi_dma_stop(tqspi); + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); =20 - tegra_qspi_handle_error(tqspi); - ret =3D -EIO; - goto complete_xfer; + tegra_qspi_handle_error(tqspi); + ret =3D -EIO; + goto complete_xfer; + } } =20 if (tqspi->tx_status || tqspi->rx_status) { --=20 2.17.1