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Tue, 28 Oct 2025 08:15:32 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , Subject: [PATCH v3 2/3] spi: tegra210-quad: Refactor error handling into helper functions Date: Tue, 28 Oct 2025 15:15:14 +0000 Message-ID: <20251028151515.4142618-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251028151515.4142618-1-va@nvidia.com> References: <20251028151515.4142618-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CB:EE_|MW4PR12MB8611:EE_ X-MS-Office365-Filtering-Correlation-Id: e49f5c99-bfab-4919-0ebe-08de1634e7e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+3rNvYEOkmwEIV4jWAov1S05UtzONHXbNxQtbdf1bsPzqscU83/it/AdywhP?= =?us-ascii?Q?Z0WQY0tsesSrXPYCPk1lpDOr/3ZUb3I6WQoG/JsBJ0jDumNDauEKj2hf78Fq?= =?us-ascii?Q?4mjr3krGNu2rrh8p+bIP5fzC6wFhasXiRNPtlWAfkiMr5SuarINW9F/XRCfO?= =?us-ascii?Q?692W9uWQVvnp/1FKOL0/M0jkiIEOqx6vV5LRMn1aAw0t2Y79mSYjgfHJ8nd+?= =?us-ascii?Q?A67HRvM+HdNnNSlilmMor+y/VBgHHjuH9QhOENbwQ52DvN1GqMH6owqqHiSN?= =?us-ascii?Q?zWdFa4n6hCSNGG4i8q8hHOIqHQwGygTnsBwSIEk3z/4TrvhH0DcaYfu7vLY0?= =?us-ascii?Q?s3b8z9sfEWA1EyMOY9olF491eSZSXwPBToB5xzAsQmV+Mq6uwzcYiCfrdXGM?= =?us-ascii?Q?Qe3sKzi3BkFb+BA6U/yTRLi88j9+Ei2mo7DXndfjo+j8yHHkZBpgA0lpiVbr?= =?us-ascii?Q?QxJ3hInrEWEM7duNpl5RBAKqRev2Sm8UpCysbeQNL92GKu4XxqPExEj1dUoY?= =?us-ascii?Q?VJX2PpPYDV1T+oI2BuJW79wwJinT9V9s1NyE06Y2jHJDp4t7oQgyGsWHE9Po?= =?us-ascii?Q?JUO93gVyWpSDxcbLjUeKVohrSQ9BZIn4M17hWmckN+M9PDQ541Rfza8UfUOU?= =?us-ascii?Q?Z6SVCy0Jr5l0SPVrfauyQQk0OKi1L11jTMudF98g/AJa1kzs5CB98HKNAZwK?= =?us-ascii?Q?SqCoG0fPPEhf3MoF+hvJfLn5zxMdnrmDKc95jStWZUFlRoYmW3/tUwXYgDu9?= =?us-ascii?Q?4xFEHKCpd2dZSXhjz67uXhPxHPCOvzUT3wD0QWlhfQuoRSamoBpO6YyozN89?= =?us-ascii?Q?ShLLQ4TmKrpoeAOrCs7JUCn5OCbOncnyyDfnFUPuOQ/5QZfIW9QeSCQ2l7Og?= =?us-ascii?Q?mFr5Xacv1o4wy+LxzW5/XKI6Dzv56TSSAxZ8MLqL1ATLyioykMUwg0yHJzWK?= =?us-ascii?Q?wK8aUh6bBk2ZueZ3NsXOAY3oAfHeHrnWOT0H5f16/PU4so/efFA0e4SnzsbO?= =?us-ascii?Q?S+SmHtVJqRX9whazFG4LP+r8yjZfQjI54oChtjnVKVRe8JopJo6FuLPuC+h/?= =?us-ascii?Q?8ec7rpfVK2daVORS7gYop2FHxx+E5gZBxbk3YVI6BeI+EC6S9TNBaK3xM7KT?= =?us-ascii?Q?JjQ2/yvA1YMXXQjkDxktWZ6Ppc5CCj9eTk+k+PRS2UbA7SHjbsLyIbgLVqHy?= =?us-ascii?Q?u3xfli+h3Rj5utA2Q9ZwUAhpKVGkADF9t3UcMUzNsnuDRGGbBQtWNK8Uoaw/?= =?us-ascii?Q?T39vWBG5nebCaQ1xirvChfH/EGsxDJNOubZejP8dQ7WE2CgPL4NQ4X7jQH/5?= =?us-ascii?Q?J3IJfz+ECj2/KESSNHVimS5ZFIP6oa0Ab+NhlSEsGM6A00TO8sf2gWMhD2Id?= =?us-ascii?Q?i4n7GyP/ZwLF6581TEY0+qs4V/EsqocTHflzlweaBjbnKfe2OgmGPmJH9v14?= =?us-ascii?Q?R245ysnuukyIM9E8Rj778OQPacbL0fDg+tB5/Yt1wuutVkiuSoglRbZ7Nkce?= =?us-ascii?Q?4Qni2HmLVxkxBjd3RTec+nvjEF5gRXNzlvG13WPqNSVBoWhAFvC4nyS4iPnp?= =?us-ascii?Q?iIuEXzuse9tElLpLmqE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 15:16:01.6255 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e49f5c99-bfab-4919-0ebe-08de1634e7e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB8611 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract common cleanup code into dedicated helper functions to simplify the code and improve readability. This refactoring includes: - tegra_qspi_reset(): Device reset and interrupt cleanup - tegra_qspi_dma_stop(): DMA termination and disable - tegra_qspi_pio_stop(): PIO mode disable No functional changes. This is purely a code reorganization to prepare for improved timeout handling in subsequent patches. Change-Id: Iab526e0c19d160a39919ad98079b97c2da2dba94 Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 84 +++++++++++++++++---------------- 1 file changed, 44 insertions(+), 40 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-qua= d.c index d9ca3d7b082f..69defb4ffe49 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1019,17 +1019,22 @@ static void tegra_qspi_dump_regs(struct tegra_qspi = *tqspi) tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); } =20 -static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) +static void tegra_qspi_reset(struct tegra_qspi *tqspi) { - dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->sta= tus_reg); - tegra_qspi_dump_regs(tqspi); - tegra_qspi_flush_fifos(tqspi, true); if (device_reset(tqspi->dev) < 0) { dev_warn_once(tqspi->dev, "device reset failed\n"); tegra_qspi_mask_clear_irq(tqspi); } } =20 +static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) +{ + dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->sta= tus_reg); + tegra_qspi_dump_regs(tqspi); + tegra_qspi_flush_fifos(tqspi, true); + tegra_qspi_reset(tqspi); +} + static void tegra_qspi_transfer_end(struct spi_device *spi) { struct tegra_qspi *tqspi =3D spi_controller_get_devdata(spi->controller); @@ -1074,6 +1079,30 @@ static u32 tegra_qspi_addr_config(bool is_ddr, u8 bu= s_width, u8 len) return addr_config; } =20 +static void tegra_qspi_dma_stop(struct tegra_qspi *tqspi) +{ + u32 value; + + if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan) + dmaengine_terminate_all(tqspi->tx_dma_chan); + + if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan) + dmaengine_terminate_all(tqspi->rx_dma_chan); + + value =3D tegra_qspi_readl(tqspi, QSPI_DMA_CTL); + value &=3D ~QSPI_DMA_EN; + tegra_qspi_writel(tqspi, value, QSPI_DMA_CTL); +} + +static void tegra_qspi_pio_stop(struct tegra_qspi *tqspi) +{ + u32 value; + + value =3D tegra_qspi_readl(tqspi, QSPI_COMMAND1); + value &=3D ~QSPI_PIO; + tegra_qspi_writel(tqspi, value, QSPI_COMMAND1); +} + static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, struct spi_message *msg) { @@ -1081,7 +1110,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_= qspi *tqspi, struct spi_transfer *xfer; struct spi_device *spi =3D msg->spi; u8 transfer_phase =3D 0; - u32 cmd1 =3D 0, dma_ctl =3D 0; + u32 cmd1 =3D 0; int ret =3D 0; u32 address_value =3D 0; u32 cmd_config =3D 0, addr_config =3D 0; @@ -1150,39 +1179,16 @@ static int tegra_qspi_combined_seq_xfer(struct tegr= a_qspi *tqspi, if (WARN_ON_ONCE(ret =3D=3D 0)) { dev_err_ratelimited(tqspi->dev, "QSPI Transfer failed with timeout\n"); - if (tqspi->is_curr_dma_xfer) { - if ((tqspi->cur_direction & DATA_DIR_TX) && - tqspi->tx_dma_chan) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if ((tqspi->cur_direction & DATA_DIR_RX) && - tqspi->rx_dma_chan) - dmaengine_terminate_all(tqspi->rx_dma_chan); - } =20 /* Abort transfer by resetting pio/dma bit */ - if (!tqspi->is_curr_dma_xfer) { - cmd1 =3D tegra_qspi_readl - (tqspi, - QSPI_COMMAND1); - cmd1 &=3D ~QSPI_PIO; - tegra_qspi_writel - (tqspi, cmd1, - QSPI_COMMAND1); - } else { - dma_ctl =3D tegra_qspi_readl - (tqspi, - QSPI_DMA_CTL); - dma_ctl &=3D ~QSPI_DMA_EN; - tegra_qspi_writel(tqspi, dma_ctl, - QSPI_DMA_CTL); - } + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + else + tegra_qspi_pio_stop(tqspi); =20 /* Reset controller if timeout happens */ - if (device_reset(tqspi->dev) < 0) { - dev_warn_once(tqspi->dev, - "device reset failed\n"); - tegra_qspi_mask_clear_irq(tqspi); - } + tegra_qspi_reset(tqspi); + ret =3D -EIO; goto exit; } @@ -1276,12 +1282,10 @@ static int tegra_qspi_non_combined_seq_xfer(struct = tegra_qspi *tqspi, QSPI_DMA_TIMEOUT); if (WARN_ON(ret =3D=3D 0)) { dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer) { - if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan) - dmaengine_terminate_all(tqspi->tx_dma_chan); - if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan) - dmaengine_terminate_all(tqspi->rx_dma_chan); - } + + if (tqspi->is_curr_dma_xfer) + tegra_qspi_dma_stop(tqspi); + tegra_qspi_handle_error(tqspi); ret =3D -EIO; goto complete_xfer; --=20 2.17.1