From nobody Tue Feb 10 11:55:24 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF64E30BF75; Tue, 28 Oct 2025 13:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657996; cv=none; b=RPr3pNL+eWzL0K9hRWJmIsf6TQhwOIyvwr2l8mJNVFkCq2Qv1jw3FJKagr/3m8/L6lQJsB7jOIr1BQ28+iakwGs4LWzxIyE5sXlLDZVmHRjtNa4hiVNovdnO7PuMLk+YG6Yb4VFNREctGJ8ensenotHhboXp8NWRGU+4NUOji18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657996; c=relaxed/simple; bh=Z1G80aTVpf4dsetRPBUGBF+f/80CiJkW2RWciysFNKo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ENZynVKW51q7BzrrjwopnBAWd8DRdyouaqX6ybNQbsh7Ei+4simfGaa/pazeiO9O6pQv7D+QV0K4OxrsIuhz0YwxJYTpxvaCRt4QGbDV1owhkfiyTMJpFWxMi60+/ramSXODFFAQWdkoc9HPu/i4fRF/ZAPxxtqF7LgxZZHt9Is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: JY3ZNVwNQ96up63hsP66qA== X-CSE-MsgGUID: 3JKNtCklTpanPO7A2N2fPQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:34 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 16F684000A98; Tue, 28 Oct 2025 22:26:28 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 6/9] arm64: dts: renesas: r9a09g077: add OPP table Date: Tue, 28 Oct 2025 15:25:14 +0200 Message-ID: <20251028132519.1472676-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 33925f13ee86..bb030bfed090 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -24,6 +35,8 @@ cpu0: cpu@0 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu1: cpu@100 { @@ -32,6 +45,8 @@ cpu1: cpu@100 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu2: cpu@200 { @@ -40,6 +55,8 @@ cpu2: cpu@200 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu3: cpu@300 { @@ -48,6 +65,8 @@ cpu3: cpu@300 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 L3_CA55: cache-controller-0 { --=20 2.51.1