From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 878BB3043AF; Tue, 28 Oct 2025 13:26:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657968; cv=none; b=NIjN8agiwwWXp2K0J4TEaXpQ0sD7+/bZR4s8TaDWfZJqKmLEiE4iu7SU3qXIh8SHj+mB2TvlRWoavOLU03B+/mx0nOaQd6HZEOIQYD6Z2A6p2cvVqLAO181GpoH7AupzVnUR2sWwgPkylWbxf4kB8AOCThgv3/2mAjq9pdDQx5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657968; c=relaxed/simple; bh=6xR1CqeBEs/Q+Kx8rCapIX1QNf5Iaf7G/rYT9KdbNtk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K3z3CqXJHRNiGBmU3NjY26Q/euCq0eXTr5x+yEDzrwW9VNK3zk5zBaFzTnboJVAzNsHFUptSnFGr1tChCnwPVZobtL/fAEdqCF8o1EVFCinpyYqa/T5piLJJlDZ8rWrllcZndAxE4gnnW6n5nqShidjVouiiI+2ruCpIibvC2ks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: LMx6OuKjRnex6b/rroPNIw== X-CSE-MsgGUID: l+dSLG2PSCSkYJy8T7tzeQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:02 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 19CB140078A8; Tue, 28 Oct 2025 22:25:57 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 1/9] thermal: renesas: rzg3e: make reset optional Date: Tue, 28 Oct 2025 15:25:09 +0200 Message-ID: <20251028132519.1472676-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have a reset line. Prepare for them by making it optional. Signed-off-by: Cosmin Tanislav --- drivers/thermal/renesas/rzg3e_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index e66d73ca6752..86c10810e5bf 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -412,7 +412,7 @@ static int rzg3e_thermal_probe(struct platform_device *= pdev) "Clock rate %lu Hz too low (min %u Hz)\n", clk_get_rate(clk), TSU_MIN_CLOCK_RATE); =20 - priv->rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + priv->rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, = NULL); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get/deassert reset control\n"); --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4574C331A71; Tue, 28 Oct 2025 13:26:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657971; cv=none; b=fX6fW5IpTPKGjRFjxIgZO/9PuoZQ6Cz1i2LJ9hPrPtBy5mGZaipnwqD72PbxOnBLyL/RXYYlgfgHbhhT0VL+zPRLzv+M2GR0rtN6ieU4ZOjv0884yhCV1ZR/6T5dGuo5r8QeQPOKROgpCxFsZPLHw+1k6G2sHM/rsDniUQcCOCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657971; c=relaxed/simple; bh=n8VUk+HAyvgzqrBtN5M1tgw+YhUkS2U0lofZNtuNHLU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MEi4WKyDS4mFOJl9tGNz22r/qyPHrk8FFxVmggHAEHGa2QfcKomQltR/DCkQL/vMBUgmTnOrnnrFJ/VufGOjrwHs3M761h778CBpipftIe6cyX24CTv0uSGORPZzMiwvz6GcNx1kMQhjERt7liA8COYxTbc7Z3xswWWgdPYGTck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: O9iyJXsoTI+rks+u4kQNrQ== X-CSE-MsgGUID: d8NRmqNMRYC185hNEsUxbg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:09 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1AA5940078A8; Tue, 28 Oct 2025 22:26:03 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 2/9] thermal: renesas: rzg3e: make min and max temperature per-chip Date: Tue, 28 Oct 2025 15:25:10 +0200 Message-ID: <20251028132519.1472676-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have different minimum and maximum temperatures compared to the already supported RZ/G3E. Prepare for them by moving these into a chip-specific struct. Signed-off-by: Cosmin Tanislav --- drivers/thermal/renesas/rzg3e_thermal.c | 35 ++++++++++++++++--------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index 86c10810e5bf..3c9ff5e43d7e 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -62,8 +62,6 @@ #define TSU_SICR_CMPCLR BIT(1) =20 /* Temperature calculation constants from datasheet */ -#define TSU_TEMP_D (-41) -#define TSU_TEMP_E 126 #define TSU_CODE_MAX 0xFFF =20 /* Timing specifications from datasheet */ @@ -72,6 +70,11 @@ #define TSU_POLL_DELAY_US 10 /* Polling interval */ #define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ =20 +struct rzg3e_thermal_info { + int temp_d_mc; + int temp_e_mc; +}; + /** * struct rzg3e_thermal_priv - RZ/G3E TSU private data * @base: TSU register base @@ -79,6 +82,7 @@ * @syscon: regmap for calibration values * @zone: thermal zone device * @rstc: reset control + * @info: chip type specific information * @trmval0: calibration value 0 (b) * @trmval1: calibration value 1 (c) * @trim_offset: offset for trim registers in syscon @@ -90,6 +94,7 @@ struct rzg3e_thermal_priv { struct regmap *syscon; struct thermal_zone_device *zone; struct reset_control *rstc; + const struct rzg3e_thermal_info *info; u16 trmval0; u16 trmval1; u32 trim_offset; @@ -161,17 +166,17 @@ static void rzg3e_thermal_power_off(struct rzg3e_ther= mal_priv *priv) */ static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16= code) { - int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; - int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + const struct rzg3e_thermal_info *info =3D priv->info; s64 numerator, denominator; int temp_mc; =20 - numerator =3D (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0); + numerator =3D (info->temp_e_mc - info->temp_d_mc) * + (s64)(code - priv->trmval0); denominator =3D priv->trmval1 - priv->trmval0; =20 - temp_mc =3D div64_s64(numerator, denominator) + temp_d_mc; + temp_mc =3D div64_s64(numerator, denominator) + info->temp_d_mc; =20 - return clamp(temp_mc, temp_d_mc, temp_e_mc); + return clamp(temp_mc, info->temp_d_mc, info->temp_e_mc); } =20 /* @@ -180,13 +185,12 @@ static int rzg3e_thermal_code_to_temp(struct rzg3e_th= ermal_priv *priv, u16 code) */ static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int= temp_mc) { - int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; - int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + const struct rzg3e_thermal_info *info =3D priv->info; s64 numerator, denominator; s64 code; =20 - numerator =3D (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0); - denominator =3D temp_e_mc - temp_d_mc; + numerator =3D (temp_mc - info->temp_d_mc) * (priv->trmval1 - priv->trmval= 0); + denominator =3D info->temp_e_mc - info->temp_d_mc; =20 code =3D div64_s64(numerator, denominator) + priv->trmval0; =20 @@ -392,6 +396,8 @@ static int rzg3e_thermal_probe(struct platform_device *= pdev) return ret; platform_set_drvdata(pdev, priv); =20 + priv->info =3D device_get_match_data(dev); + priv->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); @@ -526,8 +532,13 @@ static const struct dev_pm_ops rzg3e_thermal_pm_ops = =3D { SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume) }; =20 +static const struct rzg3e_thermal_info rzg3e_thermal_info =3D { + .temp_d_mc =3D -41000, + .temp_e_mc =3D 126000, +}; + static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { - { .compatible =3D "renesas,r9a09g047-tsu" }, + { .compatible =3D "renesas,r9a09g047-tsu", .data =3D &rzg3e_thermal_info = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4ADCA30BF75; Tue, 28 Oct 2025 13:26:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657978; cv=none; b=bsJsp5dJq2hGLgoM8ev/mYjD+JbMwFDt2eRrCynIbHwaz2rfIN5/YCzjAGGbbq/YSUwlazDZxcWOz54XKJhemR493z4SqwIwcvBfhdFOs3AXArZOTnn9PAh5x2iN4bmb/7MVomV/7j9tZ20vWyd0doGi8Dg40f6CsPbz8cazjpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657978; c=relaxed/simple; bh=9RF1T7yST9lrzOKxOvms7vMVDWybCdjzCHgrLQi2fUM=; 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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 3/9] thermal: renesas: rzg3e: make calibration value retrieval per-chip Date: Tue, 28 Oct 2025 15:25:11 +0200 Message-ID: <20251028132519.1472676-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration data via SMC SIP calls. Prepare for them by moving the syscon usage into a single function, and placing it in the chip-specific struct. Rename the functions to match their functionality, and remove single-use variables from the private state. Also, move the calibration value mask into a macro. Signed-off-by: Cosmin Tanislav --- drivers/thermal/renesas/rzg3e_thermal.c | 62 +++++++++++++------------ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index 3c9ff5e43d7e..d2525ad3ffcc 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -70,7 +70,12 @@ #define TSU_POLL_DELAY_US 10 /* Polling interval */ #define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ =20 +#define TSU_TEMP_MASK GENMASK(11, 0) + +struct rzg3e_thermal_priv; + struct rzg3e_thermal_info { + int (*get_trim)(struct rzg3e_thermal_priv *priv); int temp_d_mc; int temp_e_mc; }; @@ -91,13 +96,11 @@ struct rzg3e_thermal_info { struct rzg3e_thermal_priv { void __iomem *base; struct device *dev; - struct regmap *syscon; struct thermal_zone_device *zone; struct reset_control *rstc; const struct rzg3e_thermal_info *info; u16 trmval0; u16 trmval1; - u32 trim_offset; struct mutex lock; }; =20 @@ -334,22 +337,8 @@ static const struct thermal_zone_device_ops rzg3e_tz_o= ps =3D { .set_trips =3D rzg3e_thermal_set_trips, }; =20 -static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv) +static int rzg3e_validate_calibration(struct rzg3e_thermal_priv *priv) { - u32 val; - int ret; - - /* Read calibration values from syscon */ - ret =3D regmap_read(priv->syscon, priv->trim_offset, &val); - if (ret) - return ret; - priv->trmval0 =3D val & GENMASK(11, 0); - - ret =3D regmap_read(priv->syscon, priv->trim_offset + 4, &val); - if (ret) - return ret; - priv->trmval1 =3D val & GENMASK(11, 0); - /* Validate calibration data */ if (!priv->trmval0 || !priv->trmval1 || priv->trmval0 =3D=3D priv->trmval1 || @@ -365,17 +354,30 @@ static int rzg3e_thermal_get_calibration(struct rzg3e= _thermal_priv *priv) return 0; } =20 -static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) +static int rzg3e_thermal_get_syscon_trim(struct rzg3e_thermal_priv *priv) { struct device_node *np =3D priv->dev->of_node; + struct regmap *syscon; u32 offset; + int ret; + u32 val; =20 - priv->syscon =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-tr= im", 1, &offset); - if (IS_ERR(priv->syscon)) - return dev_err_probe(priv->dev, PTR_ERR(priv->syscon), + syscon =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1= , &offset); + if (IS_ERR(syscon)) + return dev_err_probe(priv->dev, PTR_ERR(syscon), "Failed to parse renesas,tsu-trim\n"); =20 - priv->trim_offset =3D offset; + /* Read calibration values from syscon */ + ret =3D regmap_read(syscon, offset, &val); + if (ret) + return ret; + priv->trmval0 =3D val & TSU_TEMP_MASK; + + ret =3D regmap_read(syscon, offset + 4, &val); + if (ret) + return ret; + priv->trmval1 =3D val & TSU_TEMP_MASK; + return 0; } =20 @@ -402,11 +404,16 @@ static int rzg3e_thermal_probe(struct platform_device= *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); =20 - /* Parse device tree for trim register info */ - ret =3D rzg3e_thermal_parse_dt(priv); + ret =3D priv->info->get_trim(priv); if (ret) return ret; =20 + /* Validate calibration data */ + ret =3D rzg3e_validate_calibration(priv); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get valid calibration data\n"); + /* Get clock to verify frequency - clock is managed by power domain */ clk =3D devm_clk_get(dev, NULL); if (IS_ERR(clk)) @@ -423,12 +430,6 @@ static int rzg3e_thermal_probe(struct platform_device = *pdev) return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get/deassert reset control\n"); =20 - /* Get calibration data */ - ret =3D rzg3e_thermal_get_calibration(priv); - if (ret) - return dev_err_probe(dev, ret, - "Failed to get valid calibration data\n"); - /* Get comparison interrupt */ irq =3D platform_get_irq_byname(pdev, "adcmpi"); if (irq < 0) @@ -533,6 +534,7 @@ static const struct dev_pm_ops rzg3e_thermal_pm_ops =3D= { }; =20 static const struct rzg3e_thermal_info rzg3e_thermal_info =3D { + .get_trim =3D rzg3e_thermal_get_syscon_trim, .temp_d_mc =3D -41000, .temp_e_mc =3D 126000, }; --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AA3E8331A50; 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dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: nHY/pupiS/2S0gTU/RH5LA== X-CSE-MsgGUID: uuzbHpBUROSqoABQOVMDpw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:21 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 72F2A4005631; Tue, 28 Oct 2025 22:26:16 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 4/9] dt-bindings: thermal: r9a09g047-tsu: document RZ/T2H and RZ/N2H Date: Tue, 28 Oct 2025 15:25:12 +0200 Message-ID: <20251028132519.1472676-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. Signed-off-by: Cosmin Tanislav Acked-by: Conor Dooley --- Notes: V2: * merge two items into a single enum .../thermal/renesas,r9a09g047-tsu.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml index 8d3f3c24f0f2..e0ce7d9da877 100644 --- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -16,7 +16,13 @@ description: =20 properties: compatible: - const: renesas,r9a09g047-tsu + oneOf: + - enum: + - renesas,r9a09g047-tsu # RZ/G3E + - renesas,r9a09g077-tsu # RZ/T2H + - items: + - const: renesas,r9a09g087-tsu # RZ/N2H + - const: renesas,r9a09g077-tsu # RZ/T2H =20 reg: maxItems: 1 @@ -59,12 +65,21 @@ required: - compatible - reg - clocks - - resets - power-domains - interrupts - interrupt-names - "#thermal-sensor-cells" - - renesas,tsu-trim + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-tsu + then: + required: + - resets + - renesas,tsu-trim =20 additionalProperties: false =20 --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9E1C530BF75; Tue, 28 Oct 2025 13:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657989; cv=none; b=mNXIJvMgPVaJogBsW5lGGjUDOMFfFrT+qAHfveWx+dy1Sc8G0BohyYOfpWZH7qfAxhoXKFpKP2Kz4GEvWyFz4j2TEUT4l4gKyw3G8g3vDbCags2RXLF8DCNVxn6UcQ1fx7z//7TXhEkai6IwM6KgpNLCnu/Hkt3T5PpaV8m7l8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657989; c=relaxed/simple; bh=pySrbb/+7a4yO2DdQjXcUKySBCXBK1J6Rn2aYjZ+akU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q3kFLFTyVbe9iimFNiM4sEk8Ob3W9HzJmfAbyactPjdVCIGqSFGHWF7n4Dw4GSdTardmmKJ6jX6Psg9W5rBbs1+bOQXAM31T/sanJ/eWCoQ51T0HNnMdOxvlJFSfX2+PdTKFsaDLSBjzACppeNBygUL2QgxBFiyVrO6oKi03xKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 0oWcvjanTH2f8hvLpqmiAQ== X-CSE-MsgGUID: D75B3YcAQDSqhZ3kwp3LCw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:27 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7E6BA4000A98; Tue, 28 Oct 2025 22:26:22 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 5/9] thermal: renesas: rzg3e: add support for RZ/T2H and RZ/N2H Date: Tue, 28 Oct 2025 15:25:13 +0200 Message-ID: <20251028132519.1472676-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration via SMC SIP and do not have a reset for the TSU peripheral, and use different minimum and maximum temperature values compared to the already supported RZ/G3E. Although the calibration data is stored in an OTP memory, the OTP itself is not memory-mapped, access to it is done through an OTP controller. The OTP controller is only accessible from the secure world, but the temperature calibration data stored in the OTP is exposed via SMC. Add support for retrieving the calibration data using arm_smcc_smc(). Add a compatible for RZ/T2H, RZ/N2H can use it as a fallback. Signed-off-by: Cosmin Tanislav --- drivers/thermal/renesas/rzg3e_thermal.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index d2525ad3ffcc..efd09c35b216 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -72,6 +72,10 @@ =20 #define TSU_TEMP_MASK GENMASK(11, 0) =20 +#define RZ_SIP_SVC_GET_SYSTSU 0x82000022 +#define OTP_TSU_REG_ADR_TEMPHI 0x01DC +#define OTP_TSU_REG_ADR_TEMPLO 0x01DD + struct rzg3e_thermal_priv; =20 struct rzg3e_thermal_info { @@ -381,6 +385,21 @@ static int rzg3e_thermal_get_syscon_trim(struct rzg3e_= thermal_priv *priv) return 0; } =20 +static int rzg3e_thermal_get_smc_trim(struct rzg3e_thermal_priv *priv) +{ + struct arm_smccc_res local_res; + + arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPLO, + 0, 0, 0, 0, 0, 0, &local_res); + priv->trmval0 =3D local_res.a0 & TSU_TEMP_MASK; + + arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPHI, + 0, 0, 0, 0, 0, 0, &local_res); + priv->trmval1 =3D local_res.a0 & TSU_TEMP_MASK; + + return 0; +} + static int rzg3e_thermal_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -539,8 +558,15 @@ static const struct rzg3e_thermal_info rzg3e_thermal_i= nfo =3D { .temp_e_mc =3D 126000, }; =20 +static const struct rzg3e_thermal_info rzt2h_thermal_info =3D { + .get_trim =3D rzg3e_thermal_get_smc_trim, + .temp_d_mc =3D -40000, + .temp_e_mc =3D 125000, +}; + static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { { .compatible =3D "renesas,r9a09g047-tsu", .data =3D &rzg3e_thermal_info = }, + { .compatible =3D "renesas,r9a09g077-tsu", .data =3D &rzt2h_thermal_info = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF64E30BF75; Tue, 28 Oct 2025 13:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657996; cv=none; b=RPr3pNL+eWzL0K9hRWJmIsf6TQhwOIyvwr2l8mJNVFkCq2Qv1jw3FJKagr/3m8/L6lQJsB7jOIr1BQ28+iakwGs4LWzxIyE5sXlLDZVmHRjtNa4hiVNovdnO7PuMLk+YG6Yb4VFNREctGJ8ensenotHhboXp8NWRGU+4NUOji18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761657996; c=relaxed/simple; bh=Z1G80aTVpf4dsetRPBUGBF+f/80CiJkW2RWciysFNKo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ENZynVKW51q7BzrrjwopnBAWd8DRdyouaqX6ybNQbsh7Ei+4simfGaa/pazeiO9O6pQv7D+QV0K4OxrsIuhz0YwxJYTpxvaCRt4QGbDV1owhkfiyTMJpFWxMi60+/ramSXODFFAQWdkoc9HPu/i4fRF/ZAPxxtqF7LgxZZHt9Is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: JY3ZNVwNQ96up63hsP66qA== X-CSE-MsgGUID: 3JKNtCklTpanPO7A2N2fPQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:34 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 16F684000A98; Tue, 28 Oct 2025 22:26:28 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 6/9] arm64: dts: renesas: r9a09g077: add OPP table Date: Tue, 28 Oct 2025 15:25:14 +0200 Message-ID: <20251028132519.1472676-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 33925f13ee86..bb030bfed090 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -24,6 +35,8 @@ cpu0: cpu@0 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu1: cpu@100 { @@ -32,6 +45,8 @@ cpu1: cpu@100 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu2: cpu@200 { @@ -40,6 +55,8 @@ cpu2: cpu@200 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu3: cpu@300 { @@ -48,6 +65,8 @@ cpu3: cpu@300 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 L3_CA55: cache-controller-0 { --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4A6F73328E3; Tue, 28 Oct 2025 13:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658002; cv=none; b=Or4lHtJtV4ZNZeTy/zR9nmxR7Yz890RgekI0lB8ChSHsPz0peK+EhhvkZRkmtG0acZRNasdd6Y1QrJPg8GJxoZMrKfjARehlD+bqV52FLORdtBm4YzfUjycExGYeemdkLQLxUSfTTglblOi4Gpr6JSwkTdzaaIYoWLy5ZU+wxCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658002; c=relaxed/simple; bh=AJlXX0cR7gtXKfuWOpulIby+SGUe6pqRc1ja36cvJ8s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G9vBpR5RybCg531v8AJ1hK0XNiLi3AAktiG3Kdu3G95HrfrPj/sNRd/qHey8gwOFyPnBfJdXewUm6yfKYLKIIkbKK08iYUvj/CE/TVqb5dQb85Hz1Kcf/nEl5kvKSl1jLqnZrbXSaniOUBDkdcwpATSGEvWoj98xDAr61RMNjbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: dfJ6FSlcRdeuZ78Lez5B1A== X-CSE-MsgGUID: T9myEXCdTrq1jNJOLPvbDw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:40 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 235E940078A8; Tue, 28 Oct 2025 22:26:34 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 7/9] arm64: dts: renesas: r9a09g087: add OPP table Date: Tue, 28 Oct 2025 15:25:15 +0200 Message-ID: <20251028132519.1472676-8-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OPP table for RZ/N2H SoC. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index b7685449a7d7..5eef8c18037e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -14,6 +14,17 @@ / { #size-cells =3D <2>; interrupt-parent =3D <&gic>; =20 + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -24,6 +35,8 @@ cpu0: cpu@0 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu1: cpu@100 { @@ -32,6 +45,8 @@ cpu1: cpu@100 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu2: cpu@200 { @@ -40,6 +55,8 @@ cpu2: cpu@200 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu3: cpu@300 { @@ -48,6 +65,8 @@ cpu3: cpu@300 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 L3_CA55: cache-controller-0 { --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F0B8E32A3E1; Tue, 28 Oct 2025 13:26:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658010; cv=none; b=Karb2cSeyWVqF6nLjNclWVokRvY650bE6bukCuHhy5jEtbL8/NlJOY5P0+Q0/D2uPdT0tXTJC/kZAEYUai2a3vKSsnoeWK5MhnPD3z18XyfSB5A6QT5KiDlL0yRdZDwXKJxnPWxPU6eqcPfL2eS4x792IFBEtUEjaM+85POzo1o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658010; c=relaxed/simple; bh=r3sK2rko+uhp2lYK3ThCS0k/b/zLublBCf/EgXNyAbk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fbLMwoHoiJb5qINhh/PaLktRsxO4tOlR9DEv0Fco7pjbTfzhg6kw7ZGBdofB6WG/XypVgPSedgt4SE9M4Xa/sAJTZYWGfyLHAUFOqHCOOhoWKM14bJ7pdOQS35gR69yZK4Tg3TCr8Eg8WKvCKIXSldAVhLXW7CwJs4bmU+n6Cm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: SORHQA/MTxOwomu8aVQa/w== X-CSE-MsgGUID: 3yZyCF1xQB+GV7zAroGNRA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:46 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2CC584005631; Tue, 28 Oct 2025 22:26:40 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 8/9] arm64: dts: renesas: r9a09g077: add TSU and thermal zones support Date: Tue, 28 Oct 2025 15:25:16 +0200 Message-ID: <20251028132519.1472676-9-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index bb030bfed090..42ee9f299837 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -36,6 +36,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -46,6 +47,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -56,6 +58,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -66,6 +69,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -244,6 +248,17 @@ wdt5: watchdog@80083400 { status =3D "disabled"; }; =20 + tsu: thermal@80086000 { + compatible =3D "renesas,r9a09g077-tsu"; + reg =3D <0 0x80086000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 307>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + }; + i2c0: i2c@80088000 { compatible =3D "renesas,riic-r9a09g077"; reg =3D <0 0x80088000 0 0x400>; @@ -844,6 +859,37 @@ sdhi1_vqmmc: vqmmc-regulator { }; }; =20 + thermal-zones { + cpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution =3D <1024>; + }; + }; + + trips { + target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor_crit: sensor-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + stmmac_axi_setup: stmmac-axi-config { snps,lpi_en; snps,wr_osr_lmt =3D <0xf>; --=20 2.51.1 From nobody Mon Feb 9 07:57:41 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6B00331A50; Tue, 28 Oct 2025 13:26:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658016; cv=none; b=OrLWsDF0ERkscPl2fS/4ywZJzSLvLeF64SkN44pmci6jgm5eA9pAjHjTduqvGyBRkw80iziKgwltEwUBDsvdDcTw5iGcrpqHLl8XGSPRcDp3Syn4JScW7bzcrNXYjygKYBbDRKngGqV0eZJvPxw/+sr34o29eqrZvHLD6cR9cEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761658016; c=relaxed/simple; bh=V4L/H30OuBlemwDlVM8ADYwYLpVGXZKR1xdAcxgluVg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PRZa9LgDKG+AuRbJGgX8ESaTZg31o5iZM34SwFmLqWzPziCaZs2CK4WreGeyBp9pdhsWEdqnrwLJhn9vs1jq3i7jYpR9944P3drMF+GP4gGjITlUAPRaeL9hFFKvhT/kMWd9PMjdtZWOuJJwbWgRGNjl6np7F+1DJDJratjsdPE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: I4wMIvZwTSGVxiOVXjc90Q== X-CSE-MsgGUID: BYQX+M04TrKSPZh6O30p3Q== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Oct 2025 22:26:53 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.5]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A3F2C40078A8; Tue, 28 Oct 2025 22:26:48 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 9/9] arm64: dts: renesas: r9a09g087: add TSU and thermal zones support Date: Tue, 28 Oct 2025 15:25:17 +0200 Message-ID: <20251028132519.1472676-10-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251028132519.1472676-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/N2H (R9A09G087) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 5eef8c18037e..db117b6f75a1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -36,6 +36,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -46,6 +47,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -56,6 +58,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -66,6 +69,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -244,6 +248,17 @@ wdt5: watchdog@80083400 { status =3D "disabled"; }; =20 + tsu: thermal@80086000 { + compatible =3D "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu"; + reg =3D <0 0x80086000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 307>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + }; + i2c0: i2c@80088000 { compatible =3D "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg =3D <0 0x80088000 0 0x400>; @@ -844,6 +859,37 @@ sdhi1_vqmmc: vqmmc-regulator { }; }; =20 + thermal-zones { + cpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution =3D <1024>; + }; + }; + + trips { + target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor_crit: sensor-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + stmmac_axi_setup: stmmac-axi-config { snps,lpi_en; snps,wr_osr_lmt =3D <0xf>; --=20 2.51.1