From nobody Fri Dec 19 10:41:13 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A723D242D99 for ; Tue, 28 Oct 2025 07:36:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761636967; cv=none; b=IB0bOh7xyTWYWALhWtulPCNOa+2XwgFKNxcBmILkcCgB8UIjNDyqRtsrjIkCLxBKJnF4NQFbazqOrJA1qwOAYvGzLH7AepM0oj9Sa52SRoaPySPRh81IkpHQ2tDJB7dz4lED0xkqOox8ZlOILldpKhcVAWgBcoBAZPFvaBjX46M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761636967; c=relaxed/simple; bh=BHS75REOAEnpLu0LmL2Q+i5DFOwEhuvPGHDexpSYMB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UPc9ju2CHe+yw90V3w0nlAaDGgXYTMXnrqto4DE/PlGADKwfH5xR/6BgjFntvTaSZIyP3qqJuLVNLnFOY/5E2a2KsZ1LJJf+JITQcJPROWtJGxj5GFq8qDjqIhECT0tMoW1nIgJ2yUbdAavt1NBImcPFee9+CtlyeUuh8M9ncsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CMnUw3UB; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CMnUw3UB" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 2F77D4E41391; Tue, 28 Oct 2025 07:36:04 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id F2673606AB; Tue, 28 Oct 2025 07:36:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6D631102F2514; Tue, 28 Oct 2025 08:35:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761636962; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=K9NMURKSRoyeMVqqgVeeGVItJOP1Hv8pxe6jBsnxXTg=; b=CMnUw3UBO9cRxyNZe7elGCFZfhaL7szZxONp7LtNOFGp9Okwc2B3fqeZZR9KMjHT/7uGoy Bl1s1X5YyL2RtF6Zz0EpueLVE+0MHBxqf4xxYpSoEzbXnHA1mlyQUW2Slm9NExXO8eRyp9 nZVdZ3GCr+a8IKWF/f91nDB0WniEg1se/59cuZpzvNua++bqO4rzPPk4StrTW440LzUN4r ZzK2goZmTz18YQltYF51cpFHwbIRQy6g411Rz/Gz8lMCS+y057Opl8qOzF0p6OOuoLv+Lu YxgKo7RIOEaAHpFldAe2VYhAGL6pnvcAgu7lq3uRroC8eeOYM1hoFQMP75sQYw== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud , Conor Dooley Subject: [PATCH v4 01/16] dt-bindings: mtd: sunxi: Add H616 compatible Date: Tue, 28 Oct 2025 08:34:54 +0100 Message-ID: <20251028073534.526992-2-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 NAND controller is quite different from the A10 and A23 ones, some registers offset changed, and some new one are introduced. Also, the DMA handling is different (it uses chained descriptors) So, introduce a new compatible to represent this version of the IP. Acked-by: Conor Dooley Signed-off-by: Richard Genoud --- .../mtd/allwinner,sun4i-a10-nand.yaml | 41 +++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand= .yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml index 054b6b8bf9b9..9d061e2216cb 100644 --- a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Allwinner A10 NAND Controller =20 -allOf: - - $ref: nand-controller.yaml - maintainers: - Chen-Yu Tsai - Maxime Ripard @@ -18,6 +15,8 @@ properties: enum: - allwinner,sun4i-a10-nand - allwinner,sun8i-a23-nand-controller + - allwinner,sun50i-h616-nand-controller + reg: maxItems: 1 =20 @@ -25,14 +24,20 @@ properties: maxItems: 1 =20 clocks: + minItems: 2 items: - description: Bus Clock - description: Module Clock + - description: ECC Clock + - description: MBus Clock =20 clock-names: + minItems: 2 items: - const: ahb - const: mod + - const: ecc + - const: mbus =20 resets: maxItems: 1 @@ -85,6 +90,36 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-nand + - allwinner,sun8i-a23-nand-controller + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-nand-controller + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + examples: - | #include --=20 2.47.3 From nobody Fri Dec 19 10:41:13 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE4152798E5 for ; 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bh=LCUJ5/saowpQPNFVp04KkuwgBr8Y1U1BrCTh+Ah/naI=; b=VGEOWZU7eCmMm50snDJGfubeXsxXWnafPqY4CgHnMnN0tNBfXTx91OLn8Z/qarILMzrw2e lnjmGe7H+skBJ8BigllTbFpPvMurZfKkw5ykkXeBAwEHAMEl9WaChjZPNAO72EOrfsfXgo jRxzU/Z9gNEdkHZ4JgYi18OKpoddxEAsc15kCMNfEoOrdoW2phPYlyVGe07EtPU4RTNY0Z k+cA/aYZ0Xqs0n1V3lPX1qgO3kem6qNXrCusKwnCVsjLKCz+t/iN1F8QAICMM2Uof1IneJ tPQt8O4PF4TV7WnB/+1Tbts/313lhAkllRacw9cD8Xneg3Gmmfe4npNZvlB5KA== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 02/16] mtd: rawnand: sunxi: Remove superfluous register readings Date: Tue, 28 Oct 2025 08:34:55 +0100 Message-ID: <20251028073534.526992-3-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The register NFC_REG_ECC_CTL was read twice and the result was not used, then a third time with a mask applied. Removing those calls didn't change the behavior. Tested on H616 SoC, scrambling enabled. Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index f6a8e8ae819d..cb12179b63a5 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -623,13 +623,12 @@ static void sunxi_nfc_randomizer_config(struct nand_c= hip *nand, int page, bool ecc) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); - u32 ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL); + u32 ecc_ctl; u16 state; =20 if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL); state =3D sunxi_nfc_randomizer_state(nand, page, ecc); ecc_ctl =3D readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK; writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL); --=20 2.47.3 From nobody Fri Dec 19 10:41:13 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CD4F1F4E34; Tue, 28 Oct 2025 07:36:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761636971; cv=none; b=oWYMrfr6LMj0n9g3Byk9UjafhBXvYD3ysc92XR5P+v/+CPXFxyZUPWRAgAKaO8l0HBdpoYhuSsjhClob5OKysDG0NIosKGGFcZG/h4QRDEGa7EB2IV8e90QjgXoFQlgq2tWpaaQc9ykKMx7N4WW5rUrMFXgucIErQCg/j9je5C8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761636971; c=relaxed/simple; bh=DaRXIJ/7X39HdIvMEe7DqEcRKRrB/YJqaKCw71E56G8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GZYXp7a/B0BpCZW+UlserHwlrsdSG/UdYNkyF9bJZPABtaBduSv8WlziWOhCN92doA9BCbxhcZfmFB+5BhtHIdkzd9+4veirGaaG2bx/zBNGpWuyoRhZ/kR6H5mhA3HS9LkUFl0xQV1EMQiHhLWlogqyyS3bZgvkY5JF95NrnM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=eym+dPNl; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eym+dPNl" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id B4174C0BE9B; Tue, 28 Oct 2025 07:35:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EED5C606AB; Tue, 28 Oct 2025 07:36:07 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 56C2D102F2511; Tue, 28 Oct 2025 08:36:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1761636966; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=u3S0UfkjniUygC6M3bNMepbhcEH6bkQ5H1MIMTWuTtY=; b=eym+dPNld4TdDRGXchdpD/HlCEzNadlm892YSWWyd9eY4MLl4gVFuv9voGbOGnnvDqEezj CWZSRylSKCnSWGKo8bBzM9VXx+ZZHX/6nJmPwnz3NyzprK+i16BdOl9yeLc6ZBb4YDexOk nFHf6jFQa5cWRtz+RGsadFyvzj9CiV9Rt3BoEg6v1ScEydT736gqQst1nKpFUInKo1bQIT zElM65Jz1DptBTA0ewy/PrlEcexZ5xV3pJbclE3VhCw9EvlNS5WGPu0k7fr1r4P+Pw5t8a 1Pml/PjmzFqhnxpkhGIxj8zBtAseZZ9vsWaQ0IyOPFTweNWd7C0V9tj2RVIWbg== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 03/16] mtd: rawnand: sunxi: Replace hard coded value by a define Date: Tue, 28 Oct 2025 08:34:56 +0100 Message-ID: <20251028073534.526992-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The user data length (4) used all over the code hard coded. And sometimes, it's not that trivial to know that it's the user data length and not something else. Moreover, for the H6/H616 this value is no more fixed by hardware, but could be modified. Using a define here makes the code more readable. Suggested-by: Miquel Raynal Signed-off-by: Richard Genoud Acked-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 63 ++++++++++++++++++------------- 1 file changed, 37 insertions(+), 26 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index cb12179b63a5..f24e8d2083f8 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -157,6 +157,17 @@ =20 #define NFC_MAX_CS 7 =20 +/* + * On A10/A23, this is the size of the NDFC User Data Register, containing= the + * mandatory user data bytes following the ECC for each ECC step. + * Thus, for each ECC step, we need the ECC bytes + USER_DATA_SZ. + * Those bits are currently unsused, and kept as default value 0xffffffff. + * + * On H6/H616, this size became configurable, from 0 bytes to 32, via the + * USER_DATA_LEN registers. + */ +#define USER_DATA_SZ 4 + /** * struct sunxi_nand_chip_sel - stores information related to NAND Chip Se= lect * @@ -729,7 +740,7 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct = nand_chip *nand, bool bbm, int page) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); - u8 user_data[4]; + u8 user_data[USER_DATA_SZ]; =20 /* Randomize the Bad Block Marker. */ if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) { @@ -781,7 +792,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, memset(data, pattern, ecc->size); =20 if (oob) - memset(oob, pattern, ecc->bytes + 4); + memset(oob, pattern, ecc->bytes + USER_DATA_SZ); =20 return 0; } @@ -826,7 +837,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, if (ret) return ret; =20 - *cur_off =3D oob_off + ecc->bytes + 4; + *cur_off =3D oob_off + ecc->bytes + USER_DATA_SZ; =20 ret =3D sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, readl(nfc->regs + NFC_REG_ECC_ST), @@ -846,11 +857,11 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_ch= ip *nand, memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size); =20 - nand_change_read_column_op(nand, oob_off, oob, ecc->bytes + 4, - false); + nand_change_read_column_op(nand, oob_off, oob, + ecc->bytes + USER_DATA_SZ, false); =20 - ret =3D nand_check_erased_ecc_chunk(data, ecc->size, - oob, ecc->bytes + 4, + ret =3D nand_check_erased_ecc_chunk(data, ecc->size, oob, + ecc->bytes + USER_DATA_SZ, NULL, 0, ecc->strength); if (ret >=3D 0) raw_mode =3D 1; @@ -860,7 +871,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, if (oob_required) { nand_change_read_column_op(nand, oob_off, NULL, 0, false); - sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4, + sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + USER_DATA_SZ, true, page); =20 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0, @@ -954,7 +965,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf =20 for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; bool erased; @@ -971,7 +982,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf /* TODO: use DMA to retrieve OOB */ nand_change_read_column_op(nand, mtd->writesize + oob_off, - oob, ecc->bytes + 4, false); + oob, ecc->bytes + USER_DATA_SZ, false); =20 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i, !i, page); @@ -986,7 +997,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf if (status & NFC_ECC_ERR_MSK) { for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1006,10 +1017,10 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct = nand_chip *nand, uint8_t *buf /* TODO: use DMA to retrieve OOB */ nand_change_read_column_op(nand, mtd->writesize + oob_off, - oob, ecc->bytes + 4, false); + oob, ecc->bytes + USER_DATA_SZ, false); =20 - ret =3D nand_check_erased_ecc_chunk(data, ecc->size, - oob, ecc->bytes + 4, + ret =3D nand_check_erased_ecc_chunk(data, ecc->size, oob, + ecc->bytes + USER_DATA_SZ, NULL, 0, ecc->strength); if (ret >=3D 0) @@ -1062,7 +1073,7 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, if (ret) return ret; =20 - *cur_off =3D oob_off + ecc->bytes + 4; + *cur_off =3D oob_off + ecc->bytes + USER_DATA_SZ; =20 return 0; } @@ -1073,7 +1084,7 @@ static void sunxi_nfc_hw_ecc_write_extra_oob(struct n= and_chip *nand, { struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_ecc_ctrl *ecc =3D &nand->ecc; - int offset =3D ((ecc->bytes + 4) * ecc->steps); + int offset =3D ((ecc->bytes + USER_DATA_SZ) * ecc->steps); int len =3D mtd->oobsize - offset; =20 if (len <=3D 0) @@ -1106,7 +1117,7 @@ static int sunxi_nfc_hw_ecc_read_page(struct nand_chi= p *nand, uint8_t *buf, =20 for (i =3D 0; i < ecc->steps; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); u8 *data =3D buf + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1165,7 +1176,7 @@ static int sunxi_nfc_hw_ecc_read_subpage(struct nand_= chip *nand, for (i =3D data_offs / ecc->size; i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); u8 *data =3D bufpoi + data_off; u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1219,7 +1230,7 @@ static int sunxi_nfc_hw_ecc_write_page(struct nand_ch= ip *nand, =20 for (i =3D 0; i < ecc->steps; i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); const u8 *data =3D buf + data_off; const u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1257,7 +1268,7 @@ static int sunxi_nfc_hw_ecc_write_subpage(struct nand= _chip *nand, for (i =3D data_offs / ecc->size; i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) { int data_off =3D i * ecc->size; - int oob_off =3D i * (ecc->bytes + 4); + int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); const u8 *data =3D buf + data_off; const u8 *oob =3D nand->oob_poi + oob_off; =20 @@ -1296,7 +1307,7 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nan= d_chip *nand, goto pio_fallback; =20 for (i =3D 0; i < ecc->steps; i++) { - const u8 *oob =3D nand->oob_poi + (i * (ecc->bytes + 4)); + const u8 *oob =3D nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ)); =20 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); } @@ -1566,7 +1577,7 @@ static int sunxi_nand_ooblayout_ecc(struct mtd_info *= mtd, int section, if (section >=3D ecc->steps) return -ERANGE; =20 - oobregion->offset =3D section * (ecc->bytes + 4) + 4; + oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ) + 4; oobregion->length =3D ecc->bytes; =20 return 0; @@ -1600,10 +1611,10 @@ static int sunxi_nand_ooblayout_free(struct mtd_inf= o *mtd, int section, if (section =3D=3D ecc->steps && ecc->engine_type =3D=3D NAND_ECC_ENGINE_= TYPE_ON_HOST) return -ERANGE; =20 - oobregion->offset =3D section * (ecc->bytes + 4); + oobregion->offset =3D section * (ecc->bytes + USER_DATA_SZ); =20 if (section < ecc->steps) - oobregion->length =3D 4; + oobregion->length =3D USER_DATA_SZ; else oobregion->length =3D mtd->oobsize - oobregion->offset; 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charset="utf-8" H6/H616 has more ECC strenghts than A10/A23. Move the ECC strenghts array to sunxi_nfc_caps to make it ready for H6/H616 support. No functional change. Reviewed-by: Chen-Yu Tsai Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index f24e8d2083f8..89115a8f0718 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -224,11 +224,15 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(s= truct nand_chip *nand) * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register * @dma_maxburst: DMA maxburst + * @ecc_strengths: Available ECC strengths array + * @nstrengths: Size of @ecc_strengths */ struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; unsigned int dma_maxburst; + const u8 *ecc_strengths; + unsigned int nstrengths; }; =20 /** @@ -1630,9 +1634,9 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, struct nand_ecc_ctrl *ecc, struct device_node *np) { - static const u8 strengths[] =3D { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; struct sunxi_nand_chip *sunxi_nand =3D to_sunxi_nand(nand); struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); + const u8 *strengths =3D nfc->caps->ecc_strengths; struct mtd_info *mtd =3D nand_to_mtd(nand); struct nand_device *nanddev =3D mtd_to_nanddev(mtd); int nsectors; @@ -1656,7 +1660,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, =20 ecc->strength =3D bytes * 8 / fls(8 * ecc->size); =20 - for (i =3D 0; i < ARRAY_SIZE(strengths); i++) { + for (i =3D 0; i < nfc->caps->nstrengths; i++) { if (strengths[i] > ecc->strength) break; } @@ -1677,7 +1681,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, } =20 /* Add ECC info retrieval from DT */ - for (i =3D 0; i < ARRAY_SIZE(strengths); i++) { + for (i =3D 0; i < nfc->caps->nstrengths; i++) { if (ecc->strength <=3D strengths[i]) { /* * Update ecc->strength value with the actual strength @@ -1688,7 +1692,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, } } =20 - if (i >=3D ARRAY_SIZE(strengths)) { + if (i >=3D nfc->caps->nstrengths) { dev_err(nfc->dev, "unsupported strength\n"); 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charset="utf-8" The H6/H616 ECC_ERR_CNT register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps No functional change. Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 89115a8f0718..d877c20c203d 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -46,7 +46,8 @@ #define NFC_REG_ECC_CTL 0x0034 #define NFC_REG_ECC_ST 0x0038 #define NFC_REG_DEBUG 0x003C -#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3) +#define NFC_REG_A10_ECC_ERR_CNT 0x0040 +#define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID 0x00A4 @@ -223,6 +224,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register + * @reg_ecc_err_cnt: ECC error counter register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -230,6 +232,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; + unsigned int reg_ecc_err_cnt; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -801,7 +804,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, return 0; } =20 - tmp =3D readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step)); + tmp =3D readl(nfc->regs + NFC_REG_ECC_ERR_CNT(nfc, step)); =20 return NFC_ECC_ERR_CNT(step, tmp); } @@ -2188,6 +2191,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { =20 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2196,6 +2200,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AB6A2D3733 for ; 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charset="utf-8" The H6/H616 USER_DATA register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps No functional change. Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index d877c20c203d..89495d786293 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -48,7 +48,8 @@ #define NFC_REG_DEBUG 0x003C #define NFC_REG_A10_ECC_ERR_CNT 0x0040 #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) -#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) +#define NFC_REG_A10_USER_DATA 0x0050 +#define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 @@ -225,6 +226,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * through MBUS on A23/A33 needs extra configuration. * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register + * @reg_user_data: User data register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -233,6 +235,7 @@ struct sunxi_nfc_caps { bool has_mdma; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; + unsigned int reg_user_data; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -734,8 +737,7 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct = nand_chip *nand, u8 *oob, { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); =20 - sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)), - oob); + sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(nfc, step)= ), oob); =20 /* De-randomize the Bad Block Marker. */ if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) @@ -757,7 +759,7 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct = nand_chip *nand, } =20 writel(sunxi_nfc_buf_to_user_data(oob), - nfc->regs + NFC_REG_USER_DATA(step)); + nfc->regs + NFC_REG_USER_DATA(nfc, step)); } =20 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand, @@ -2192,6 +2194,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_A10_USER_DATA, .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2201,6 +2204,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .has_mdma =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_A10_USER_DATA, .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B33452D594F for ; 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bh=8eJPK7PbpIXPqb8tR+4LMkZq3MDAIiNfkxw7nAa5m1M=; b=bniHsEY5nfohnlAQHs19DEcpf/y7Y4Yhj+bZx11SlvO59KIBw/DvsTKH/xyrHmhWimUzSj IDZGaLSh1XTID02gwB8mAY3nODuTm/hnmTugZgpJMpMhcMNFb1tC5a+M0QtOV0CiFmFTIS L9YEQd+WFf4WanKJmjSNFdW50FM3KVQ9ozqzhpOJoQ048dAJ9ikm9XG1bx7Ch0Vv0tTzqH 7AjQNau20g2tnNYESmDiH6LZNcRiZMysEngT61OO0irHbC8OFE3gNLWuezZHq9+QRdW1sl F5vJYamrsrnM701Nx5tB5jx5eeHOnw8kDX5mHKzfcvjN8Cc1QdBQj2fMyTtAug== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 07/16] mtd: rawnand: sunxi: rework pattern found registers Date: Tue, 28 Oct 2025 08:35:00 +0100 Message-ID: <20251028073534.526992-8-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" On H6/H616, the register ECC_PAT_FOUND is at its own address, and not part of ECC status register. So, introduce the pattern found register offset in sunxi_nfc_caps, along with its mask. Also, introduce a non compile-time field_get() because FIELD_GET() and u32_get_bits() don't work with non compile-time constant. https://lore.kernel.org/all/cover.1761588465.git.geert+renesas@glider.be No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 36 ++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 89495d786293..021034a761b7 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -29,6 +29,9 @@ #include #include =20 +/* non compile-time field get */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + #define NFC_REG_CTL 0x0000 #define NFC_REG_ST 0x0004 #define NFC_REG_INT 0x0008 @@ -150,7 +153,13 @@ /* define bit use in NFC_ECC_ST */ #define NFC_ECC_ERR(x) BIT(x) #define NFC_ECC_ERR_MSK GENMASK(15, 0) -#define NFC_ECC_PAT_FOUND(x) BIT(x + 16) + +/* + * define bit use in NFC_REG_PAT_FOUND + * For A10/A23, NFC_REG_PAT_FOUND =3D=3D NFC_ECC_ST register + */ +#define NFC_ECC_PAT_FOUND_MSK(nfc) (nfc->caps->pat_found_mask) + #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) =20 #define NFC_DEFAULT_TIMEOUT_MS 1000 @@ -227,6 +236,8 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_pat_found: Data Pattern Status Register + * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths @@ -236,6 +247,8 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_pat_found; + unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; @@ -776,7 +789,8 @@ static void sunxi_nfc_hw_ecc_update_stats(struct nand_c= hip *nand, } =20 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *= oob, - int step, u32 status, bool *erased) + int step, u32 status, u32 pattern_found, + bool *erased) { struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct nand_ecc_ctrl *ecc =3D &nand->ecc; @@ -787,7 +801,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, if (status & NFC_ECC_ERR(step)) return -EBADMSG; =20 - if (status & NFC_ECC_PAT_FOUND(step)) { + if (pattern_found & BIT(step)) { u8 pattern; =20 if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) { @@ -821,6 +835,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, struct sunxi_nfc *nfc =3D to_sunxi_nfc(nand->controller); struct nand_ecc_ctrl *ecc =3D &nand->ecc; int raw_mode =3D 0; + u32 pattern_found; bool erased; int ret; =20 @@ -848,8 +863,12 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chi= p *nand, =20 *cur_off =3D oob_off + ecc->bytes + USER_DATA_SZ; =20 + pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); + pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); + ret =3D sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, readl(nfc->regs + NFC_REG_ECC_ST), + pattern_found, &erased); if (erased) return 1; @@ -930,7 +949,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf unsigned int max_bitflips =3D 0; int ret, i, raw_mode =3D 0; struct scatterlist sg; - u32 status, wait; + u32 status, pattern_found, wait; =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -971,6 +990,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand= _chip *nand, uint8_t *buf return ret; =20 status =3D readl(nfc->regs + NFC_REG_ECC_ST); + pattern_found =3D readl(nfc->regs + nfc->caps->reg_pat_found); + pattern_found =3D field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); =20 for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; @@ -981,7 +1002,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nan= d_chip *nand, uint8_t *buf =20 ret =3D sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL, oob_required ? oob : NULL, - i, status, &erased); + i, status, pattern_found, + &erased); =20 /* ECC errors are handled in the second loop. */ if (ret < 0) @@ -2195,6 +2217,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_found =3D NFC_REG_ECC_ST, + .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), @@ -2205,6 +2229,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_found =3D NFC_REG_ECC_ST, + .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C09732D6E62 for ; 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charset="utf-8" The H616 controller can't handle 512 bytes ECC block size. The NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its place. So, add has_ecc_block_512 capability to only set this bit on SoC having it. No functional change. Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 021034a761b7..7976cd862b1b 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -233,6 +233,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. + * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register @@ -244,6 +245,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) */ struct sunxi_nfc_caps { bool has_mdma; + bool has_ecc_block_512; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; @@ -1758,8 +1760,14 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_c= hip *nand, sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION | NFC_ECC_PIPELINE | NFC_ECC_EN; =20 - if (ecc->size =3D=3D 512) - sunxi_nand->ecc.ecc_ctl |=3D NFC_ECC_BLOCK_512; + if (ecc->size =3D=3D 512) { + if (nfc->caps->has_ecc_block_512) { + sunxi_nand->ecc.ecc_ctl |=3D NFC_ECC_BLOCK_512; + } else { + dev_err(nfc->dev, "512B ECC block not supported\n"); + return -EOPNOTSUPP; + } + } =20 return 0; } @@ -2214,6 +2222,7 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { + .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, @@ -2226,6 +2235,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { .has_mdma =3D true, + .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 447F12D7DF9; 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bh=WHT5aJzkY83/xR8KEjHxLalZD9CDZAzX9GTwaJs76KY=; b=aTatl4/DUeZ/ETOVmVGskT4/f2W3KOfEAEio9LxG/85xfrnhggo5grwLZrkKOKa3H56O2x flx0cJcUmaE1gm5peOVfCwkzdX1vIIGuSdYGU6B049QSqm4MPSOwsGtXbCiPHze1yIDZPG wKzAzDlG+0MJ2rYOuEKLNyMxTiD3sLitBVDf4lNYokqUtJQA2xDE1TTGRxcaLArQSH1K/B ZOUi8WGyauTiS91D/N6OVP5KCdYtWH/9M3SWbbbTEH2TRnXtUd0u0/EHgeHQX5Xy2tLA74 e3MeeeJkAMb6Rw6sP9l1CUTTXsgIr5zQg0ubBmnCcP8TRzBHOxrTyYoqVyqETA== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 09/16] mtd: rawnand: sunxi: introduce ecc_mode_mask in sunxi_nfc_caps Date: Tue, 28 Oct 2025 08:35:02 +0100 Message-ID: <20251028073534.526992-10-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H6/H616 ECC_MODE field is not at the same offset, and has not the same size. So move the mask into sunxi_nfc_caps. Also, introduce a non compile-time field_prep() because FIELD_PREP() doesn't work with non compile-time constant. https://lore.kernel.org/all/cover.1761588465.git.geert+renesas@glider.be No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 7976cd862b1b..a16d50a01751 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -29,8 +29,9 @@ #include #include =20 -/* non compile-time field get */ +/* non compile-time field get/prep */ #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) =20 #define NFC_REG_CTL 0x0000 #define NFC_REG_ST 0x0004 @@ -145,8 +146,8 @@ #define NFC_ECC_BLOCK_512 BIT(5) #define NFC_RANDOM_EN BIT(9) #define NFC_RANDOM_DIRECTION BIT(10) -#define NFC_ECC_MODE_MSK GENMASK(15, 12) -#define NFC_ECC_MODE(x) ((x) << 12) +#define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) +#define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) #define NFC_RANDOM_SEED(x) ((x) << 16) =20 @@ -238,6 +239,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register * @reg_pat_found: Data Pattern Status Register + * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array @@ -250,6 +252,7 @@ struct sunxi_nfc_caps { unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; unsigned int reg_pat_found; + unsigned int ecc_mode_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; @@ -1757,7 +1760,7 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_ch= ip *nand, ecc->read_oob_raw =3D nand_read_oob_std; ecc->write_oob_raw =3D nand_write_oob_std; =20 - sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION | + sunxi_nand->ecc.ecc_ctl =3D NFC_ECC_MODE(nfc, i) | NFC_ECC_EXCEPTION | NFC_ECC_PIPELINE | NFC_ECC_EN; =20 if (ecc->size =3D=3D 512) { @@ -2227,6 +2230,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, @@ -2240,6 +2244,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1FA62D8773 for ; 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charset="utf-8" The H6/H616 RANDOM EN/DIRECTION masks are different from A10/A23. So move the masks into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index a16d50a01751..7dfc50a788e2 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -144,8 +144,8 @@ #define NFC_ECC_EXCEPTION BIT(4) #define NFC_ECC_BLOCK_SIZE_MSK BIT(5) #define NFC_ECC_BLOCK_512 BIT(5) -#define NFC_RANDOM_EN BIT(9) -#define NFC_RANDOM_DIRECTION BIT(10) +#define NFC_RANDOM_EN(nfc) (nfc->caps->random_en_mask) +#define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) #define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) #define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) @@ -239,6 +239,8 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register * @reg_pat_found: Data Pattern Status Register + * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register + * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst @@ -252,6 +254,8 @@ struct sunxi_nfc_caps { unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; unsigned int reg_pat_found; + unsigned int random_en_mask; + unsigned int random_dir_mask; unsigned int ecc_mode_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; @@ -680,7 +684,7 @@ static void sunxi_nfc_randomizer_enable(struct nand_chi= p *nand) if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN, + writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN(nfc), nfc->regs + NFC_REG_ECC_CTL); } =20 @@ -691,7 +695,7 @@ static void sunxi_nfc_randomizer_disable(struct nand_ch= ip *nand) if (!(nand->options & NAND_NEED_SCRAMBLING)) return; =20 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN, + writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN(nfc), nfc->regs + NFC_REG_ECC_CTL); } =20 @@ -2230,6 +2234,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .random_en_mask =3D BIT(9), + .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, @@ -2244,6 +2250,8 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, .reg_pat_found =3D NFC_REG_ECC_ST, + .random_en_mask =3D BIT(9), + .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 440742D877B for ; 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charset="utf-8" The H6/H616 pattern ID register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 7dfc50a788e2..3cb84e502ad7 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -55,7 +55,8 @@ #define NFC_REG_A10_USER_DATA 0x0050 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) #define NFC_REG_SPARE_AREA 0x00A0 -#define NFC_REG_PAT_ID 0x00A4 +#define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) +#define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 #define NFC_REG_MDMA_CNT 0x00C4 #define NFC_RAM0_BASE 0x0400 @@ -238,6 +239,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register @@ -253,6 +255,7 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_pat_id; unsigned int reg_pat_found; unsigned int random_en_mask; unsigned int random_dir_mask; @@ -813,7 +816,7 @@ static int sunxi_nfc_hw_ecc_correct(struct nand_chip *n= and, u8 *data, u8 *oob, if (pattern_found & BIT(step)) { u8 pattern; =20 - if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) { + if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID(nfc)) & 0x1))) { pattern =3D 0x0; } else { pattern =3D 0xff; @@ -2233,6 +2236,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), @@ -2249,6 +2253,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED1C2C11D7; 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charset="utf-8" The H6/H616 spare area register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 3cb84e502ad7..d2e5bcb76925 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -54,7 +54,8 @@ #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) #define NFC_REG_A10_USER_DATA 0x0050 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) -#define NFC_REG_SPARE_AREA 0x00A0 +#define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) +#define NFC_REG_A10_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) #define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 @@ -239,6 +240,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_spare_area: Spare Area Register * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register @@ -255,6 +257,7 @@ struct sunxi_nfc_caps { unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_spare_area; unsigned int reg_pat_id; unsigned int reg_pat_found; unsigned int random_en_mask; @@ -477,7 +480,7 @@ static void sunxi_nfc_select_chip(struct nand_chip *nan= d, unsigned int cs) if (sel->rb >=3D 0) ctl |=3D NFC_RB_SEL(sel->rb); =20 - writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA(nfc)); =20 if (nfc->clk_rate !=3D sunxi_nand->clk_rate) { clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); @@ -2236,6 +2239,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .reg_io_data =3D NFC_REG_A10_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_spare_area =3D NFC_REG_A10_SPARE_AREA, .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), @@ -2253,6 +2257,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .reg_io_data =3D NFC_REG_A23_IO_DATA, .reg_ecc_err_cnt =3D NFC_REG_A10_ECC_ERR_CNT, .reg_user_data =3D NFC_REG_A10_USER_DATA, + .reg_spare_area =3D NFC_REG_A10_SPARE_AREA, .reg_pat_id =3D NFC_REG_A10_PAT_ID, .reg_pat_found =3D NFC_REG_ECC_ST, .random_en_mask =3D BIT(9), --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE1392DAFA1 for ; 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charset="utf-8" The H6/H616 error mask register is bigger than the A10/A23 one, so move its mask into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index d2e5bcb76925..0a9ac75bb229 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -155,7 +155,7 @@ =20 /* define bit use in NFC_ECC_ST */ #define NFC_ECC_ERR(x) BIT(x) -#define NFC_ECC_ERR_MSK GENMASK(15, 0) +#define NFC_ECC_ERR_MSK(nfc) (nfc->caps->ecc_err_mask) =20 /* * define bit use in NFC_REG_PAT_FOUND @@ -246,6 +246,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register + * @ecc_err_mask: NFC_ECC_ERR mask in NFC_ECC_ST register * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array @@ -263,6 +264,7 @@ struct sunxi_nfc_caps { unsigned int random_en_mask; unsigned int random_dir_mask; unsigned int ecc_mode_mask; + unsigned int ecc_err_mask; unsigned int pat_found_mask; unsigned int dma_maxburst; const u8 *ecc_strengths; @@ -1040,7 +1042,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct na= nd_chip *nand, uint8_t *buf sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret); } =20 - if (status & NFC_ECC_ERR_MSK) { + if (status & NFC_ECC_ERR_MSK(nfc)) { for (i =3D 0; i < nchunks; i++) { int data_off =3D i * ecc->size; int oob_off =3D i * (ecc->bytes + USER_DATA_SZ); @@ -2245,6 +2247,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), + .ecc_err_mask =3D GENMASK(15, 0), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, @@ -2263,6 +2266,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .random_en_mask =3D BIT(9), .random_dir_mask =3D BIT(10), .ecc_mode_mask =3D GENMASK(15, 12), + .ecc_err_mask =3D GENMASK(15, 0), .pat_found_mask =3D GENMASK(31, 16), .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F71D2DCBE0; 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charset="utf-8" The H6/H616 the SRAM is bigger than the A10/A23 one, so move its size into sunxi_nfc_caps. No functional change Signed-off-by: Richard Genoud Reviewed-by: Jernej Skrabec --- drivers/mtd/nand/raw/sunxi_nand.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 0a9ac75bb229..5e030fc2fde5 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -167,8 +167,6 @@ =20 #define NFC_DEFAULT_TIMEOUT_MS 1000 =20 -#define NFC_SRAM_SIZE 1024 - #define NFC_MAX_CS 7 =20 /* @@ -251,6 +249,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths + * @sram_size: Size of the NAND controller SRAM */ struct sunxi_nfc_caps { bool has_mdma; @@ -269,6 +268,7 @@ struct sunxi_nfc_caps { unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; + int sram_size; }; =20 /** @@ -506,7 +506,7 @@ static void sunxi_nfc_read_buf(struct nand_chip *nand, = uint8_t *buf, int len) while (len > offs) { bool poll =3D false; =20 - cnt =3D min(len - offs, NFC_SRAM_SIZE); + cnt =3D min(len - offs, nfc->caps->sram_size); =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -544,7 +544,7 @@ static void sunxi_nfc_write_buf(struct nand_chip *nand,= const uint8_t *buf, while (len > offs) { bool poll =3D false; =20 - cnt =3D min(len - offs, NFC_SRAM_SIZE); + cnt =3D min(len - offs, nfc->caps->sram_size); =20 ret =3D sunxi_nfc_wait_cmd_fifo_empty(nfc); if (ret) @@ -1871,7 +1871,7 @@ static int sunxi_nfc_exec_subop(struct nand_chip *nan= d, case NAND_OP_DATA_OUT_INSTR: start =3D nand_subop_get_data_start_off(subop, i); remaining =3D nand_subop_get_data_len(subop, i); - cnt =3D min_t(u32, remaining, NFC_SRAM_SIZE); + cnt =3D min_t(u32, remaining, nfc->caps->sram_size); cmd |=3D NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; =20 if (instr->type =3D=3D NAND_OP_DATA_OUT_INSTR) { @@ -2252,6 +2252,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .sram_size =3D 1024, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { @@ -2271,6 +2272,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .sram_size =3D 1024, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { --=20 2.47.3 From nobody Fri Dec 19 10:41:14 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B69782DECC6; Tue, 28 Oct 2025 07:36:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761636997; cv=none; b=rMPcKTi+BDIfWhB+HHgTyr0A/RqZdbGQo5fY+VwUdtX0VF1L1Wy6HmANFkjhB5oaq7rFlj09xBz1iNn4+cO09bhEnN7bJiIC15iz0BuQCzcxotaaI5BThv0RD4+An/8IE/Q6gOHDvDACebb68z0iY/9eW1lkbbHCmiDp2vonVv8= ARC-Message-Signature: i=1; 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charset="utf-8" The H616 nand controller has the same base as A10/A23, with some differences: - mdma is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud --- drivers/mtd/nand/raw/sunxi_nand.c | 185 ++++++++++++++++++++++++++++-- 1 file changed, 177 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 5e030fc2fde5..031ab651c5a8 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -49,17 +49,40 @@ #define NFC_REG_A23_IO_DATA 0x0300 #define NFC_REG_ECC_CTL 0x0034 #define NFC_REG_ECC_ST 0x0038 -#define NFC_REG_DEBUG 0x003C +#define NFC_REG_H6_PAT_FOUND 0x003C #define NFC_REG_A10_ECC_ERR_CNT 0x0040 +#define NFC_REG_H6_ECC_ERR_CNT 0x0050 #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & = ~0x3) +#define NFC_REG_H6_RDATA_CTL 0x0044 +#define NFC_REG_H6_RDATA_0 0x0048 +#define NFC_REG_H6_RDATA_1 0x004C #define NFC_REG_A10_USER_DATA 0x0050 +#define NFC_REG_H6_USER_DATA 0x0080 #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) +#define NFC_REG_H6_USER_DATA_LEN 0x0070 +/* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */ +#define NFC_REG_USER_DATA_LEN_CAPACITY 8 +#define NFC_REG_USER_DATA_LEN(nfc, step) \ + (nfc->caps->reg_user_data_len + \ + ((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4) #define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) #define NFC_REG_A10_SPARE_AREA 0x00A0 #define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) #define NFC_REG_A10_PAT_ID 0x00A4 #define NFC_REG_MDMA_ADDR 0x00C0 #define NFC_REG_MDMA_CNT 0x00C4 +#define NFC_REG_H6_EFNAND_STATUS 0x0110 +#define NFC_REG_H6_SPARE_AREA 0x0114 +#define NFC_REG_H6_PAT_ID 0x0118 +#define NFC_REG_H6_DDR2_SPEC_CTL 0x011C +#define NFC_REG_H6_NDMA_MODE_CTL 0x0120 +#define NFC_REG_H6_MDMA_DLBA_REG 0x0200 +#define NFC_REG_H6_MDMA_STA 0x0204 +#define NFC_REG_H6_MDMA_INT_MAS 0x0208 +#define NFC_REG_H6_MDMA_DESC_ADDR 0x020C +#define NFC_REG_H6_MDMA_BUF_ADDR 0x0210 +#define NFC_REG_H6_MDMA_CNT 0x0214 + #define NFC_RAM0_BASE 0x0400 #define NFC_RAM1_BASE 0x0800 =20 @@ -71,6 +94,7 @@ #define NFC_BUS_WIDTH_16 (1 << 2) #define NFC_RB_SEL_MSK BIT(3) #define NFC_RB_SEL(x) ((x) << 3) +/* CE_SEL BIT 27 is meant to be used for GPIO chipselect */ #define NFC_CE_SEL_MSK GENMASK(26, 24) #define NFC_CE_SEL(x) ((x) << 24) #define NFC_CE_CTL BIT(6) @@ -89,6 +113,9 @@ #define NFC_STA BIT(4) #define NFC_NATCH_INT_FLAG BIT(5) #define NFC_RB_STATE(x) BIT(x + 8) +#define NFC_RB_STATE_MSK GENMASK(11, 8) +#define NDFC_RDATA_STA_1 BIT(12) +#define NDFC_RDATA_STA_0 BIT(13) =20 /* define bit use in NFC_INT */ #define NFC_B2R_INT_ENABLE BIT(0) @@ -100,6 +127,7 @@ =20 /* define bit use in NFC_TIMING_CTL */ #define NFC_TIMING_CTL_EDO BIT(8) +#define NFC_TIMING_CTL_E_EDO BIT(9) =20 /* define NFC_TIMING_CFG register layout */ #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ @@ -107,9 +135,15 @@ (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ (((tCAD) & 0x7) << 8)) =20 +#define NFC_TIMING_CFG2(tCDQSS, tSC, tCLHZ, tCSS, tWC) \ + ((((tCDQSS) & 0x1) << 11) | (((tSC) & 0x3) << 12) | \ + (((tCLHZ) & 0x3) << 14) | (((tCSS) & 0x3) << 16) | \ + (((tWC) & 0x3) << 18)) + /* define bit use in NFC_CMD */ #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0) -#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) +#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) /* 15-10 reserved on H6 */ +#define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8) #define NFC_CMD(x) (x) #define NFC_ADR_NUM_MSK GENMASK(18, 16) #define NFC_ADR_NUM(x) (((x) - 1) << 16) @@ -122,6 +156,7 @@ #define NFC_SEQ BIT(25) #define NFC_DATA_SWAP_METHOD BIT(26) #define NFC_ROW_AUTO_INC BIT(27) +#define NFC_H6_SEND_RND_CMD2 BIT(27) #define NFC_SEND_CMD3 BIT(28) #define NFC_SEND_CMD4 BIT(29) #define NFC_CMD_TYPE_MSK GENMASK(31, 30) @@ -133,6 +168,7 @@ #define NFC_READ_CMD_MSK GENMASK(7, 0) #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8) #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16) +#define NFC_RND_READ_CMD2_MSK GENMASK(31, 24) =20 /* define bit use in NFC_WCMD_SET */ #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0) @@ -150,6 +186,9 @@ #define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) #define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) #define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) +/* RANDOM_PAGE_SIZE: 0: ECC block size 1: page size */ +#define NFC_A23_RANDOM_PAGE_SIZE BIT(11) +#define NFC_H6_RANDOM_PAGE_SIZE BIT(7) #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) #define NFC_RANDOM_SEED(x) ((x) << 16) =20 @@ -165,6 +204,9 @@ =20 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) =20 +#define NFC_USER_DATA_LEN_MSK(step) \ + (0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4)) + #define NFC_DEFAULT_TIMEOUT_MS 1000 =20 #define NFC_MAX_CS 7 @@ -235,9 +277,12 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(st= ruct nand_chip *nand) * @has_mdma: Use mbus dma mode, otherwise general dma * through MBUS on A23/A33 needs extra configuration. * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks + * @has_ecc_clk: If the controller needs an ECC clock. + * @has_mbus_clk: If the controller needs a mbus clock. * @reg_io_data: I/O data register * @reg_ecc_err_cnt: ECC error counter register * @reg_user_data: User data register + * @reg_user_data_len: User data length register * @reg_spare_area: Spare Area Register * @reg_pat_id: Pattern ID Register * @reg_pat_found: Data Pattern Status Register @@ -249,14 +294,24 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(s= truct nand_chip *nand) * @dma_maxburst: DMA maxburst * @ecc_strengths: Available ECC strengths array * @nstrengths: Size of @ecc_strengths + * @max_ecc_steps: Maximum supported steps for ECC, this is also the + * number of user data registers + * @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN regist= er + * The table index is the value to set in NFC_USER_DATA_LEN + * registers, and the corresponding value is the number of + * bytes to write + * @nuser_data_tab: Size of @user_data_len_tab * @sram_size: Size of the NAND controller SRAM */ struct sunxi_nfc_caps { bool has_mdma; bool has_ecc_block_512; + bool has_ecc_clk; + bool has_mbus_clk; unsigned int reg_io_data; unsigned int reg_ecc_err_cnt; unsigned int reg_user_data; + unsigned int reg_user_data_len; unsigned int reg_spare_area; unsigned int reg_pat_id; unsigned int reg_pat_found; @@ -268,6 +323,9 @@ struct sunxi_nfc_caps { unsigned int dma_maxburst; const u8 *ecc_strengths; unsigned int nstrengths; + const u8 *user_data_len_tab; + unsigned int nuser_data_tab; + unsigned int max_ecc_steps; int sram_size; }; =20 @@ -279,6 +337,8 @@ struct sunxi_nfc_caps { * @regs: NAND controller registers * @ahb_clk: NAND controller AHB clock * @mod_clk: NAND controller mod clock + * @ecc_clk: NAND controller ECC clock + * @mbus_clk: NAND controller MBUS clock * @reset: NAND controller reset line * @assigned_cs: bitmask describing already assigned CS lines * @clk_rate: NAND controller current clock rate @@ -294,6 +354,8 @@ struct sunxi_nfc { void __iomem *regs; struct clk *ahb_clk; struct clk *mod_clk; + struct clk *ecc_clk; + struct clk *mbus_clk; struct reset_control *reset; unsigned long assigned_cs; unsigned long clk_rate; @@ -774,6 +836,53 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct= nand_chip *nand, u8 *oob, sunxi_nfc_randomize_bbm(nand, page, oob); } =20 +/* + * On H6/H6 the user_data length has to be set in specific registers + * before writing. + */ +static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc) +{ + int loop_step =3D NFC_REG_USER_DATA_LEN_CAPACITY; + + /* not all SoCs have this register */ + if (!nfc->caps->reg_user_data_len) + return; + + for (int i =3D 0; i < nfc->caps->max_ecc_steps; i +=3D loop_step) + writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i)); +} + +static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc, + int len, int step) +{ + bool found =3D false; + u32 val; + int i; + + /* not all SoCs have this register */ + if (!nfc->caps->reg_user_data_len) + return; + + for (i =3D 0; i < nfc->caps->nuser_data_tab; i++) { + if (len =3D=3D nfc->caps->user_data_len_tab[i]) { + found =3D true; + break; + } + } + + if (!found) { + dev_warn(nfc->dev, + "Unsupported length for user data reg: %d\n", len); + return; + } + + val =3D readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); + + val &=3D ~NFC_USER_DATA_LEN_MSK(step); + val |=3D field_prep(NFC_USER_DATA_LEN_MSK(step), i); + writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); +} + static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand, const u8 *oob, int step, bool bbm, int page) @@ -868,6 +977,8 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip= *nand, if (ret) return ret; =20 + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, @@ -978,6 +1089,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nan= d_chip *nand, uint8_t *buf return ret; =20 sunxi_nfc_hw_ecc_enable(nand); + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); =20 @@ -1110,6 +1223,8 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_c= hip *nand, =20 sunxi_nfc_randomizer_config(nand, page, false); sunxi_nfc_randomizer_enable(nand); + sunxi_nfc_reset_user_data_len(nfc); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page); =20 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | @@ -1354,10 +1469,12 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct n= and_chip *nand, if (ret) goto pio_fallback; =20 + sunxi_nfc_reset_user_data_len(nfc); for (i =3D 0; i < ecc->steps; i++) { const u8 *oob =3D nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ)); =20 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, i); } =20 nand_prog_page_begin_op(nand, page, 0, NULL, 0); @@ -2158,6 +2275,10 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) if (irq < 0) return irq; =20 + nfc->caps =3D of_device_get_match_data(dev); + if (!nfc->caps) + return -EINVAL; + nfc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); if (IS_ERR(nfc->ahb_clk)) { dev_err(dev, "failed to retrieve ahb clk\n"); @@ -2170,6 +2291,22 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) return PTR_ERR(nfc->mod_clk); } =20 + if (nfc->caps->has_ecc_clk) { + nfc->ecc_clk =3D devm_clk_get_enabled(dev, "ecc"); + if (IS_ERR(nfc->ecc_clk)) { + dev_err(dev, "failed to retrieve ecc clk\n"); + return PTR_ERR(nfc->ecc_clk); + } + } + + if (nfc->caps->has_mbus_clk) { + nfc->mbus_clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(nfc->mbus_clk)) { + dev_err(dev, "failed to retrieve mbus clk\n"); + return PTR_ERR(nfc->mbus_clk); + } + } + nfc->reset =3D devm_reset_control_get_optional_exclusive(dev, "ahb"); if (IS_ERR(nfc->reset)) return PTR_ERR(nfc->reset); @@ -2180,12 +2317,6 @@ static int sunxi_nfc_probe(struct platform_device *p= dev) return ret; } =20 - nfc->caps =3D of_device_get_match_data(&pdev->dev); - if (!nfc->caps) { - ret =3D -EINVAL; - goto out_ahb_reset_reassert; - } - ret =3D sunxi_nfc_rst(nfc); if (ret) goto out_ahb_reset_reassert; @@ -2236,6 +2367,14 @@ static const u8 sunxi_ecc_strengths_a10[] =3D { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; =20 +static const u8 sunxi_ecc_strengths_h6[] =3D { + 16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 +}; + +static const u8 sunxi_user_data_len_h6[] =3D { + 0, 4, 8, 12, 16, 20, 24, 28, 32 +}; + static const struct sunxi_nfc_caps sunxi_nfc_a10_caps =3D { .has_ecc_block_512 =3D true, .reg_io_data =3D NFC_REG_A10_IO_DATA, @@ -2252,6 +2391,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .dma_maxburst =3D 4, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .max_ecc_steps =3D 16, .sram_size =3D 1024, }; =20 @@ -2272,9 +2412,34 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_cap= s =3D { .dma_maxburst =3D 8, .ecc_strengths =3D sunxi_ecc_strengths_a10, .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), + .max_ecc_steps =3D 16, .sram_size =3D 1024, }; =20 +static const struct sunxi_nfc_caps sunxi_nfc_h616_caps =3D { + .has_ecc_clk =3D true, + .has_mbus_clk =3D true, + .reg_io_data =3D NFC_REG_A23_IO_DATA, + .reg_ecc_err_cnt =3D NFC_REG_H6_ECC_ERR_CNT, + .reg_user_data =3D NFC_REG_H6_USER_DATA, + .reg_user_data_len =3D NFC_REG_H6_USER_DATA_LEN, + .reg_spare_area =3D NFC_REG_H6_SPARE_AREA, + .reg_pat_id =3D NFC_REG_H6_PAT_ID, + .reg_pat_found =3D NFC_REG_H6_PAT_FOUND, + .random_en_mask =3D BIT(5), + .random_dir_mask =3D BIT(6), + .ecc_mode_mask =3D GENMASK(15, 8), + .ecc_err_mask =3D GENMASK(31, 0), + .pat_found_mask =3D GENMASK(31, 0), + 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t=1761636994; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=HDL+cduKGo0iwjImHuxRFOSxsiEzs6TUgE6gWmABSIg=; b=VfW+i13nyaovNMhOgJDRHw3FVtH49cPKUE/qlj/T3LX2zoZz8OaUuNkQidN4SvX+UxhxmX zAlRe30kXPqneuD46fPFB1Sk3osgunGsMn4ln0on/w604ivEwkGk7XIQ8ffKdyPByVRoh2 sjAZ72dzOLO+ScPme5ueaQGv27fjYaS7fCQVMW5RNdCiOH7vxCWzgc9ASauxrcPEjo5AyR jxKqDPwBmDk64gC5RjIViG5XKDYfZVA92J7upzyz1QJPKOcyJNRuU0I52g1yri0xsPqVBI oPc5ufrAS98mXp0AihVw9/N3ukKYmO5bv0+K/hA/14f8Xgvy1DVsYP5IoR83iA== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH v4 16/16] arm64: dts: allwinner: h616: add NAND controller Date: Tue, 28 Oct 2025 08:35:09 +0100 Message-ID: <20251028073534.526992-17-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251028073534.526992-1-richard.genoud@bootlin.com> References: <20251028073534.526992-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The H616 has a NAND controller quite similar to the A10/A23 ones, but with some register differences, more clocks (for ECC and MBUS), more ECC strengths, so this requires a new compatible string. Add the NAND controller node and pins in the device tree. Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index ceedae9e399b..2a4d70298655 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + /omit-if-no-ref/ + nand_pins: nand-pins { + pins =3D "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function =3D "nand0"; + }; + + /omit-if-no-ref/ + nand_cs0_pin: nand-cs0-pin { + pins =3D "PC4"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_cs1_pin: nand-cs1-pin { + pins =3D "PC3"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb0_pin: nand-rb0-pin { + pins =3D "PC6"; + function =3D "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb1_pin: nand-rb1-pin { + pins =3D "PC7"; + function =3D "nand0"; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins =3D "PC0", "PC2", "PC4"; @@ -377,6 +413,22 @@ iommu: iommu@30f0000 { #iommu-cells =3D <1>; }; =20 + nfc: nand-controller@4011000 { + compatible =3D "allwinner,sun50i-h616-nand-controller"; + reg =3D <0x04011000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; + clock-names =3D "ahb", "mod", "ecc", "mbus"; + resets =3D <&ccu RST_BUS_NAND>; + reset-names =3D "ahb"; + dmas =3D <&dma 10>; + dma-names =3D "rxtx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + mmc0: mmc@4020000 { compatible =3D "allwinner,sun50i-h616-mmc", "allwinner,sun50i-a100-mmc"; --=20 2.47.3