From nobody Sun Feb 8 06:49:51 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D550717C21E for ; Tue, 28 Oct 2025 03:40:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761622848; cv=none; b=Y5Z00YCyALj3GOaugCwu4B1OnS5TH6zzGAww0oMydvrBVCxW97vrLXSJkYvs06Wuwp8EbohK5WrhND1N6xZZ2EqL0b5r5aN79JsHvwZ29EJvB/WJ/mN6ldA4bNP4khjqaZSnMuFByLXW6JrvoUhnyWSotchWBmTJlOYQvjEMtOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761622848; c=relaxed/simple; bh=DNq4+3TXq9EfjM7kdNigYuP8GMWIJc/TUvBGaZPD+5g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H8MVCH1aH6CuFXGjabk1sqZLFOW/gQJsnxzIKV8fCJti+3LgTOVY+FkL5hoyo5wf+MEJH/zt7I2masq1Oih7+QS6Caz/4VT5MZANzhRoG9bb7vT8wfbpURcMm90e5oo8ANiP91yZZh6eY1aP+GqI3QXB9J5nFPEcnwnBpRePfnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=SzHxACLp; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SzHxACLp" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59S3e8i31399677; Mon, 27 Oct 2025 22:40:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1761622808; bh=8YsUL3FmjkiSJTuL3XXGj1pESxfnhDNRpNWlSDg3YYA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SzHxACLpIScA45hT2Z8iRmwYYxDbK8UfrpV9X1ifwCBIjuvYap0SuwMWa30Q8wG9E hPAIzDztRn4yfK+mkXAOu1gmbQCT+zw5tR0gJg+z7rMHYN5Cg4nRLtA/cN1cu/sAAg qvQZj1B00tk9+faE5xdwKyD0uk9sYnBCWDmRHvG0= Received: from DFLE201.ent.ti.com (dfle201.ent.ti.com [10.64.6.59]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59S3e81t1393714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Oct 2025 22:40:08 -0500 Received: from DFLE205.ent.ti.com (10.64.6.63) by DFLE201.ent.ti.com (10.64.6.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 27 Oct 2025 22:40:08 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE205.ent.ti.com (10.64.6.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Mon, 27 Oct 2025 22:40:08 -0500 Received: from a0512632.dhcp.ti.com (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59S3dxWT1685770; Mon, 27 Oct 2025 22:40:04 -0500 From: Swamil Jain To: , , , , , , , , , CC: , , , , , Subject: [RESEND PATCH v7 1/2] drm/tidss: Remove max_pclk_khz and min_pclk_khz from tidss display features Date: Tue, 28 Oct 2025 09:09:57 +0530 Message-ID: <20251028033958.369100-2-s-jain1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251028033958.369100-1-s-jain1@ti.com> References: <20251028033958.369100-1-s-jain1@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jayesh Choudhary The TIDSS hardware does not have independent maximum or minimum pixel clock limits for each video port. Instead, these limits are determined by the SoC's clock architecture. Previously, this constraint was modeled using the 'max_pclk_khz' and 'min_pclk_khz' fields in 'dispc_features', but this approach is static and does not account for the dynamic behavior of PLLs. This patch removes the 'max_pclk_khz' and 'min_pclk_khz' fields from 'dispc_features'. The correct way to check if a requested mode's pixel clock is supported is by using 'clk_round_rate()' in the 'mode_valid()' hook. If the best frequency match for the mode clock falls within the supported tolerance, it is approved. TIDSS supports a 5% pixel clock tolerance, which is now reflected in the validation logic. This change allows existing DSS-compatible drivers to be reused across SoCs that only differ in their pixel clock characteristics. The validation uses 'clk_round_rate()' for each mode, which may introduce additional delay (about 3.5 ms for 30 modes), but this is generally negligible. Users desiring faster validation may bypass these calls selectively, for example, checking only the highest resolution mode, as shown here[1]. [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/ Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_dispc.c | 85 ++++++++++------------------- drivers/gpu/drm/tidss/tidss_dispc.h | 3 - 2 files changed, 30 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index d0b191c470ca..07731b02490f 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -57,12 +57,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_= TABLE_LEN] =3D { }; =20 const struct dispc_features dispc_k2g_feats =3D { - .min_pclk_khz =3D 4375, - - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 150000, - }, - /* * XXX According TRM the RGB input buffer width up to 2560 should * work on 3 taps, but in practice it only works up to 1280. @@ -145,11 +139,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_= REG_TABLE_LEN] =3D { }; =20 const struct dispc_features dispc_am65x_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - [DISPC_VP_OLDI_AM65X] =3D 165000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -245,11 +234,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_= REG_TABLE_LEN] =3D { }; =20 const struct dispc_features dispc_j721e_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 170000, - [DISPC_VP_INTERNAL] =3D 600000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 2048, .in_width_max_3tap_rgb =3D 4096, @@ -316,11 +300,6 @@ const struct dispc_features dispc_j721e_feats =3D { }; =20 const struct dispc_features dispc_am625_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - [DISPC_VP_INTERNAL] =3D 170000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -377,15 +356,6 @@ const struct dispc_features dispc_am625_feats =3D { }; =20 const struct dispc_features dispc_am62a7_feats =3D { - /* - * if the code reaches dispc_mode_valid with VP1, - * it should return MODE_BAD. - */ - .max_pclk_khz =3D { - [DISPC_VP_TIED_OFF] =3D 0, - [DISPC_VP_DPI] =3D 165000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -442,10 +412,6 @@ const struct dispc_features dispc_am62a7_feats =3D { }; =20 const struct dispc_features dispc_am62l_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - }, - .subrev =3D DISPC_AM62L, =20 .common =3D "common", @@ -1333,33 +1299,53 @@ static void dispc_vp_set_default_color(struct dispc= _device *dispc, DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); } =20 +/* + * Calculate the percentage difference between the requested pixel clock r= ate + * and the effective rate resulting from calculating the clock divider val= ue. + */ +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) +{ + int r =3D rate / 100, rr =3D real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +static int check_pixel_clock(struct dispc_device *dispc, + u32 hw_videoport, unsigned long clock) +{ + unsigned long round_clock; + + round_clock =3D clk_round_rate(dispc->vp_clk[hw_videoport], clock); + /* + * To keep the check consistent with dispc_vp_set_clk_rate(), we + * use the same 5% check here. + */ + if (dispc_pclk_diff(clock, round_clock) > 5) + return -EINVAL; + return 0; +} + enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, u32 hw_videoport, const struct drm_display_mode *mode) { u32 hsw, hfp, hbp, vsw, vfp, vbp; enum dispc_vp_bus_type bus_type; - int max_pclk; =20 bus_type =3D dispc->feat->vp_bus_type[hw_videoport]; =20 - max_pclk =3D dispc->feat->max_pclk_khz[bus_type]; - - if (WARN_ON(max_pclk =3D=3D 0)) + if (WARN_ON(bus_type =3D=3D DISPC_VP_TIED_OFF)) return MODE_BAD; =20 - if (mode->clock < dispc->feat->min_pclk_khz) - return MODE_CLOCK_LOW; - - if (mode->clock > max_pclk) - return MODE_CLOCK_HIGH; - if (mode->hdisplay > 4096) return MODE_BAD; =20 if (mode->vdisplay > 4096) return MODE_BAD; =20 + if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000)) + return MODE_CLOCK_HIGH; + /* TODO: add interlace support */ if (mode->flags & DRM_MODE_FLAG_INTERLACE) return MODE_NO_INTERLACE; @@ -1423,17 +1409,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc= , u32 hw_videoport) clk_disable_unprepare(dispc->vp_clk[hw_videoport]); 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charset="utf-8" From: Jayesh Choudhary After integrating OLDI support[0], it is necessary to identify which VP instances use OLDI, since the OLDI driver owns the video port clock (as a serial clock). Clock operations on these VPs must be delegated to the OLDI driver, not handled by the TIDSS driver. This issue also emerged in upstream discussions when DSI-related clock management was attempted in the TIDSS driver[1]. To address this, add an 'is_ext_vp_clk' array to the 'tidss_device' structure, marking a VP as 'true' during 'tidss_oldi_init()' and as 'false' during 'tidss_oldi_deinit()'. TIDSS then uses 'is_ext_vp_clk' to skip clock validation checks in 'dispc_vp_mode_valid()' for VPs under OLDI control. Since OLDI uses the DSS VP clock directly as a serial interface and manages its own rate, mode validation should be implemented in the OLDI bridge's 'mode_valid' hook. This patch adds that logic, ensuring proper delegation and avoiding spurious clock handling in the TIDSS driver. [0]: https://lore.kernel.org/all/20250528122544.817829-1-aradhya.bhatia@lin= ux.dev/ [1]: https://lore.kernel.org/all/DA6TT575Z82D.3MPK8HG5GRL8U@kernel.org/ Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_dispc.c | 2 ++ drivers/gpu/drm/tidss/tidss_drv.h | 2 ++ drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 07731b02490f..0c3337a7b163 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1315,6 +1315,8 @@ static int check_pixel_clock(struct dispc_device *dis= pc, { unsigned long round_clock; =20 + if (dispc->tidss->is_ext_vp_clk[hw_videoport]) + return 0; round_clock =3D clk_round_rate(dispc->vp_clk[hw_videoport], clock); /* * To keep the check consistent with dispc_vp_set_clk_rate(), we diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tids= s_drv.h index 84454a4855d1..e1c1f41d8b4b 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -24,6 +24,8 @@ struct tidss_device { =20 const struct dispc_features *feat; struct dispc_device *dispc; + bool is_ext_vp_clk[TIDSS_MAX_PORTS]; + =20 unsigned int num_crtcs; struct drm_crtc *crtcs[TIDSS_MAX_PORTS]; diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tid= ss_oldi.c index 7688251beba2..d1a5fdac93ff 100644 --- a/drivers/gpu/drm/tidss/tidss_oldi.c +++ b/drivers/gpu/drm/tidss/tidss_oldi.c @@ -309,6 +309,24 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struc= t drm_bridge *bridge, return input_fmts; } =20 +static enum drm_mode_status +tidss_oldi_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct tidss_oldi *oldi =3D drm_bridge_to_tidss_oldi(bridge); + unsigned long round_clock; + + round_clock =3D clk_round_rate(oldi->serial, mode->clock * 7 * 1000); + /* + * To keep the check consistent with dispc_vp_set_clk_rate(), + * we use the same 5% check here. + */ + if (dispc_pclk_diff(mode->clock * 7 * 1000, round_clock) > 5) + return -EINVAL; + return 0; +} + static const struct drm_bridge_funcs tidss_oldi_bridge_funcs =3D { .attach =3D tidss_oldi_bridge_attach, .atomic_pre_enable =3D tidss_oldi_atomic_pre_enable, @@ -317,6 +335,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_= funcs =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, .atomic_reset =3D drm_atomic_helper_bridge_reset, + .mode_valid =3D tidss_oldi_mode_valid, }; =20 static int get_oldi_mode(struct device_node *oldi_tx, int *companion_insta= nce) @@ -430,6 +449,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss) for (int i =3D 0; i < tidss->num_oldis; i++) { if (tidss->oldis[i]) { drm_bridge_remove(&tidss->oldis[i]->bridge); + tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] =3D false; tidss->oldis[i] =3D NULL; } } @@ -580,6 +600,7 @@ int tidss_oldi_init(struct tidss_device *tidss) oldi->bridge.timings =3D &default_tidss_oldi_timings; =20 tidss->oldis[tidss->num_oldis++] =3D oldi; + tidss->is_ext_vp_clk[oldi->parent_vp] =3D true; oldi->tidss =3D tidss; =20 drm_bridge_add(&oldi->bridge);