From nobody Sun Feb 8 11:40:45 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77E7C170A11; Tue, 28 Oct 2025 15:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761663652; cv=none; b=Elif+dL4cY35o8rFQdpQKXv3OBGjAFHW99w1IfAW0c20j807Y1vZJtJr3KF/u5iPkX9e6LJc36omYNpVEf3LRLyNMPmMRVOtFK8AlWuQX6jNUezlz2E+zW3QvFBZDnEAOoCbIPncfJE+KnkWB9oNWOe5EA/5E/xBz0Fo37RDxgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761663652; c=relaxed/simple; bh=NqtS/vo6GQ9GLxrmrNCvwi9dCjnitvmWTlCDHG2vFA8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=uezIC94TY5pO+KWD3cQ+M0qjeYXSpTVtAt358DSHkFfftOJW+Gobp9E5Lx49B6AkF2xO7ZFFdRyPkYq4V+H04dw824RYDt6xBeTPC2pW0meiTdJoVpSOlrmQif9yuB6CK+cXpnGTwibW09au+VZq378F7wHVvs2R/dCm4qD0YH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rMEBgbxb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rMEBgbxb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06F31C4CEE7; Tue, 28 Oct 2025 15:00:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761663652; bh=NqtS/vo6GQ9GLxrmrNCvwi9dCjnitvmWTlCDHG2vFA8=; h=From:Date:Subject:To:Cc:From; b=rMEBgbxbusNwEbZInt9zjNooDq+meSxtgQ68h+Jkz78I2Ubtptzeti7HdQOwvAm1n RDw3ygBUsUEA6+64+Dgt8sd9jTO4LojiEoq4FybTCQrGsWSjMiLjErLZr2VCHxgsCM G++aqXA7WQOQxpDeD5k2rU5yDHu1miBucR7BvfGRnSzp8wc0MA0+fkS4GTv55dZvgV ySxDV3hmPrgqhkVjfZdcCQvnYCo3bliGtsF3n533HXQiIeYE9XkKjXoLkJhVuPu/Zc TPyHurEXjQkzoWqTIDBrVGxy/kboYz505zk5LsYsDpKwzI7fTft9PBlSSEbcEfzo7c 6PugmvGO6srKA== From: Andreas Kemnade Date: Tue, 28 Oct 2025 16:00:36 +0100 Subject: [PATCH v4] ARM: dts: imx: e70k02: add sy7636 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251028-sy7636-rsrc-v4-1-242ccfd3bc10@kernel.org> X-B4-Tracking: v=1; b=H4sIAJPaAGkC/23MQQ7CIBRF0a0YxmLoh0Jx5D6MA4RPSzStAUNsm u5d2lEbHb6XnDuRhDFgIufDRCLmkMLQlyGOB2I707dIgyubAIOaaSZpGpXkksYULbXAjJF3Y8A KUsQrog+ftXa9ld2F9B7iuMZztbz/O7mijCI0jTS6vEZdHhh7fJ6G2JIllGGL9R5DwdY77YXwD mr9g/kGV2qPecGcV8CVq5kysMPzPH8BeUugNyEBAAA= X-Change-ID: 20250906-sy7636-rsrc-c20aa6baa2c4 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alistair Francis , Liam Girdwood , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Frank Li Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Peng Fan , Andreas Kemnade X-Mailer: b4 0.15-dev-50721 X-Developer-Signature: v=1; a=openpgp-sha256; l=6304; i=akemnade@kernel.org; h=from:subject:message-id; bh=NqtS/vo6GQ9GLxrmrNCvwi9dCjnitvmWTlCDHG2vFA8=; b=owGbwMvMwCUm/rzkS6lq2x3G02pJDJkMtxZUrd0wLUxqM4v+x1T1F68ObOl+dOGBWgqfpuHGm Owyh75XHaUsDGJcDLJiiiy/rBXcPqk8yw2eGmEPM4eVCWQIAxenAEzktAzDP+2u4u/9V+J5DB1P uHJptmzvvG9772P21nr1C98um96xsGZkuHX+UOhis0f9eQ1TH3QcuX159hXLyKtpqxuF2hfq/Ju 3jA8A X-Developer-Key: i=akemnade@kernel.org; a=openpgp; fpr=EEC0DB858E66C0DA70620AC07DBD6AC74DE29324 Add the EPD PMIC for the e70k02 based devices as a step towards full EPD support. Acked-by: Alistair Francis Reviewed-by: Peng Fan Signed-off-by: Andreas Kemnade --- The SY7636A has some pins which can be hardwired or used to have more more advanced power management available. As several devices containing this regulator have these pins not hardwired, but instead connected to some GPIO, enhance the driver to have them defined and initialized. Also add the ability to power off the chip completely by defining some input power supply. Actually implementing better power management is planned to be implemented as a second step. The regulators in the SY7636A should only be on for a short time during display refresh, but currently they are unconditionally forcefully enabled by the hwmon part of this chip. --- Changes in v4: - reorder enable-active-high property - Link to v3: https://lore.kernel.org/r/20250917-sy7636-rsrc-v3-0-331237d50= 7a2@kernel.org Changes in v3: - shorten descriptions in binding - Link to v2: https://lore.kernel.org/r/20250909-sy7636-rsrc-v2-0-cfd9f44fd= 259@kernel.org Changes in v2: - en[-gpios] -> enable[-gpios] in yaml/dts/driver - fix en vs vcom_en in error handling - comment delay - drop applied commit (rebased to regulator/for-linus) - Link to v1: https://lore.kernel.org/r/20250906-sy7636-rsrc-v1-0-e2886a976= 3a7@kernel.org --- arch/arm/boot/dts/nxp/imx/e70k02.dtsi | 25 ++++++++++++++++++= +++- .../arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts | 24 ++++++++++++++++++= +++ .../arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts | 24 ++++++++++++++++++= +++ 3 files changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi b/arch/arm/boot/dts/nxp/= imx/e70k02.dtsi index dcc3c9d488a8..3bb11c5a6353 100644 --- a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi @@ -69,6 +69,14 @@ memory@80000000 { reg =3D <0x80000000 0x20000000>; }; =20 + epd_pmic_supply: regulator-epd-pmic-in { + compatible =3D "regulator-fixed"; + regulator-name =3D "epd_pmic_supply"; + gpio =3D <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us =3D <20000>; + }; + reg_wifi: regulator-wifi { compatible =3D "regulator-fixed"; regulator-name =3D "SD3_SPWR"; @@ -133,7 +141,22 @@ touchscreen@24 { vdd-supply =3D <&ldo5_reg>; }; =20 - /* TODO: SY7636 PMIC for E Ink at 0x62 */ + sy7636: pmic@62 { + compatible =3D "silergy,sy7636a"; + reg =3D <0x62>; + enable-gpios =3D <&gpio2 8 GPIO_ACTIVE_HIGH>; + vcom-en-gpios =3D <&gpio2 3 GPIO_ACTIVE_HIGH>; + epd-pwr-good-gpios =3D <&gpio2 13 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&epd_pmic_supply>; + + #thermal-sensor-cells =3D <0>; + + regulators { + reg_epdpmic: vcom { + regulator-name =3D "vcom"; + }; + }; + }; =20 }; =20 diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts b/arch/arm= /boot/dts/nxp/imx/imx6sl-tolino-vision5.dts index a2534c422a52..f8709a952409 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts @@ -26,6 +26,11 @@ / { compatible =3D "kobo,tolino-vision5", "fsl,imx6sl"; }; =20 +&epd_pmic_supply { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_gpio_keys>; @@ -59,6 +64,12 @@ MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x10059 /* TP_RS= T */ >; }; =20 + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins =3D < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins =3D < MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -159,6 +170,14 @@ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 ba= t_low_int */ >; }; =20 + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins =3D < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins =3D < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 @@ -329,6 +348,11 @@ &ricoh619 { pinctrl-0 =3D <&pinctrl_ricoh_gpio>; }; =20 +&sy7636 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts b/arch/arm= /boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts index 660620d226f7..19bbe60331b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts @@ -36,6 +36,11 @@ &cpu0 { soc-supply =3D <&dcdc1_reg>; }; =20 +&epd_pmic_supply { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_gpio_keys>; @@ -69,6 +74,12 @@ MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ >; }; =20 + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins =3D < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins =3D < MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -169,6 +180,14 @@ MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 b= at_low_int */ >; }; =20 + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins =3D < + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins =3D < MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 @@ -319,6 +338,11 @@ &ricoh619 { pinctrl-0 =3D <&pinctrl_ricoh_gpio>; }; =20 +&sy7636 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_uart1>; --- base-commit: f7d2388eeec24966fc4d5cf32d706f0514f29ac5 change-id: 20250906-sy7636-rsrc-c20aa6baa2c4 Best regards, -- =20 Andreas Kemnade