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Only support for private transfers and does not support sending CCC commands in HDR mode. Key differences: - HDR uses commands (0x00-0x7F for write, 0x80-0xFF for read) to distinguish transfer direction. - HDR read/write commands must be written to FIFO before issuing the I3C address command. The hardware automatically sends the standard CCC command to enter HDR mode. - HDR exit pattern must be sent instead of send a stop after transfer completion. - Read/write data size must be an even number. Co-developed-by: Carlos Song Signed-off-by: Carlos Song Signed-off-by: Frank Li --- change in v7: - add comment about why need check return value readl_poll_timeout() in svc_i3c_master_emit_force_exit() - add comment about why need udelay(1) - remove reg =3D 0; - chagne to use readl_poll_timeout_atomic(); - replace all i3c_priv_xfer with new i3c_xfer. change in v4 - use hdr_cap. change in v3 - rename to svc_cmd_is_read() - rename to i3c_mode_to_svc_type() - use local varible bool rnw to reduce change change in v2 - support HDR DDR write - rdterm unit is byte, not words (RM is wrong). --- drivers/i3c/master/svc-i3c-master.c | 96 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 83 insertions(+), 13 deletions(-) diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i= 3c-master.c index 7c516e05d0a1a118479ee3d8ea8ae37ae19fea57..a732443caaf15a2f6e54de46bba= fdeb3fc9a9296 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -40,11 +40,13 @@ #define SVC_I3C_MCTRL_REQUEST_NONE 0 #define SVC_I3C_MCTRL_REQUEST_START_ADDR 1 #define SVC_I3C_MCTRL_REQUEST_STOP 2 +#define SVC_I3C_MCTRL_REQUEST_FORCE_EXIT 6 #define SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3 #define SVC_I3C_MCTRL_REQUEST_PROC_DAA 4 #define SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7 #define SVC_I3C_MCTRL_TYPE_I3C 0 #define SVC_I3C_MCTRL_TYPE_I2C BIT(4) +#define SVC_I3C_MCTRL_TYPE_DDR BIT(5) #define SVC_I3C_MCTRL_IBIRESP_AUTO 0 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0 #define SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7) @@ -95,6 +97,7 @@ #define SVC_I3C_MINTMASKED 0x098 #define SVC_I3C_MERRWARN 0x09C #define SVC_I3C_MERRWARN_NACK BIT(2) +#define SVC_I3C_MERRWARN_CRC BIT(10) #define SVC_I3C_MERRWARN_TIMEOUT BIT(20) #define SVC_I3C_MDMACTRL 0x0A0 #define SVC_I3C_MDATACTRL 0x0AC @@ -174,7 +177,7 @@ struct svc_i3c_cmd { const void *out; unsigned int len; unsigned int actual_len; - struct i3c_priv_xfer *xfer; + struct i3c_xfer *xfer; bool continued; }; =20 @@ -389,7 +392,32 @@ svc_i3c_master_dev_from_addr(struct svc_i3c_master *ma= ster, =20 static bool svc_cmd_is_read(u32 rnw_cmd, u32 type) { - return rnw_cmd; + return (type =3D=3D SVC_I3C_MCTRL_TYPE_DDR) ? !!(rnw_cmd & 0x80) : rnw_cm= d; +} + +static void svc_i3c_master_emit_force_exit(struct svc_i3c_master *master) +{ + u32 reg; + + writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL); + + /* + * Not need check error here because it is never happen at hardware. IP + * just wait for few fclk cycle to complete DDR exit pattern. Even + * though fclk stop, timeout happen here, the whole data actually + * already finish transfer. The next command will be timeout because + * wrong hardware state. + */ + readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, + SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000); + + /* + * This delay is necessary after the emission of a stop, otherwise eg. + * repeating IBIs do not get detected. There is a note in the manual + * about it, stating that the stop condition might not be settled + * correctly if a start condition follows too rapidly. + */ + udelay(1); } =20 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) @@ -521,7 +549,7 @@ static void svc_i3c_master_ibi_isr(struct svc_i3c_maste= r *master) * cycle, leading to missed client IBI handlers. * * A typical scenario is when IBIWON occurs and bus arbitration is lost - * at svc_i3c_master_priv_xfers(). + * at svc_i3c_master_i3c_xfers(). * * Clear SVC_I3C_MINT_IBIWON before sending SVC_I3C_MCTRL_REQUEST_AUTO_IB= I. */ @@ -801,6 +829,8 @@ static int svc_i3c_master_bus_init(struct i3c_master_co= ntroller *m) =20 info.dyn_addr =3D ret; =20 + info.hdr_cap =3D I3C_CCC_HDR_MODE(I3C_HDR_DDR); + writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr), master->regs + SVC_I3C_MDYNADDR); =20 @@ -1314,6 +1344,16 @@ static int svc_i3c_master_xfer(struct svc_i3c_master= *master, /* clean SVC_I3C_MINT_IBIWON w1c bits */ writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); =20 + if (xfer_type =3D=3D SVC_I3C_MCTRL_TYPE_DDR) { + /* DDR command need prefill into FIFO */ + writel(rnw_cmd, master->regs + SVC_I3C_MWDATAB); + if (!rnw) { + /* write data also need prefill into FIFO */ + ret =3D svc_i3c_master_write(master, out, xfer_len); + if (ret) + goto emit_stop; + } + } =20 while (retry--) { writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | @@ -1407,7 +1447,7 @@ static int svc_i3c_master_xfer(struct svc_i3c_master = *master, =20 if (rnw) ret =3D svc_i3c_master_read(master, in, xfer_len); - else + else if (xfer_type !=3D SVC_I3C_MCTRL_TYPE_DDR) ret =3D svc_i3c_master_write(master, out, xfer_len); if (ret < 0) goto emit_stop; @@ -1420,10 +1460,19 @@ static int svc_i3c_master_xfer(struct svc_i3c_maste= r *master, if (ret) goto emit_stop; =20 + if (xfer_type =3D=3D SVC_I3C_MCTRL_TYPE_DDR && + (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_CRC)) { + ret =3D -ENXIO; + goto emit_stop; + } + writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); =20 if (!continued) { - svc_i3c_master_emit_stop(master); + if (xfer_type !=3D SVC_I3C_MCTRL_TYPE_DDR) + svc_i3c_master_emit_stop(master); + else + svc_i3c_master_emit_force_exit(master); =20 /* Wait idle if stop is sent. */ readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, @@ -1433,7 +1482,11 @@ static int svc_i3c_master_xfer(struct svc_i3c_master= *master, return 0; =20 emit_stop: - svc_i3c_master_emit_stop(master); + if (xfer_type !=3D SVC_I3C_MCTRL_TYPE_DDR) + svc_i3c_master_emit_stop(master); + else + svc_i3c_master_emit_force_exit(master); + svc_i3c_master_clear_merrwarn(master); svc_i3c_master_flush_fifo(master); =20 @@ -1480,6 +1533,11 @@ static void svc_i3c_master_dequeue_xfer(struct svc_i= 3c_master *master, spin_unlock_irqrestore(&master->xferqueue.lock, flags); } =20 +static int i3c_mode_to_svc_type(enum i3c_xfer_mode mode) +{ + return (mode =3D=3D I3C_SDR) ? SVC_I3C_MCTRL_TYPE_I3C : SVC_I3C_MCTRL_TYP= E_DDR; +} + static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) { struct svc_i3c_xfer *xfer =3D master->xferqueue.cur; @@ -1669,9 +1727,8 @@ static int svc_i3c_master_send_ccc_cmd(struct i3c_mas= ter_controller *m, return ret; } =20 -static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev, - struct i3c_priv_xfer *xfers, - int nxfers) +static int svc_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_x= fer *xfers, + int nxfers, enum i3c_xfer_mode mode) { struct i3c_master_controller *m =3D i3c_dev_get_master(dev); struct svc_i3c_master *master =3D to_svc_i3c_master(m); @@ -1679,19 +1736,32 @@ static int svc_i3c_master_priv_xfers(struct i3c_dev= _desc *dev, struct svc_i3c_xfer *xfer; int ret, i; =20 + if (mode !=3D I3C_SDR) { + /* + * Only support data size less than FIFO SIZE when using DDR + * mode. First entry is cmd in FIFO, so actual available FIFO + * for data is SVC_I3C_FIFO_SIZE - 2 since DDR only supports + * even length. + */ + for (i =3D 0; i < nxfers; i++) + if (xfers[i].len > SVC_I3C_FIFO_SIZE - 2) + return -EINVAL; + } + xfer =3D svc_i3c_master_alloc_xfer(master, nxfers); if (!xfer) return -ENOMEM; =20 - xfer->type =3D SVC_I3C_MCTRL_TYPE_I3C; + xfer->type =3D i3c_mode_to_svc_type(mode); =20 for (i =3D 0; i < nxfers; i++) { + u32 rnw_cmd =3D (mode =3D=3D I3C_SDR) ? xfers[i].rnw : xfers[i].cmd; + bool rnw =3D svc_cmd_is_read(rnw_cmd, xfer->type); struct svc_i3c_cmd *cmd =3D &xfer->cmds[i]; - bool rnw =3D xfers[i].rnw; =20 cmd->xfer =3D &xfers[i]; cmd->addr =3D master->addrs[data->index]; - cmd->rnw =3D rnw; + cmd->rnw_cmd =3D rnw_cmd; cmd->in =3D rnw ? xfers[i].data.in : NULL; cmd->out =3D rnw ? NULL : xfers[i].data.out; cmd->len =3D xfers[i].len; @@ -1890,7 +1960,7 @@ static const struct i3c_master_controller_ops svc_i3c= _master_ops =3D { .do_daa =3D svc_i3c_master_do_daa, .supports_ccc_cmd =3D svc_i3c_master_supports_ccc_cmd, .send_ccc_cmd =3D svc_i3c_master_send_ccc_cmd, - .priv_xfers =3D svc_i3c_master_priv_xfers, + .i3c_xfers =3D svc_i3c_master_i3c_xfers, .i2c_xfers =3D svc_i3c_master_i2c_xfers, .request_ibi =3D svc_i3c_master_request_ibi, .free_ibi =3D svc_i3c_master_free_ibi, --=20 2.34.1