From nobody Sun Feb 8 23:03:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC37F303A03; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761645155; cv=none; b=YT4iBXI+ydsyzNrQ+2bDRTJUVocPFiVefO7gTdwdDNM+ffPH7fHl4qRMnhGJPbA/U7VU3ELO2/1hxfBWfi0jkLKbvaoZaaD24Z+tL/qHCHwapms/nP9CF8TztVdf5d8uom9IrDkqEFeiZ+ztYQNnCWPtHuVBJRZ1NrW7+GPc3yI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761645155; c=relaxed/simple; bh=MnV2BOCd8DTs0wVX3sUywUNj4t1O0jc50IRxp5XXIJw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I3RF54tA4wbf2PQDlrFsio+J6u5CF9B5X6yaPfzV5sDJXi8g7PU+DishsL1DHibplGfbCG4lMxwGRhs9knwa2g2m6Cg6BC2PIsjL2dPySroiMJIJtt+A7njnIA1iFkdxwx0GmEWAc72a8hXg3hNj936NaLY+yO8v/3gzbsblxs8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Io0w7+YV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Io0w7+YV" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8B14DC16AAE; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761645155; bh=MnV2BOCd8DTs0wVX3sUywUNj4t1O0jc50IRxp5XXIJw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Io0w7+YV5lGMPmYa3+AZ29JcvmpusrVy0A8PrUVf43jpQH/nNPXqUcvS9AZzjQLH8 pQjQBRjvdYzIbVOo4D4VyM54ETncG5fqWayyXFJXRCsXD6Krqh0/JbYpbvWxo/59j0 olfF1TBgwQQ8iXxtaaGahZYZej/fcFFJMWIe1vMNU/0pmyE4AJ207byEw215/mBFsd rohprq4p9PFwItP95byDlUcanX4jtP7/z3e6WMLQPWQhXdxbFK37a4V/9anI3RDz3o AJpsfrnHyb/TQSj78V3e3xFdTURlTgyHj1RNBwhK5xPtLJWgf/D1T9tiTxEgbCcnac uJbQApYAvYTLg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 824AFCCF9EE; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 28 Oct 2025 17:52:30 +0800 Subject: [PATCH v4 4/8] clk: amlogic: Add A5 PLL clock controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251028-a5-clk-v4-4-e62ca0aae243@amlogic.com> References: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com> In-Reply-To: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761645153; l=13554; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=bqPQfOJqLfFXBRF759KJLHWjqGxOIH91g1/52NuwjAA=; b=UV83sWcOCcECVREuHcUsKh5wKwRE2cT6hJ/tQB5fU1uM+Vbm0CCQ4CV6baZZ+O7rh1iboEQuS l2c7claT78iBr9hLCTIkTMnl/UkOvzRSJb/iVMWjKTqC9mKYRQkinIq X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller driver for the Amlogic A5 SoC family. Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- drivers/clk/meson/Kconfig | 14 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-pll.c | 476 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 491 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 71481607a6d5..b627821da081 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -132,6 +132,20 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A5_PLL + tristate "Amlogic A5 PLL clock controller" + depends on ARM64 + default ARCH_MESON + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_MPLL + select COMMON_CLK_MESON_CLKC_UTILS + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A113X2 device, AKA A5. + Say Y if you want the board to work, because PLLs are the parent + of most peripherals. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index c6998e752c68..a074aa7e187f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-pll.c b/drivers/clk/meson/a5-pll.c new file mode 100644 index 000000000000..1789a7e6470d --- /dev/null +++ b/drivers/clk/meson/a5-pll.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 PLL Controller Driver + * + * Copyright (c) 2024-2025 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include + +#define GP0PLL_CTRL0 0x80 +#define GP0PLL_CTRL1 0x84 +#define GP0PLL_CTRL2 0x88 +#define GP0PLL_CTRL3 0x8c +#define GP0PLL_CTRL4 0x90 +#define GP0PLL_CTRL5 0x94 +#define GP0PLL_CTRL6 0x98 +#define HIFIPLL_CTRL0 0x100 +#define HIFIPLL_CTRL1 0x104 +#define HIFIPLL_CTRL2 0x108 +#define HIFIPLL_CTRL3 0x10c +#define HIFIPLL_CTRL4 0x110 +#define HIFIPLL_CTRL5 0x114 +#define HIFIPLL_CTRL6 0x118 +#define MPLL_CTRL0 0x180 +#define MPLL_CTRL1 0x184 +#define MPLL_CTRL2 0x188 +#define MPLL_CTRL3 0x18c +#define MPLL_CTRL4 0x190 +#define MPLL_CTRL5 0x194 +#define MPLL_CTRL6 0x198 +#define MPLL_CTRL7 0x19c +#define MPLL_CTRL8 0x1a0 + +static struct clk_fixed_factor a5_mpll_prediv =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll_prediv", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix_dco" + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence a5_mpll0_init_regs[] =3D { + { .reg =3D MPLL_CTRL2, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll0_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL1, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll0_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll0_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll0 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL1, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll0_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll1_init_regs[] =3D { + { .reg =3D MPLL_CTRL4, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll1_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL3, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll1_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll1_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll1_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll1 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL3, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "a5_mpll1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll1_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll2_init_regs[] =3D { + { .reg =3D MPLL_CTRL6, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll2_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL5, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll2_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll2_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL5, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll2_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_mpll3_init_regs[] =3D { + { .reg =3D MPLL_CTRL8, .def =3D 0x40000033 }, +}; + +static struct clk_regmap a5_mpll3_div =3D { + .data =3D &(struct meson_clk_mpll_data){ + .sdm =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 0, + .width =3D 14, + }, + .sdm_en =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 30, + .width =3D 1, + }, + .n2 =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 20, + .width =3D 9, + }, + .ssen =3D { + .reg_off =3D MPLL_CTRL7, + .shift =3D 29, + .width =3D 1, + }, + .init_regs =3D a5_mpll3_init_regs, + .init_count =3D ARRAY_SIZE(a5_mpll3_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3_div", + .ops =3D &meson_clk_mpll_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_mpll_prediv.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_mpll3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D MPLL_CTRL7, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mpll3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { &a5_mpll3_div.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_gp0_init_regs[] =3D { + { .reg =3D GP0PLL_CTRL3, .def =3D 0x6a295c00 }, + { .reg =3D GP0PLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D GP0PLL_CTRL6, .def =3D 0x54540000 } +}; + +static const struct pll_mult_range a5_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_gp0_pll_mult_range, + .init_regs =3D a5_gp0_init_regs, + .init_count =3D ARRAY_SIZE(a5_gp0_init_regs), + .frac_max =3D 100000, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 32, not 128(2^7) */ +static const struct clk_div_table a5_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { 5, 32 }, + { /* sentinel */ } +}; + +static struct clk_regmap a5_gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .table =3D a5_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence a5_hifi_init_regs[] =3D { + { .reg =3D HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D HIFIPLL_CTRL6, .def =3D 0x56540000 } +}; + +static const struct pll_mult_range a5_hifi_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap a5_hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 17, + }, + .n =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &a5_hifi_pll_mult_range, + .init_regs =3D a5_hifi_init_regs, + .init_count =3D ARRAY_SIZE(a5_hifi_init_regs), + .frac_max =3D 100000, + .flags =3D CLK_MESON_PLL_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap a5_hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &a5_hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *a5_pll_hw_clks[] =3D { + [CLKID_MPLL_PREDIV] =3D &a5_mpll_prediv.hw, + [CLKID_MPLL0_DIV] =3D &a5_mpll0_div.hw, + [CLKID_MPLL0] =3D &a5_mpll0.hw, + [CLKID_MPLL1_DIV] =3D &a5_mpll1_div.hw, + [CLKID_MPLL1] =3D &a5_mpll1.hw, + [CLKID_MPLL2_DIV] =3D &a5_mpll2_div.hw, + [CLKID_MPLL2] =3D &a5_mpll2.hw, + [CLKID_MPLL3_DIV] =3D &a5_mpll3_div.hw, + [CLKID_MPLL3] =3D &a5_mpll3.hw, + [CLKID_GP0_PLL_DCO] =3D &a5_gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &a5_gp0_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &a5_hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &a5_hifi_pll.hw +}; + +static const struct meson_clkc_data a5_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a5_pll_hw_clks, + .num =3D ARRAY_SIZE(a5_pll_hw_clks), + }, +}; + +static const struct of_device_id a5_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-pll-clkc", + .data =3D &a5_pll_clkc_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a5_pll_clkc_match_table); + +static struct platform_driver a5_pll_clkc_driver =3D { + .probe =3D meson_clkc_mmio_probe, + .driver =3D { + .name =3D "a5-pll-clkc", + .of_match_table =3D a5_pll_clkc_match_table, + }, +}; +module_platform_driver(a5_pll_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A5 PLL Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); --=20 2.42.0