From nobody Mon Feb 9 03:11:25 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD823302CD1; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761645155; cv=none; b=h0I/1uej7wfSHRTUtsbpSEBvByX2eFzODNUr7w44rR6F39lbFRO0ijxBQUM8Vy2OJOOx48naDQqPSiQlqpMmMH254qPhZBO8XbgB4PgVauEwpI2B4Ta10hFGNGfoUvfBArWojEa0ZeCDonrjZh+LIxcuMyCWtcppyzg1FJ3/8XU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761645155; c=relaxed/simple; bh=h7V3+pw89fOc1KwUoKduNUn4vFERB1dIg8cLMp0/MLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WqkXAQYlk6kvVnICqMeoSeBdQidTgOJzeHLUzh7+UkOAmfW6sx7vxWN5tYyQ1uFRQ+7M3Yj8dxtEihwJ27pSrxXz1bSOJMT6Z09IG1IrLSVvNXAlbg9KCXBhIuKBkGc0RyjDoC+b9kUenHf4lSzNvt+DbHAN8OYjT20jZAwjsik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YJy+McYX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YJy+McYX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7131CC116B1; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761645155; bh=h7V3+pw89fOc1KwUoKduNUn4vFERB1dIg8cLMp0/MLA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YJy+McYXqYiclT463Y1om9YHJSw6R61QsjQmgdn2I/bz0okA3FaFccx2HsoMHsW9h rmJ2Y9ml69m/La18OHUztSnkp5jITddCCkvoNji/qQPbkZ6j+TNHFiHeutPh+imMUt wP22GR1lNAukwI8eoaflRF13O+F39jgYEGIk71E983w59n1VdJw+s7t2G1C9wOqWpw /iMSoBZITb5shseLlmrsSL0Ga5Mg4ZkbNY3CKxY/66fwAcgtE6G5DQoqbqYmsT2CfS ywSeVh+vDt9g06tLutdXgDj4KPZYpWJlJXSyVCC8t8p6hi+t9Ie3FId5vEGzx2G3jQ JjMmnB2BMUVYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63B00CCD1BF; Tue, 28 Oct 2025 09:52:35 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 28 Oct 2025 17:52:28 +0800 Subject: [PATCH v4 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251028-a5-clk-v4-2-e62ca0aae243@amlogic.com> References: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com> In-Reply-To: <20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761645153; l=3248; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=l0xvEX2cvQ+4zU5eZkaCNHE8ezIcqmOYLzKXuhlEW6M=; b=91zNtvK1BEUSWrPSu1SawezPdLv8vB+ZPLGQ5NrIcuYcbt2a6VgXjJPaRaYhaxvtqGUy2ZfTa gEj1NukbYzHD+y9Ju3ACwVo7YHqSxGRqv2SKXmyEwhGj/LqAMpK14hx X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for the Amlogic A5 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) Signed-off-by: Xianwei Zhao --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..d74570a90926 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL_DCO>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix_dco", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ --=20 2.42.0