From nobody Tue Feb 10 06:25:23 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 17B6031E10C; Mon, 27 Oct 2025 15:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761580032; cv=none; b=XQlPe/W1OBJwki/UJxC8rYFlDKmQ276F6r3GIItYYwusjfhH3F2dXIUq0XSQ1QwWYtU5jZ2cSqZ1WCK3Ph9nRsb2jjvnqkfN+NW9lOI19aUY/fbQ0TYOjYe/njDp+xprjdSyHI47o6wrgTGypuaTAGe/U7oiRmas7l++zOvFMcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761580032; c=relaxed/simple; bh=oG0rovoNpNXF/+ccTOdiQLS42A98YzuU1Z2EQYdzNdE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u+TK2UvX5l2GMnGGM0Zx2OKh0Kuwe7nbHfdLLKG4bOMZh0RNy34Hu2iEBaMndR+72KQEtSA+HBIG7Q3T79s3gKXa5ljm7Z5TJ5vF/rVI/0s0w3MHgS7HOPQatAwuHc0SAbaab6g6v5CTqQRhAtkyvFn7PCQCB1uXbbGfL3marJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: Ddd7LeqVTrix66H3rBZ93Q== X-CSE-MsgGUID: AvyG9dDRQiSCouSE/0BWew== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Oct 2025 00:47:10 +0900 Received: from localhost.localdomain (unknown [10.226.93.103]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 61B00400A67C; Tue, 28 Oct 2025 00:47:07 +0900 (JST) From: Biju Das To: Greg Kroah-Hartman , Jiri Slaby Cc: Biju Das , Geert Uytterhoeven , Lad Prabhakar , Wolfram Sang , Claudiu Beznea , Nam Cao , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 12/19] serial: sh-sci: Add support for RZ/G3E RSCI clks Date: Mon, 27 Oct 2025 15:45:59 +0000 Message-ID: <20251027154615.115759-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251027154615.115759-1-biju.das.jz@bp.renesas.com> References: <20251027154615.115759-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RZ/G3E RSCI has 5 module clocks. Add support for these clocks. Signed-off-by: Biju Das --- drivers/tty/serial/sh-sci-common.h | 3 +++ drivers/tty/serial/sh-sci.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci= -common.h index ef1d94ae8b5c..f730ff9add60 100644 --- a/drivers/tty/serial/sh-sci-common.h +++ b/drivers/tty/serial/sh-sci-common.h @@ -17,6 +17,9 @@ enum SCI_CLKS { SCI_SCK, /* Optional External Clock */ SCI_BRG_INT, /* Optional BRG Internal Clock Source */ SCI_SCIF_CLK, /* Optional BRG External Clock Source */ + SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */ + SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */ + SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */ SCI_NUM_CLKS }; =20 diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 5f5913410df9..d45bdda2b6c1 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) [SCI_SCK] =3D "sck", [SCI_BRG_INT] =3D "brg_int", [SCI_SCIF_CLK] =3D "scif_clk", + [SCI_FCK_DIV64] =3D "tclk_div64", + [SCI_FCK_DIV16] =3D "tclk_div16", + [SCI_FCK_DIV4] =3D "tclk_div4", }; struct clk *clk; unsigned int i; @@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port,= struct device *dev) } else if (sci_port->type =3D=3D SCI_PORT_RSCI) { clk_names[SCI_FCK] =3D "operation"; clk_names[SCI_BRG_INT] =3D "bus"; + } else if (sci_port->type =3D=3D RSCI_PORT_SCI || sci_port->type =3D=3D R= SCI_PORT_SCIF) { + clk_names[SCI_FCK] =3D "tclk"; + clk_names[SCI_BRG_INT] =3D "bus"; } =20 for (i =3D 0; i < SCI_NUM_CLKS; i++) { @@ -3018,6 +3024,14 @@ static int sci_init_clocks(struct sci_port *sci_port= , struct device *dev) name); } =20 + if (!clk && (sci_port->type =3D=3D RSCI_PORT_SCI || + sci_port->type =3D=3D RSCI_PORT_SCIF) && + (i =3D=3D SCI_FCK || i =3D=3D SCI_BRG_INT || i =3D=3D SCI_FCK_DIV64 = || + i =3D=3D SCI_FCK_DIV16 || i =3D=3D SCI_FCK_DIV4)) { + return dev_err_probe(dev, -ENODEV, "failed to get %s\n", + name); + } + if (!clk && i =3D=3D SCI_FCK) { /* * Not all SH platforms declare a clock lookup entry --=20 2.43.0