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Mon, 27 Oct 2025 06:34:51 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, conor@kernel.org, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, atishp@rivosinc.com, cleger@rivosinc.com, ajones@ventanamicro.com, apatel@ventanamicro.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, songshuaishuai@tinylab.org, bjorn@rivosinc.com, charlie@rivosinc.com, masahiroy@kernel.org, valentina.fernandezalanis@microchip.com, jassisinghbrar@gmail.com, conor.dooley@microchip.com Subject: [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support Date: Mon, 27 Oct 2025 21:34:29 +0800 Message-Id: <20251027133431.15321-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251027133431.15321-1-cuiyunhui@bytedance.com> References: <20251027133431.15321-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for handling Non-Maskable Interrupts (NMIs) through the RISC-V Supervisor Software Events (SSE) framework. Since each NMI type(e.g., unknown NMI, etc.) requires a distinct SSE event, a newfile sse_nmi.c is introduced to manage their registration and enabling. Signed-off-by: Yunhui Cui --- MAINTAINERS | 7 +++ arch/riscv/include/asm/sbi.h | 1 + drivers/firmware/riscv/Kconfig | 10 ++++ drivers/firmware/riscv/Makefile | 1 + drivers/firmware/riscv/sse_nmi.c | 81 ++++++++++++++++++++++++++++++++ 5 files changed, 100 insertions(+) create mode 100644 drivers/firmware/riscv/sse_nmi.c diff --git a/MAINTAINERS b/MAINTAINERS index 8bf5416953f45..6df6cbec4d85d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22057,6 +22057,13 @@ S: Maintained F: drivers/firmware/riscv/riscv_sse.c F: include/linux/riscv_sse.h =20 +RISC-V SSE NMI SUPPORT +M: Yunhui Cui +R: Xu Lu +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/firmware/riscv/sse_nmi.c + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 874cc1d7603a5..52d3fdf2d4cc1 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -486,6 +486,7 @@ enum sbi_sse_attr_id { #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS 0x00100000 #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS 0x00108000 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED 0xffff0000 +#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI 0xffff0001 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED 0xffff8000 =20 #define SBI_SSE_EVENT_PLATFORM BIT(14) diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig index ed5b663ac5f91..fd16b4c43cf01 100644 --- a/drivers/firmware/riscv/Kconfig +++ b/drivers/firmware/riscv/Kconfig @@ -12,4 +12,14 @@ config RISCV_SBI_SSE this option provides support to register callbacks on specific SSE events. =20 +config RISCV_SSE_NMI + bool "Enable SBI Supervisor Software Events NMI support" + depends on RISCV_SBI_SSE + default y + help + This option enables support for delivering Non-Maskable Interrupt + (NMI) notifications through the Supervisor Software Events (SSE) + framework. When enabled, the system supports some common NMI features + such as unknown NMI handling. + endmenu diff --git a/drivers/firmware/riscv/Makefile b/drivers/firmware/riscv/Makef= ile index c8795d4bbb2ea..ecf2b31935d9c 100644 --- a/drivers/firmware/riscv/Makefile +++ b/drivers/firmware/riscv/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_RISCV_SBI_SSE) +=3D riscv_sbi_sse.o +obj-$(CONFIG_RISCV_SSE_NMI) +=3D sse_nmi.o diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_= nmi.c new file mode 100644 index 0000000000000..2c1eaea2bbabc --- /dev/null +++ b/drivers/firmware/riscv/sse_nmi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "SSE NMI: " fmt + +#include +#include +#include + +#include +#include + +int unknown_nmi_panic; +static struct sse_event *unknown_nmi_evt; +static struct ctl_table_header *unknown_nmi_sysctl_header; + +static int __init setup_unknown_nmi_panic(char *str) +{ + unknown_nmi_panic =3D 1; + return 1; +} +__setup("unknown_nmi_panic", setup_unknown_nmi_panic); + +const struct ctl_table unknown_nmi_table[] =3D { + { + .procname =3D "unknown_nmi_panic", + .data =3D &unknown_nmi_panic, + .maxlen =3D sizeof(int), + .mode =3D 0644, + .proc_handler =3D proc_dointvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, +}; + +static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) +{ + pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id()); + + if (unknown_nmi_panic) + nmi_panic(regs, "NMI: Not continuing"); + + pr_emerg("Dazed and confused, but trying to continue\n"); + + return 0; +} + +static int unknown_nmi_init(void) +{ + int ret; + + unknown_nmi_evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI, 0, + unknown_nmi_handler, NULL); + if (IS_ERR(unknown_nmi_evt)) + return PTR_ERR(unknown_nmi_evt); + + ret =3D sse_event_enable(unknown_nmi_evt); + if (ret) + goto err_unregister; + + unknown_nmi_sysctl_header =3D register_sysctl("kernel", unknown_nmi_table= ); + if (!unknown_nmi_sysctl_header) { + ret =3D -ENOMEM; + goto err_disable; + } + + pr_info("Using SSE for unknown NMI event delivery\n"); + return 0; + +err_disable: + sse_event_disable(unknown_nmi_evt); +err_unregister: + sse_event_unregister(unknown_nmi_evt); + return ret; +} + +static int __init sse_nmi_init(void) +{ + return unknown_nmi_init(); +} + +late_initcall(sse_nmi_init); --=20 2.39.5