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Mon, 27 Oct 2025 06:34:51 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, conor@kernel.org, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, atishp@rivosinc.com, cleger@rivosinc.com, ajones@ventanamicro.com, apatel@ventanamicro.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, songshuaishuai@tinylab.org, bjorn@rivosinc.com, charlie@rivosinc.com, masahiroy@kernel.org, valentina.fernandezalanis@microchip.com, jassisinghbrar@gmail.com, conor.dooley@microchip.com Subject: [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support Date: Mon, 27 Oct 2025 21:34:29 +0800 Message-Id: <20251027133431.15321-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251027133431.15321-1-cuiyunhui@bytedance.com> References: <20251027133431.15321-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for handling Non-Maskable Interrupts (NMIs) through the RISC-V Supervisor Software Events (SSE) framework. Since each NMI type(e.g., unknown NMI, etc.) requires a distinct SSE event, a newfile sse_nmi.c is introduced to manage their registration and enabling. Signed-off-by: Yunhui Cui --- MAINTAINERS | 7 +++ arch/riscv/include/asm/sbi.h | 1 + drivers/firmware/riscv/Kconfig | 10 ++++ drivers/firmware/riscv/Makefile | 1 + drivers/firmware/riscv/sse_nmi.c | 81 ++++++++++++++++++++++++++++++++ 5 files changed, 100 insertions(+) create mode 100644 drivers/firmware/riscv/sse_nmi.c diff --git a/MAINTAINERS b/MAINTAINERS index 8bf5416953f45..6df6cbec4d85d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22057,6 +22057,13 @@ S: Maintained F: drivers/firmware/riscv/riscv_sse.c F: include/linux/riscv_sse.h =20 +RISC-V SSE NMI SUPPORT +M: Yunhui Cui +R: Xu Lu +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/firmware/riscv/sse_nmi.c + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 874cc1d7603a5..52d3fdf2d4cc1 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -486,6 +486,7 @@ enum sbi_sse_attr_id { #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS 0x00100000 #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS 0x00108000 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED 0xffff0000 +#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI 0xffff0001 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED 0xffff8000 =20 #define SBI_SSE_EVENT_PLATFORM BIT(14) diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig index ed5b663ac5f91..fd16b4c43cf01 100644 --- a/drivers/firmware/riscv/Kconfig +++ b/drivers/firmware/riscv/Kconfig @@ -12,4 +12,14 @@ config RISCV_SBI_SSE this option provides support to register callbacks on specific SSE events. =20 +config RISCV_SSE_NMI + bool "Enable SBI Supervisor Software Events NMI support" + depends on RISCV_SBI_SSE + default y + help + This option enables support for delivering Non-Maskable Interrupt + (NMI) notifications through the Supervisor Software Events (SSE) + framework. When enabled, the system supports some common NMI features + such as unknown NMI handling. + endmenu diff --git a/drivers/firmware/riscv/Makefile b/drivers/firmware/riscv/Makef= ile index c8795d4bbb2ea..ecf2b31935d9c 100644 --- a/drivers/firmware/riscv/Makefile +++ b/drivers/firmware/riscv/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_RISCV_SBI_SSE) +=3D riscv_sbi_sse.o +obj-$(CONFIG_RISCV_SSE_NMI) +=3D sse_nmi.o diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_= nmi.c new file mode 100644 index 0000000000000..2c1eaea2bbabc --- /dev/null +++ b/drivers/firmware/riscv/sse_nmi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "SSE NMI: " fmt + +#include +#include +#include + +#include +#include + +int unknown_nmi_panic; +static struct sse_event *unknown_nmi_evt; +static struct ctl_table_header *unknown_nmi_sysctl_header; + +static int __init setup_unknown_nmi_panic(char *str) +{ + unknown_nmi_panic =3D 1; + return 1; +} +__setup("unknown_nmi_panic", setup_unknown_nmi_panic); + +const struct ctl_table unknown_nmi_table[] =3D { + { + .procname =3D "unknown_nmi_panic", + .data =3D &unknown_nmi_panic, + .maxlen =3D sizeof(int), + .mode =3D 0644, + .proc_handler =3D proc_dointvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, +}; + +static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) +{ + pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id()); + + if (unknown_nmi_panic) + nmi_panic(regs, "NMI: Not continuing"); + + pr_emerg("Dazed and confused, but trying to continue\n"); + + return 0; +} + +static int unknown_nmi_init(void) +{ + int ret; + + unknown_nmi_evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI, 0, + unknown_nmi_handler, NULL); + if (IS_ERR(unknown_nmi_evt)) + return PTR_ERR(unknown_nmi_evt); + + ret =3D sse_event_enable(unknown_nmi_evt); + if (ret) + goto err_unregister; + + unknown_nmi_sysctl_header =3D register_sysctl("kernel", unknown_nmi_table= ); + if (!unknown_nmi_sysctl_header) { + ret =3D -ENOMEM; + goto err_disable; + } + + pr_info("Using SSE for unknown NMI event delivery\n"); + return 0; + +err_disable: + sse_event_disable(unknown_nmi_evt); +err_unregister: + sse_event_unregister(unknown_nmi_evt); + return ret; +} + +static int __init sse_nmi_init(void) +{ + return unknown_nmi_init(); +} + +late_initcall(sse_nmi_init); --=20 2.39.5 From nobody Sun Feb 8 22:08:18 2026 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BB1726CE36 for ; Mon, 27 Oct 2025 13:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761572101; cv=none; b=bGRhMRaqr7U5Th7W1FqPYhwAkDLoQa26IvWTSTdMds4NFvanYhJyEfC8n+CF5QwfeOBBXD/zqyBmr5epByOnGTi5OlPXH0kDeefklNsSojq0hpG+ho04RIYIt8+HB9WhLVcUqLi0jES+ssH8ZIHeGeCnQT/Akbnusu2pHgZCEGs= ARC-Message-Signature: i=1; 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Mon, 27 Oct 2025 06:34:58 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.234]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d42558sm82144935ad.69.2025.10.27.06.34.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 06:34:58 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, conor@kernel.org, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, atishp@rivosinc.com, cleger@rivosinc.com, ajones@ventanamicro.com, apatel@ventanamicro.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, songshuaishuai@tinylab.org, bjorn@rivosinc.com, charlie@rivosinc.com, masahiroy@kernel.org, valentina.fernandezalanis@microchip.com, jassisinghbrar@gmail.com, conor.dooley@microchip.com Subject: [PATCH 2/3] riscv: crash: move IPI crash handling logic to crash.c Date: Mon, 27 Oct 2025 21:34:30 +0800 Message-Id: <20251027133431.15321-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251027133431.15321-1-cuiyunhui@bytedance.com> References: <20251027133431.15321-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move IPI crash handling code from smp.c to a new crash.c to separate concerns and improve code organization, no functional change. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/crash.h | 16 ++++++ arch/riscv/include/asm/smp.h | 14 +++++ arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/crash.c | 84 +++++++++++++++++++++++++++++ arch/riscv/kernel/smp.c | 99 +--------------------------------- 5 files changed, 117 insertions(+), 98 deletions(-) create mode 100644 arch/riscv/include/asm/crash.h create mode 100644 arch/riscv/kernel/crash.c diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h new file mode 100644 index 0000000000000..b64df919277d4 --- /dev/null +++ b/arch/riscv/include/asm/crash.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_RISC_V_CRASH_H +#define _ASM_RISC_V_CRASH_H + +#ifdef CONFIG_KEXEC_CORE +void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs); +#else +static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) +{ + unreachable(); +} +#endif + +#endif + diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 7ac80e9f22889..ffd7f6f8d25aa 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -12,6 +12,18 @@ =20 #define INVALID_HARTID ULONG_MAX =20 +enum ipi_message_type { + IPI_RESCHEDULE, + IPI_CALL_FUNC, + IPI_CPU_STOP, + IPI_CPU_CRASH_STOP, + IPI_IRQ_WORK, + IPI_TIMER, + IPI_CPU_BACKTRACE, + IPI_KGDB_ROUNDUP, + IPI_MAX +}; + struct seq_file; extern unsigned long boot_cpu_hartid; =20 @@ -51,6 +63,8 @@ bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ void riscv_ipi_set_virq_range(int virq, int nr); =20 +void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op); + /* Check other CPUs stop or not */ bool smp_crash_stop_failed(void); =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 16637e01a6b34..f0fd655b113d3 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -107,7 +107,7 @@ endif obj-$(CONFIG_HOTPLUG_CPU) +=3D cpu-hotplug.o obj-$(CONFIG_PARAVIRT) +=3D paravirt.o obj-$(CONFIG_KGDB) +=3D kgdb.o -obj-$(CONFIG_KEXEC_CORE) +=3D kexec_relocate.o crash_save_regs.o machine_k= exec.o +obj-$(CONFIG_KEXEC_CORE) +=3D kexec_relocate.o crash_save_regs.o machine_k= exec.o crash.o obj-$(CONFIG_KEXEC_FILE) +=3D kexec_elf.o kexec_image.o machine_kexec_file= .o obj-$(CONFIG_CRASH_DUMP) +=3D crash_dump.o obj-$(CONFIG_VMCORE_INFO) +=3D vmcore_info.o diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c new file mode 100644 index 0000000000000..12598bbc2df04 --- /dev/null +++ b/arch/riscv/kernel/crash.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include + +#include + +static atomic_t waiting_for_crash_ipi =3D ATOMIC_INIT(0); + +inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) +{ + crash_save_cpu(regs, cpu); + + atomic_dec(&waiting_for_crash_ipi); + + local_irq_disable(); + +#ifdef CONFIG_HOTPLUG_CPU + if (cpu_has_hotplug(cpu)) + cpu_ops->cpu_stop(); +#endif + + for (;;) + wait_for_interrupt(); +} + +/* + * The number of CPUs online, not counting this CPU (which may not be + * fully online and so not counted in num_online_cpus()). + */ +static inline unsigned int num_other_online_cpus(void) +{ + unsigned int this_cpu_online =3D cpu_online(smp_processor_id()); + + return num_online_cpus() - this_cpu_online; +} + +void crash_smp_send_stop(void) +{ + static int cpus_stopped; + cpumask_t mask; + unsigned long timeout; + + /* + * This function can be called twice in panic path, but obviously + * we execute this only once. + */ + if (cpus_stopped) + return; + + cpus_stopped =3D 1; + + /* + * If this cpu is the only one alive at this point in time, online or + * not, there are no stop messages to be sent around, so just back out. + */ + if (num_other_online_cpus() =3D=3D 0) + return; + + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); + + atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); + + pr_crit("SMP: stopping secondary CPUs\n"); + send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + + /* Wait up to one second for other CPUs to stop */ + timeout =3D USEC_PER_SEC; + while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) + udelay(1); + + if (atomic_read(&waiting_for_crash_ipi) > 0) + pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", + cpumask_pr_args(&mask)); +} + +bool smp_crash_stop_failed(void) +{ + return (atomic_read(&waiting_for_crash_ipi) > 0); +} diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index e650dec448176..c4191b15b3547 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -24,22 +24,11 @@ #include #include =20 +#include #include #include #include =20 -enum ipi_message_type { - IPI_RESCHEDULE, - IPI_CALL_FUNC, - IPI_CPU_STOP, - IPI_CPU_CRASH_STOP, - IPI_IRQ_WORK, - IPI_TIMER, - IPI_CPU_BACKTRACE, - IPI_KGDB_ROUNDUP, - IPI_MAX -}; - unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init =3D { [0 ... NR_CPUS-1] =3D INVALID_HARTID }; @@ -75,33 +64,7 @@ static void ipi_stop(void) wait_for_interrupt(); } =20 -#ifdef CONFIG_KEXEC_CORE -static atomic_t waiting_for_crash_ipi =3D ATOMIC_INIT(0); - -static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) -{ - crash_save_cpu(regs, cpu); - - atomic_dec(&waiting_for_crash_ipi); - - local_irq_disable(); - -#ifdef CONFIG_HOTPLUG_CPU - if (cpu_has_hotplug(cpu)) - cpu_ops->cpu_stop(); -#endif - - for(;;) - wait_for_interrupt(); -} -#else -static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) -{ - unreachable(); -} -#endif - -static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_typ= e op) +void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) { __ipi_send_mask(ipi_desc[op], mask); } @@ -276,64 +239,6 @@ void smp_send_stop(void) cpumask_pr_args(cpu_online_mask)); } =20 -#ifdef CONFIG_KEXEC_CORE -/* - * The number of CPUs online, not counting this CPU (which may not be - * fully online and so not counted in num_online_cpus()). - */ -static inline unsigned int num_other_online_cpus(void) -{ - unsigned int this_cpu_online =3D cpu_online(smp_processor_id()); - - return num_online_cpus() - this_cpu_online; -} - -void crash_smp_send_stop(void) -{ - static int cpus_stopped; - cpumask_t mask; - unsigned long timeout; - - /* - * This function can be called twice in panic path, but obviously - * we execute this only once. - */ - if (cpus_stopped) - return; - - cpus_stopped =3D 1; - - /* - * If this cpu is the only one alive at this point in time, online or - * not, there are no stop messages to be sent around, so just back out. - */ - if (num_other_online_cpus() =3D=3D 0) - return; - - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &mask); - - atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); - - pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); - - /* Wait up to one second for other CPUs to stop */ - timeout =3D USEC_PER_SEC; - while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) - udelay(1); - - if (atomic_read(&waiting_for_crash_ipi) > 0) - pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", - cpumask_pr_args(&mask)); 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Mon, 27 Oct 2025 06:35:05 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.234]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d42558sm82144935ad.69.2025.10.27.06.34.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 06:35:05 -0700 (PDT) From: Yunhui Cui To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, conor@kernel.org, cuiyunhui@bytedance.com, luxu.kernel@bytedance.com, atishp@rivosinc.com, cleger@rivosinc.com, ajones@ventanamicro.com, apatel@ventanamicro.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, songshuaishuai@tinylab.org, bjorn@rivosinc.com, charlie@rivosinc.com, masahiroy@kernel.org, valentina.fernandezalanis@microchip.com, jassisinghbrar@gmail.com, conor.dooley@microchip.com Subject: [PATCH 3/3] riscv: crash: use NMI to stop the CPU Date: Mon, 27 Oct 2025 21:34:31 +0800 Message-Id: <20251027133431.15321-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20251027133431.15321-1-cuiyunhui@bytedance.com> References: <20251027133431.15321-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NMI is more robust than IPI for stopping CPUs during crashes, especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI eventid to implement NMI for stopping CPUs. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/crash.h | 1 + arch/riscv/include/asm/sbi.h | 1 + arch/riscv/kernel/crash.c | 31 +++++++++++++- drivers/firmware/riscv/sse_nmi.c | 71 +++++++++++++++++++++++++++++++- include/linux/sse_nmi.h | 8 ++++ 5 files changed, 109 insertions(+), 3 deletions(-) create mode 100644 include/linux/sse_nmi.h diff --git a/arch/riscv/include/asm/crash.h b/arch/riscv/include/asm/crash.h index b64df919277d4..5076f297cbc15 100644 --- a/arch/riscv/include/asm/crash.h +++ b/arch/riscv/include/asm/crash.h @@ -5,6 +5,7 @@ =20 #ifdef CONFIG_KEXEC_CORE void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs); +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs); #else static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *re= gs) { diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 52d3fdf2d4cc1..65cce85237879 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -487,6 +487,7 @@ enum sbi_sse_attr_id { #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS 0x00108000 #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED 0xffff0000 #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI 0xffff0001 +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI 0xffff0002 #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED 0xffff8000 =20 #define SBI_SSE_EVENT_PLATFORM BIT(14) diff --git a/arch/riscv/kernel/crash.c b/arch/riscv/kernel/crash.c index 12598bbc2df04..9f3f0becfdd95 100644 --- a/arch/riscv/kernel/crash.c +++ b/arch/riscv/kernel/crash.c @@ -3,14 +3,16 @@ #include #include #include +#include #include #include =20 +#include #include =20 static atomic_t waiting_for_crash_ipi =3D ATOMIC_INIT(0); =20 -inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) +void cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) { crash_save_cpu(regs, cpu); =20 @@ -27,6 +29,11 @@ inline void ipi_cpu_crash_stop(unsigned int cpu, struct = pt_regs *regs) wait_for_interrupt(); } =20 +inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) +{ + cpu_crash_stop(cpu, regs); +} + /* * The number of CPUs online, not counting this CPU (which may not be * fully online and so not counted in num_online_cpus()). @@ -38,6 +45,24 @@ static inline unsigned int num_other_online_cpus(void) return num_online_cpus() - this_cpu_online; } =20 +#ifdef CONFIG_RISCV_SSE_NMI +static int send_nmi_stop_cpu(cpumask_t *mask) +{ + unsigned int cpu; + int ret =3D 0; + + for_each_cpu(cpu, mask) + ret +=3D carsh_nmi_stop_cpu(cpu); + + return ret; +} +#else +static inline int send_nmi_stop_cpu(cpumask_t *mask) +{ + return -EOPNOTSUPP; +} +#endif + void crash_smp_send_stop(void) { static int cpus_stopped; @@ -66,7 +91,9 @@ void crash_smp_send_stop(void) atomic_set(&waiting_for_crash_ipi, num_other_online_cpus()); =20 pr_crit("SMP: stopping secondary CPUs\n"); - send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); + + if (send_nmi_stop_cpu(&mask)) + send_ipi_mask(&mask, IPI_CPU_CRASH_STOP); =20 /* Wait up to one second for other CPUs to stop */ timeout =3D USEC_PER_SEC; diff --git a/drivers/firmware/riscv/sse_nmi.c b/drivers/firmware/riscv/sse_= nmi.c index 2c1eaea2bbabc..152d787075345 100644 --- a/drivers/firmware/riscv/sse_nmi.c +++ b/drivers/firmware/riscv/sse_nmi.c @@ -4,13 +4,16 @@ =20 #include #include +#include #include =20 +#include #include #include =20 int unknown_nmi_panic; static struct sse_event *unknown_nmi_evt; +static struct sse_event *crash_nmi_evt; static struct ctl_table_header *unknown_nmi_sysctl_header; =20 static int __init setup_unknown_nmi_panic(char *str) @@ -32,6 +35,12 @@ const struct ctl_table unknown_nmi_table[] =3D { }, }; =20 +static inline struct sbiret sbi_sse_ecall(int fid, unsigned long arg0, + unsigned long arg1) +{ + return sbi_ecall(SBI_EXT_SSE, fid, arg0, arg1, 0, 0, 0, 0); +} + static int unknown_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) { pr_emerg("NMI received for unknown on CPU %d.\n", smp_processor_id()); @@ -73,9 +82,69 @@ static int unknown_nmi_init(void) return ret; } =20 +#ifdef CONFIG_KEXEC_CORE +int carsh_nmi_stop_cpu(unsigned int cpu) +{ + unsigned int hart_id =3D cpuid_to_hartid_map(cpu); + u32 evt =3D SBI_SSE_EVENT_LOCAL_CRASH_NMI; + struct sbiret ret; + + ret =3D sbi_sse_ecall(SBI_SSE_EVENT_INJECT, evt, hart_id); + if (ret.error) { + pr_err("Failed to signal event %x, error %ld\n", evt, ret.error); + return sbi_err_map_linux_errno(ret.error); + } + + return 0; +} + +static int crash_nmi_handler(u32 evt, void *arg, struct pt_regs *regs) +{ + cpu_crash_stop(smp_processor_id(), regs); + + return 0; +} + +static int crash_nmi_init(void) +{ + int ret; + + crash_nmi_evt =3D sse_event_register(SBI_SSE_EVENT_LOCAL_CRASH_NMI, 0, + crash_nmi_handler, NULL); + if (IS_ERR(crash_nmi_evt)) + return PTR_ERR(crash_nmi_evt); + + ret =3D sse_event_enable(crash_nmi_evt); + if (ret) { + sse_event_unregister(crash_nmi_evt); + return ret; + } + + pr_info("Using SSE for crash NMI event delivery\n"); + + return 0; +} +#endif + static int __init sse_nmi_init(void) { - return unknown_nmi_init(); + int ret; + + ret =3D unknown_nmi_init(); + if (ret) { + pr_err("Unknown_nmi_init failed with error %d\n", ret); + return ret; + } + +#ifdef CONFIG_KEXEC_CORE + ret =3D crash_nmi_init(); + if (ret) { + pr_err("Crash_nmi_init failed with error %d\n", ret); + return ret; + } +#endif + + return 0; } =20 late_initcall(sse_nmi_init); diff --git a/include/linux/sse_nmi.h b/include/linux/sse_nmi.h new file mode 100644 index 0000000000000..548a348ac0a46 --- /dev/null +++ b/include/linux/sse_nmi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __LINUX_RISCV_SSE_NMI_H +#define __LINUX_RISCV_SSE_NMI_H + +int carsh_nmi_stop_cpu(unsigned int cpu); + +#endif --=20 2.39.5