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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8964E41C0148; Mon, 27 Oct 2025 16:42:40 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org Cc: linux-spi@vger.kernel.org, michal.simek@amd.com, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jun Guo Subject: [PATCH v2 1/3] arm64: dts: cix: add a compatible string for the cix sky1 SoC Date: Mon, 27 Oct 2025 16:42:37 +0800 Message-Id: <20251027084239.2610141-2-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251027084239.2610141-1-jun.guo@cixtech.com> References: <20251027084239.2610141-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|TYZPR06MB6955:EE_ X-MS-Office365-Filtering-Correlation-Id: fb13b836-fd8f-48cf-a3bd-08de1534cadb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TAmNoyVmyEffJ7idMrMPKbpC2fY1spIqa+qdj95zk5S+WzrIerIG8Q+gfdnj?= =?us-ascii?Q?VDTdD9tCn0ty56LzQpRIzOifHaTGo9ETqw8Z5ZUdtBze+QnX+5RCbLqx2gfv?= =?us-ascii?Q?yW8mwobmh9NDHcEX4VvWe+ne7ME8Ggna5NPrKuH+Euw32PmjAmibF3RagLqi?= =?us-ascii?Q?/vs602TpSIQukZVqZEr2bFQS/uK7xeeJVNDkPBi/oJsiR47o1gErVlK6RyGp?= =?us-ascii?Q?mO81XfNJvDD/dexthtOaWDjyWSZNNRANvn3aAliYTnvgDaJQmKCeXRBWJnbr?= =?us-ascii?Q?1plbtV7y6U/d1drZ5JK3o1/M2sRRqfsaB58rU/e5BatDZ+LAPg+oHbY7sO9D?= =?us-ascii?Q?5GBJooVDQ6e9YAJkNsr12F2myPW4Z7wRojXedpOp7JCQgOF4fGYZ+HghsYHb?= =?us-ascii?Q?SieH37FoWAm/E3uwoHTZACctU99DmabIBHxytbtoWKUFyscizt1j4/St2HAP?= =?us-ascii?Q?Ex1sKKZI1C7kS2ZYdfz1mo9Ae3+2HRsDrpnK8y91+0+i7aIqrgRsHa70hrXW?= =?us-ascii?Q?H2E0Nu6XvBYew4coSfG2bACqR9s5KDvELZESoNy2sPgAR99PeDufeEsBb1mS?= =?us-ascii?Q?FOpwxCD9D2XbIFs0Nm6u3eUQ4qJg3NV4bwCNf1sYv9PGznvbuJJtu3PVk7Ym?= =?us-ascii?Q?/SIn9H47cT7LZzV65RtvyVqvnT+CglbAeVyrAOMk4vkQxJRE3vnWO+ScXgd3?= =?us-ascii?Q?woDsDN3xPTtxdtUnbmpZF+fEHiV3hMm/AdlvQPv+ksPnt/hw0Epz+jbBGuFx?= =?us-ascii?Q?Qe1Ta5t5LXETP+F74Nd9Oz2U9zq6MMqf1b5s3LoFXDKJZIdubFPozuS7/dUA?= =?us-ascii?Q?MhptxiUk+JMgDcFRgYMKhZ0QMisCcOQJZpMyEvDMW7vF8BNn15JtO8LBNDys?= =?us-ascii?Q?EKY7VnjRZGvEMGK6GM7Polve9ysI47WirrRMCQpslEtrJBc27qNSc2n2i2WL?= =?us-ascii?Q?GYDVut4f5kG3DiOifWdjhVXCNQzNuB2lAVWmyOuX/bu8iFf7BDJQ6ns13lZU?= =?us-ascii?Q?vGOGXGyZhhAsu50CF4d4hlmPyk1mPeluabHP0BROZKw5f49suFIxDE2/FP/5?= =?us-ascii?Q?1VLSnvGKPFbjZj4DZhcPtyLW+JI5tJTMSXVuj2zFdHxcAIN1AyK4p6dhiJTJ?= =?us-ascii?Q?yFBbnE5fZ9guep/qkMWLOC0zDsBjXSFF8SiQnWddfIRU3q+bJecOb/RHq4iU?= =?us-ascii?Q?BuTPz2L1TuuEY98s1rumE2/7iTHBYtwOVqL8flSfF+UxlH0BWKb5FAswMkgR?= =?us-ascii?Q?InQ9R2udia448WODOOp58wY4R/7ihUcVY5Mrk75OxrXcI7QIyWnZSyh1iiU9?= =?us-ascii?Q?l21RrmHcbORRDN9/tjHrkY9attpIEy3sfCPAaQyQAqMpV97N1uZcB7PsHKJA?= =?us-ascii?Q?LVGnkNGHRn4Hlt/NQYlIdaJSNDx8rielXs9DBjkOgNtiE9G+weuLzGIMBoWT?= =?us-ascii?Q?Sv0BZrxFr0esdWkzSXPCcyPx3/E0vF5aEfswzjVwV+PyGb1MCXjyMNjV2kp/?= =?us-ascii?Q?vdijG08Zd/1xxgE4MFwAnIQY+lOtkIUsjphw6VuL0n3S42pUalClGJQmQ2G+?= =?us-ascii?Q?8p+25k44YRBz1BuClLw=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2025 08:42:41.7298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb13b836-fd8f-48cf-a3bd-08de1534cadb X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6955 Content-Type: text/plain; charset="utf-8" The SPI IP design for the cix sky1 SoC uses a FIFO with a data width of 32 bits, instead of the default 8 bits. Therefore, a compatible string is added to specify the FIFO data width configuration for the cix sky1 SoC. Signed-off-by: Jun Guo --- arch/arm64/boot/dts/cix/sky1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index d21387224e79..189b9a3be55c 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -265,7 +265,7 @@ i2c7: i2c@4080000 { }; =20 spi0: spi@4090000 { - compatible =3D "cdns,spi-r1p6"; + compatible =3D "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; reg =3D <0x0 0x04090000 0x0 0x10000>; clocks =3D <&scmi_clk CLK_TREE_FCH_SPI0_APB>, <&scmi_clk CLK_TREE_FCH_SPI0_APB>; @@ -275,7 +275,7 @@ spi0: spi@4090000 { }; =20 spi1: spi@40a0000 { - compatible =3D "cdns,spi-r1p6"; + compatible =3D "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; reg =3D <0x0 0x040a0000 0x0 0x10000>; clocks =3D <&scmi_clk CLK_TREE_FCH_SPI1_APB>, <&scmi_clk CLK_TREE_FCH_SPI1_APB>; --=20 2.34.1 From nobody Sat Feb 7 21:15:29 2026 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023108.outbound.protection.outlook.com [40.107.44.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC1CE2F531F; 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id D713741C014A; Mon, 27 Oct 2025 16:42:40 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org Cc: linux-spi@vger.kernel.org, michal.simek@amd.com, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jun Guo Subject: [PATCH v2 2/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC Date: Mon, 27 Oct 2025 16:42:38 +0800 Message-Id: <20251027084239.2610141-3-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251027084239.2610141-1-jun.guo@cixtech.com> References: <20251027084239.2610141-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CC:EE_|TYZPR06MB7256:EE_ X-MS-Office365-Filtering-Correlation-Id: 360e80d3-ef3f-494f-f2ab-08de1534cad0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2025 08:42:41.6708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 360e80d3-ef3f-494f-f2ab-08de1534cad0 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CC.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB7256 - Add new compatible strings to the DT binding documents to support cix sky1 SoC; - Adjust the configuration of the compatible property to support both single-item and two-items cases.=E2=80=8B=E2=80=8B Signed-off-by: Jun Guo --- .../devicetree/bindings/spi/spi-cadence.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Docum= entation/devicetree/bindings/spi/spi-cadence.yaml index 8de96abe9da1..e75b142a1368 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -14,9 +14,14 @@ allOf: =20 properties: compatible: - enum: - - cdns,spi-r1p6 - - xlnx,zynq-spi-r1p6 + oneOf: + - enum: + - cdns,spi-r1p6 + - xlnx,zynq-spi-r1p6 + - items: + - enum: + - cix,sky1-spi-r1p6 + - const: cdns,spi-r1p6 =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sat Feb 7 21:15:29 2026 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022093.outbound.protection.outlook.com [40.107.75.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05D012F068F; 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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2FFDB40A5A13; Mon, 27 Oct 2025 16:42:41 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org Cc: linux-spi@vger.kernel.org, michal.simek@amd.com, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jun Guo Subject: [PATCH v2 3/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32 Date: Mon, 27 Oct 2025 16:42:39 +0800 Message-Id: <20251027084239.2610141-4-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251027084239.2610141-1-jun.guo@cixtech.com> References: <20251027084239.2610141-1-jun.guo@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CE:EE_|PUZPR06MB6248:EE_ X-MS-Office365-Filtering-Correlation-Id: 713d70e3-f47c-47d2-b083-08de1534cbbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wtE97W30gffDFkP/pjTygiUnREAMDUEua7h7DUEAoVxAnXVqrl0bbQyrF2yt?= =?us-ascii?Q?jc3KQ7oU0TROZWFHnb9J+BqVbf5Cn+muFSeYmkBEsF72y0Ir0EchbZzRuhRu?= =?us-ascii?Q?pY4wSZdlKhAdimxcB/f2jgrpxdl5m824VQ0L2LZzx8VztVxTpzvtMrOPQSXR?= =?us-ascii?Q?qEYzdVgqWNVTZ6DNVopk76xq0rMii3AzP9/diJgSqBkrWYsoO+aKSpeOA5XB?= =?us-ascii?Q?ACA2v1BURULDOt2eOkLbLqXkKyvJgaSgGxFn7DcN4opJD4ThiH3KuzsF+jmF?= =?us-ascii?Q?NGc1sLQnBR3AimAI1oW+wFKa2rokl22nZaiyw3Oe/Z0uxh9gimm0jp7Pmh/2?= =?us-ascii?Q?sX1usXY2wCOnG+mK9D1UxJNwbUoN0dQAS0//yt9Ee8QXCIlHXwu0RRBg9gdS?= =?us-ascii?Q?8NTFvY6WA48fh2lRx0evaBr4eHOLCIa0HfvsBW/gdlXgUmksAmYeifWAnZ+K?= =?us-ascii?Q?+e/Q3+BuWPdrZtjEfMICvmgxDEsvZBfxYyGJ3JlcbuiBNcpLqbWEbGL6WN+P?= =?us-ascii?Q?eS77VgvSuggFhg8Vo0tTXTh2ZDX7iZaV7ilF/PD1fJZ5pEov6mDhyDBr3hbq?= =?us-ascii?Q?f+bRrkYS9Q58dCNlf9C60O++AChZGX/IBhcv+Ghuutl+M/MNsX3FGhE76hkc?= =?us-ascii?Q?Qp9EJ4YjlNq93c0d/PEAQ+aJEhFXRULcOzMUYDjyb8CGuRuB0U3+Jdz66SFC?= =?us-ascii?Q?wj5G1qUENyyx8suYHAU04yL8ri+KtN48uSKmu8iWt9hYcK9bhAYIk0P/Bszg?= =?us-ascii?Q?QgshmJmrCZnP7sN1bWGYUBFrbw0ot9c4Cw/uvd6SX7pR7PXgIR42sNRfJZJw?= =?us-ascii?Q?0KHN1ges8ydN1R7mEmcsHf+K0JupyuLQ1GlJkLZYhZSfqWi3K1d0n0hQclod?= =?us-ascii?Q?SptXYRisDdXHac4IpcVzXjtX4qKUfq9OlJEuszhnETzz95Z/x+jxifRr4bQa?= =?us-ascii?Q?GrcO4Omw3XzyKEGX3UMsSvO9MhrCNpYKY8EG1N4LWMBN5WjTSH9rhpmiJctE?= =?us-ascii?Q?eVtEfNIK+p/C+v5bLNpzDl8aQaY0xKsFHDmFoWS9BET/dj4Cfx5wSdzXhUBX?= =?us-ascii?Q?aLlkW/WCvKZcNK5KxswBfJG/nLkrQltsxqudqUmjmQRyrfvnQ/3dz8mdV2jp?= =?us-ascii?Q?dBYXlZnOgPv2Mmo2odaLLWDUCUkV55P+Dln7O0gTJxjy8mddQGKuNHTC6pUS?= =?us-ascii?Q?Ck622U933sBkrpWW9/yYAjs6iBrvPyiFEkZTUC1GPxR8/j64YWeEluzJScVT?= =?us-ascii?Q?p7ddq4LsJzFOVBm2otQ48gtyjZMoPCbovcUUD/jEMOTBt6EKOhK07TvaCOCa?= =?us-ascii?Q?eqTpmcuwAPYTaZ6OHnXDioTH/2stS7Q94SYu1z4cnFlgok5WaCvwVuTM7MnZ?= =?us-ascii?Q?Pai5tAp2RXzr/7JpLZtkYlnHj/Jv3rwBKFdl2MZhZAYMgMudFi+Zk1ckiMX1?= =?us-ascii?Q?phGmIwM1OXmHJ9Q34NlW66HOGEbcsxGU+fT0EEnOefuhbUpFUD/0m9Fd21Vo?= =?us-ascii?Q?03MoPPCsATspEPX32bIhUJSTxRtPf6hHwSB9lptFjFNyOMFky2cWU9Fe6fWk?= =?us-ascii?Q?1Dg5NFbmNGK/HBybmtc=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2025 08:42:43.1999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 713d70e3-f47c-47d2-b083-08de1534cbbc X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CE.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB6248 Content-Type: text/plain; charset="utf-8" The default FIFO data width of the Cadence SPI IP is 8 bits, but the hardware supports configurations of 16 bits and 32 bits. This patch enhances the driver to support communication with both 16-bits and 32-bits FIFO data widths. Signed-off-by: Jun Guo --- drivers/spi/spi-cadence.c | 106 +++++++++++++++++++++++++++++++++----- 1 file changed, 93 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 5ae09b21d23a..47054da630d0 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -109,6 +109,7 @@ * @rxbuf: Pointer to the RX buffer * @tx_bytes: Number of bytes left to transfer * @rx_bytes: Number of bytes requested + * @n_bytes: Number of bytes per word * @dev_busy: Device busy flag * @is_decoded_cs: Flag for decoder property set or not * @tx_fifo_depth: Depth of the TX FIFO @@ -120,16 +121,24 @@ struct cdns_spi { struct clk *pclk; unsigned int clk_rate; u32 speed_hz; - const u8 *txbuf; - u8 *rxbuf; + const void *txbuf; + void *rxbuf; int tx_bytes; int rx_bytes; + u8 n_bytes; u8 dev_busy; u32 is_decoded_cs; unsigned int tx_fifo_depth; struct reset_control *rstc; }; =20 +enum cdns_spi_frame_n_bytes { + CDNS_SPI_N_BYTES_NULL =3D 0, + CDNS_SPI_N_BYTES_U8 =3D 1, + CDNS_SPI_N_BYTES_U16 =3D 2, + CDNS_SPI_N_BYTES_U32 =3D 4 +}; + /* Macros for the SPI controller read/write */ static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) { @@ -305,6 +314,78 @@ static int cdns_spi_setup_transfer(struct spi_device *= spi, return 0; } =20 +static u8 cdns_spi_n_bytes(struct spi_transfer *transfer) +{ + if (transfer->bits_per_word <=3D 8) + return CDNS_SPI_N_BYTES_U8; + else if (transfer->bits_per_word <=3D 16) + return CDNS_SPI_N_BYTES_U16; + else + return CDNS_SPI_N_BYTES_U32; +} + +static inline void cdns_spi_reader(struct cdns_spi *xspi) +{ + u32 rxw =3D 0; + + if (xspi->rxbuf && !IS_ALIGNED((uintptr_t)xspi->rxbuf, xspi->n_bytes)) { + pr_err("%s: rxbuf address is not aligned for %d bytes\n", + __func__, xspi->n_bytes); + return; + } + + rxw =3D cdns_spi_read(xspi, CDNS_SPI_RXD); + if (xspi->rxbuf) { + switch (xspi->n_bytes) { + case CDNS_SPI_N_BYTES_U8: + *(u8 *)xspi->rxbuf =3D rxw; + break; + case CDNS_SPI_N_BYTES_U16: + *(u16 *)xspi->rxbuf =3D rxw; + break; + case CDNS_SPI_N_BYTES_U32: + *(u32 *)xspi->rxbuf =3D rxw; + break; + default: + pr_err("%s invalid n_bytes %d\n", __func__, + xspi->n_bytes); + return; + } + xspi->rxbuf =3D (u8 *)xspi->rxbuf + xspi->n_bytes; + } +} + +static inline void cdns_spi_writer(struct cdns_spi *xspi) +{ + u32 txw =3D 0; + + if (xspi->txbuf && !IS_ALIGNED((uintptr_t)xspi->txbuf, xspi->n_bytes)) { + pr_err("%s: txbuf address is not aligned for %d bytes\n", + __func__, xspi->n_bytes); + return; + } + + if (xspi->txbuf) { + switch (xspi->n_bytes) { + case CDNS_SPI_N_BYTES_U8: + txw =3D *(u8 *)xspi->txbuf; + break; + case CDNS_SPI_N_BYTES_U16: + txw =3D *(u16 *)xspi->txbuf; + break; + case CDNS_SPI_N_BYTES_U32: + txw =3D *(u32 *)xspi->txbuf; + break; + default: + pr_err("%s invalid n_bytes %d\n", __func__, + xspi->n_bytes); + return; + } + cdns_spi_write(xspi, CDNS_SPI_TXD, txw); + xspi->txbuf =3D (u8 *)xspi->txbuf + xspi->n_bytes; + } +} + /** * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO * @xspi: Pointer to the cdns_spi structure @@ -321,23 +402,14 @@ static void cdns_spi_process_fifo(struct cdns_spi *xs= pi, int ntx, int nrx) =20 while (ntx || nrx) { if (nrx) { - u8 data =3D cdns_spi_read(xspi, CDNS_SPI_RXD); - - if (xspi->rxbuf) - *xspi->rxbuf++ =3D data; - + cdns_spi_reader(xspi); nrx--; } =20 if (ntx) { - if (xspi->txbuf) - cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); - else - cdns_spi_write(xspi, CDNS_SPI_TXD, 0); - + cdns_spi_writer(xspi); ntx--; } - } } =20 @@ -454,6 +526,10 @@ static int cdns_transfer_one(struct spi_controller *ct= lr, if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) udelay(10); =20 + xspi->n_bytes =3D cdns_spi_n_bytes(transfer); + xspi->tx_bytes =3D DIV_ROUND_UP(xspi->tx_bytes, xspi->n_bytes); + xspi->rx_bytes =3D DIV_ROUND_UP(xspi->rx_bytes, xspi->n_bytes); + cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0); =20 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); @@ -654,6 +730,9 @@ static int cdns_spi_probe(struct platform_device *pdev) ctlr->mode_bits =3D SPI_CPOL | SPI_CPHA; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); =20 + if (of_device_is_compatible(pdev->dev.of_node, "cix,sky1-spi-r1p6")) + ctlr->bits_per_word_mask |=3D SPI_BPW_MASK(16) | SPI_BPW_MASK(32); + if (!spi_controller_is_target(ctlr)) { ctlr->mode_bits |=3D SPI_CS_HIGH; ctlr->set_cs =3D cdns_spi_chipselect; @@ -797,6 +876,7 @@ static const struct dev_pm_ops cdns_spi_dev_pm_ops =3D { =20 static const struct of_device_id cdns_spi_of_match[] =3D { { .compatible =3D "xlnx,zynq-spi-r1p6" }, + { .compatible =3D "cix,sky1-spi-r1p6" }, { .compatible =3D "cdns,spi-r1p6" }, { /* end of table */ } }; --=20 2.34.1