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Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_ctrls.c | 2 +- drivers/media/platform/qcom/iris/iris_platform_common.h | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 754a5ad718bc37630bb861012301df7a2e7342a1..9da050aa1f7ce8152dfa46a706e= 2c27adfb5d6ce 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -301,7 +301,7 @@ int iris_ctrls_init(struct iris_inst *inst) =20 void iris_session_init_caps(struct iris_core *core) { - struct platform_inst_fw_cap *caps; + const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 caps =3D core->iris_platform_data->inst_fw_caps_dec; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 58d05e0a112eed25faea027a34c719c89d6c3897..17ed86bf78bb3b0bc3f0862253f= ba6505ac3d164 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -215,9 +215,9 @@ struct iris_platform_data { const char *fwname; u32 pas_id; struct platform_inst_caps *inst_caps; - struct platform_inst_fw_cap *inst_fw_caps_dec; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; - struct platform_inst_fw_cap *inst_fw_caps_enc; + const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; struct tz_cp_config *tz_cp_config_data; u32 core_arch; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 36d69cc73986b74534a2912524c8553970fd862e..cbf38e13f89e5c4c46e759fbb86= 777854d751552 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -19,7 +19,7 @@ #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -203,7 +203,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_d= ec[] =3D { }, }; =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 35ea0efade73caa687d300779c5b1dc3b17a0128..87517361a1cf4b6fe53b8a14831= 88670df52c7e7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -5,7 +5,7 @@ =20 #define BITRATE_MAX 245000000 =20 -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -189,7 +189,7 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs8300_= dec[] =3D { }, }; =20 -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 16486284f8acccf6a95a27f6003e885226e28f4d..e29cba993fde922b579eb7e5a59= ae34bb46f9f0f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -17,7 +17,7 @@ #define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, @@ -38,7 +38,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec= [] =3D { }, }; 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Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_platform_common.h | 10 +++++----- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 8 ++++---- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 17ed86bf78bb3b0bc3f0862253fba6505ac3d164..5ffc1874e8c6362b1c650e912c2= 30e9c4e3bd160 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,11 +41,11 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 -extern struct iris_platform_data qcs8300_data; -extern struct iris_platform_data sm8250_data; -extern struct iris_platform_data sm8550_data; -extern struct iris_platform_data sm8650_data; -extern struct iris_platform_data sm8750_data; +extern const struct iris_platform_data qcs8300_data; +extern const struct iris_platform_data sm8250_data; +extern const struct iris_platform_data sm8550_data; +extern const struct iris_platform_data sm8650_data; +extern const struct iris_platform_data sm8750_data; =20 enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index cbf38e13f89e5c4c46e759fbb86777854d751552..b444e816355624bca8248cce9da= 7adcd7caf6c5b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -737,7 +737,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -struct iris_platform_data sm8550_data =3D { +const struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -827,7 +827,7 @@ struct iris_platform_data sm8550_data =3D { * - controller_rst_tbl to sm8650_controller_reset_table * - fwname to "qcom/vpu/vpu33_p4.mbn" */ -struct iris_platform_data sm8650_data =3D { +const struct iris_platform_data sm8650_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -912,7 +912,7 @@ struct iris_platform_data sm8650_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 -struct iris_platform_data sm8750_data =3D { +const struct iris_platform_data sm8750_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -998,7 +998,7 @@ struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 * - inst_fw_caps to inst_fw_cap_qcs8300 */ -struct iris_platform_data qcs8300_data =3D { +const struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index e29cba993fde922b579eb7e5a59ae34bb46f9f0f..66a5bdd24d8a0e98b0554a01943= 8bf4caa1dc43c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -314,7 +314,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59301f83cb5sm2253474e87.102.2025.10.27.05.27.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 05:27:05 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 27 Oct 2025 14:27:01 +0200 Subject: [PATCH v5 3/6] media: iris: stop encoding PIPE value into fw_caps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-iris-sc7280-v5-3-5eeab5670e4b@oss.qualcomm.com> References: <20251027-iris-sc7280-v5-0-5eeab5670e4b@oss.qualcomm.com> In-Reply-To: <20251027-iris-sc7280-v5-0-5eeab5670e4b@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4228; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=NcGTRwOQ90/nrMX55xwrZxHeSbupJ7buA4aBXqPJnXc=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ8b/VFGGs5uTbMNE19soJryZ2FO/5lx8c0czm8T++wmc/ PnHVes7GY1ZGBi5GGTFFFl8ClqmxmxKDvuwY2o9zCBWJrApXJwCMJHXF9j/R0/5enrR0qs3VmyY xS3l965rNbt84zuHE6n2uwWFLl5ou/rufO2u9w2vavjkzXIK+CL1+VS+6dtWnlOKebJeYlvXEvH Ot9MXltz5+5XfUaxAWs/yconOl+LY9jvV58vZ59/4/OnkLzYX/3Xik4S6wzbb3zMoufutKU6SSX m+6cH6O0uiGiMne+34tcn9196PRof+frC58Ndz7QLhP/vcfhkvv5/whDOv0XZ2p7vRZs+qeZdKf /mlO/5mkF4+7fctBd1axYx/UrJpiYxc69+YXp93ZvZGhcYYw84jkeeKrPl57TlVdDZZ6Gowpf4p Xvvc2dF1zfJ5NSn8gi+9+aNjbm99/2NFlNM1jnN/2II1AA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI3MDExNiBTYWx0ZWRfX3BtLv2v99zeM Z+QbQF1JNJzdTS85iPrKF5NkCKHshjPquAO80pbLSVoKpgEGbM4BNnvVqjmnazJdpvwmgj7Qm4k tpGakKdG4cz1dpdk3Jt/fL7AKrTWpEFszUZHRIH6bybtVE+9PgG//O7OGRU754DGdAmJT0CscxO z1HRrdA5J1TCnPmdkdvutzWCx2ivP1RTGnJ/C9zumcGyWKocXR0hJwHOTNPTZkpPke+RhoWmLcG u/rOTjiq9MkJynHZ+Nj2VU89eNxGzgZ8Gj1wn6bEu8XN3y8W693SSlkviVeRdVWJJFbobwZ7kN1 VzmnP5vTsyXV8PhTM511TIfyPj4OH5L9Jca1bndj5t3kqMfiuRawEH1EQy5z0KwBGcRK9uvLhiR 5UHnCWAjAM7b3YZD/BE/s4hBFBkUMg== X-Authority-Analysis: v=2.4 cv=RIW+3oi+ c=1 sm=1 tr=0 ts=68ff651d cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=SYGkZlDhJRt_0546ciQA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: jfzPFCAQzIoonYiW7nu9S3XifdtHnNjv X-Proofpoint-GUID: jfzPFCAQzIoonYiW7nu9S3XifdtHnNjv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-27_05,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510270116 The value of the PIPE property depends on the number of pipes available on the platform and is frequently the only difference between several fw_caps. In order to reduce duplciation, use num_vpp_pipe from the iris_platform_data rather than hardcoding the value into the fw_cap. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_ctrls.c | 16 ++++++++++++= +--- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 +--- drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 +--- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 4 +--- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce..c0b3a09ad3e3dfb0a47e3603a80= 89cf61390fda8 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -313,13 +313,23 @@ void iris_session_init_caps(struct iris_core *core) continue; =20 core->inst_fw_caps_dec[cap_id].cap_id =3D caps[i].cap_id; - core->inst_fw_caps_dec[cap_id].min =3D caps[i].min; - core->inst_fw_caps_dec[cap_id].max =3D caps[i].max; core->inst_fw_caps_dec[cap_id].step_or_mask =3D caps[i].step_or_mask; - core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; core->inst_fw_caps_dec[cap_id].flags =3D caps[i].flags; core->inst_fw_caps_dec[cap_id].hfi_id =3D caps[i].hfi_id; core->inst_fw_caps_dec[cap_id].set =3D caps[i].set; + + if (cap_id =3D=3D PIPE) { + core->inst_fw_caps_dec[cap_id].value =3D + core->iris_platform_data->num_vpp_pipe; + core->inst_fw_caps_dec[cap_id].min =3D + core->iris_platform_data->num_vpp_pipe; + core->inst_fw_caps_dec[cap_id].max =3D + core->iris_platform_data->num_vpp_pipe; + } else { + core->inst_fw_caps_dec[cap_id].min =3D caps[i].min; + core->inst_fw_caps_dec[cap_id].max =3D caps[i].max; + core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; + } } =20 caps =3D core->iris_platform_data->inst_fw_caps_enc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index b444e816355624bca8248cce9da7adcd7caf6c5b..fb3fa1665c523fbe01df590f14d= 8012da3a8dd09 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -160,10 +160,8 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8550_dec[] =3D { }, { .cap_id =3D PIPE, - .min =3D PIPE_1, - .max =3D PIPE_4, + /* .max, .min and .value are set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_4, .hfi_id =3D HFI_PROP_PIPE, .set =3D iris_set_pipe, }, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 87517361a1cf4b6fe53b8a1483188670df52c7e7..7ae50ab22f8c577675a10b767e1= d5f3cfe16d439 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -146,10 +146,8 @@ static const struct platform_inst_fw_cap inst_fw_cap_q= cs8300_dec[] =3D { }, { .cap_id =3D PIPE, - .min =3D PIPE_1, - .max =3D PIPE_2, + /* .max, .min and .value are set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_2, .hfi_id =3D HFI_PROP_PIPE, .set =3D iris_set_pipe, }, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 66a5bdd24d8a0e98b0554a019438bf4caa1dc43c..805179fba0c41bd7c9e3e5de365= 912de2b56c182 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -20,10 +20,8 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, - .min =3D PIPE_1, - .max =3D PIPE_4, + /* .max, .min and .value are set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_4, .hfi_id =3D HFI_PROPERTY_PARAM_WORK_ROUTE, .set =3D iris_set_pipe, }, --=20 2.47.3 From nobody Sun Feb 8 10:49:17 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18797303A09 for ; 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Drop the QCS8300-specific tables and use generic one instead. The differences between QCS8300 and SM8550 data comes from a non-conflict merge of commit d22037f3fd33 ("media: iris: Set platform capabilities to firmware for encoder video device") (which added .set callbacks), and commit 6bdfa3f947a7 ("media: iris: Add platform-specific capabilities for encoder video device") (which added QCS8300 data, but not the callbacks). Reviewed-by: Vikash Garodia Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +- .../platform/qcom/iris/iris_platform_qcs8300.h | 532 +----------------= ---- 2 files changed, 8 insertions(+), 533 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index fb3fa1665c523fbe01df590f14d8012da3a8dd09..2631b7317e086084e5be95e2e03= 70c44ea255df7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -994,7 +994,6 @@ const struct iris_platform_data sm8750_data =3D { /* * Shares most of SM8550 data except: * - inst_caps to platform_inst_cap_qcs8300 - * - inst_fw_caps to inst_fw_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, @@ -1020,10 +1019,10 @@ const struct iris_platform_data qcs8300_data =3D { .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps_dec =3D inst_fw_cap_qcs8300_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_dec), - .inst_fw_caps_enc =3D inst_fw_cap_qcs8300_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_enc), + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D &tz_cp_config_sm8550, .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 7ae50ab22f8c577675a10b767e1d5f3cfe16d439..a97a9f932b75a88535df66160df= c934220919ed5 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -3,535 +3,9 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -#define BITRATE_MAX 245000000 =20 -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { - { - .cap_id =3D PROFILE_H264, - .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, - .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), - .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D PROFILE_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), - .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D PROFILE_VP9, - .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, - .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | - BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), - .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_H264, - .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_1, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, - .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_VP9, - .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0), - .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D TIER, - .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), - .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, - .hfi_id =3D HFI_PROP_TIER, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, - .min =3D DEFAULT_MAX_HOST_BUF_COUNT, - .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, - .step_or_mask =3D 1, - .value =3D DEFAULT_MAX_HOST_BUF_COUNT, - .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, - .flags =3D CAP_FLAG_INPUT_PORT, - .set =3D iris_set_u32, - }, - { - .cap_id =3D STAGE, - .min =3D STAGE_1, - .max =3D STAGE_2, - .step_or_mask =3D 1, - .value =3D STAGE_2, - .hfi_id =3D HFI_PROP_STAGE, - .set =3D iris_set_stage, - }, - { - .cap_id =3D PIPE, - /* .max, .min and .value are set via platform data */ - .step_or_mask =3D 1, - .hfi_id =3D HFI_PROP_PIPE, - .set =3D iris_set_pipe, - }, - { - .cap_id =3D POC, - .min =3D 0, - .max =3D 2, - .step_or_mask =3D 1, - .value =3D 1, - .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, - }, - { - .cap_id =3D CODED_FRAMES, - .min =3D CODED_FRAMES_PROGRESSIVE, - .max =3D CODED_FRAMES_PROGRESSIVE, - .step_or_mask =3D 0, - .value =3D CODED_FRAMES_PROGRESSIVE, - .hfi_id =3D HFI_PROP_CODED_FRAMES, - }, - { - .cap_id =3D BIT_DEPTH, - .min =3D BIT_DEPTH_8, - .max =3D BIT_DEPTH_8, - .step_or_mask =3D 1, - .value =3D BIT_DEPTH_8, - .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, - }, - { - .cap_id =3D RAP_FRAME, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 1, - .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, - .flags =3D CAP_FLAG_INPUT_PORT, - .set =3D iris_set_u32, - }, -}; - -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { - { - .cap_id =3D PROFILE_H264, - .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, - .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), - .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D PROFILE_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), - .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D LEVEL_H264, - .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), - .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D LEVEL_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, - .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D STAGE, - .min =3D STAGE_1, - .max =3D STAGE_2, - .step_or_mask =3D 1, - .value =3D STAGE_2, - .hfi_id =3D HFI_PROP_STAGE, - }, - { - .cap_id =3D HEADER_MODE, - .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, - .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | - BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), - .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, - .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D PREPEND_SPSPPS_TO_IDR, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 0, - }, - { - .cap_id =3D BITRATE, - .min =3D 1, - .max =3D BITRATE_MAX, - .step_or_mask =3D 1, - .value =3D BITRATE_DEFAULT, - .hfi_id =3D HFI_PROP_TOTAL_BITRATE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D BITRATE_PEAK, - .min =3D 1, - .max =3D BITRATE_MAX, - .step_or_mask =3D 1, - .value =3D BITRATE_DEFAULT, - .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D BITRATE_MODE, - .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, - .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | - BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), - .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, - .hfi_id =3D HFI_PROP_RATE_CONTROL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D FRAME_SKIP_MODE, - .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, - .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), - .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D FRAME_RC_ENABLE, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 1, - }, - { - .cap_id =3D GOP_SIZE, - .min =3D 0, - .max =3D INT_MAX, - .step_or_mask =3D 1, - .value =3D 2 * DEFAULT_FPS - 1, - .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D ENTROPY_MODE, - .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, - .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | - BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), - .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, - .hfi_id =3D HFI_PROP_CABAC_SESSION, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D MIN_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - .hfi_id =3D HFI_PROP_MIN_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MIN_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - .hfi_id =3D HFI_PROP_MIN_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MAX_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - .hfi_id =3D HFI_PROP_MAX_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MAX_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - .hfi_id =3D HFI_PROP_MAX_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D I_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D I_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D P_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D P_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D B_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D B_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D I_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D I_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D P_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D P_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D B_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D B_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D I_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D I_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D P_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D P_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D B_FRAME_QP_H264, - .min =3D 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Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | = 2 +- .../platform/qcom/iris/{iris_platform_sm8250.c =3D> iris_platform_gen1.c} = | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 13270cd6d899852dded675b33d37f5919b81ccba..fad3be044e5fe783db697a592b4= f09de4d42d0d2 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -26,7 +26,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_vpu_common.o \ =20 ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) -qcom-iris-objs +=3D iris_platform_sm8250.o +qcom-iris-objs +=3D iris_platform_gen1.o endif =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_gen1.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_platform_sm8250.c rename to drivers/media/platform/qcom/iris/iris_platform_gen1.c --=20 2.47.3 From nobody Sun Feb 8 10:49:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B99930F94C for ; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59301f83cb5sm2253474e87.102.2025.10.27.05.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 05:27:12 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 27 Oct 2025 14:27:04 +0200 Subject: [PATCH v5 6/6] media: iris: enable support for SC7280 platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-iris-sc7280-v5-6-5eeab5670e4b@oss.qualcomm.com> References: <20251027-iris-sc7280-v5-0-5eeab5670e4b@oss.qualcomm.com> In-Reply-To: <20251027-iris-sc7280-v5-0-5eeab5670e4b@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11575; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=t1CBvWMfN655XxZugDbjqKvfK7Hnxfownu0/2DhhsmY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBo/2UVHzdHaKwryTr5Ve+s9z8lc8kfVUOe//Iee GOD7RDTOqKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaP9lFQAKCRCLPIo+Aiko 1cryB/4mxqclcENIP+UIykLBTJcKwI51oiN5z8igSjTvnTZGX3ChDqikhshF1VWSFzw6QMuCzfe AU6ZjdPiaUnmL5Grx96TAtn+gnDPH0br76315S/aq+vvtm4ReLTbBXL2NXfG76e7tAtqIsQn0Rr UERSekH5v8MeFdpEiXgPwtvkaSf+LFgiWOg4IlSUlsL/y0NQ8C4O8D9L+5MziZhzZKoO8bCb7rI 73THSxHf1DS/n7jmV+WFe/HmsyHUl10lqRd621ffgFjffdDoEf8mXLAc8zuNE0+gPf4Sk3hHMon ck0N3HCmHPUB0w/du/oL4Tsci9S7Veyb8ray4fCH0VnpHQdv X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: VogsuWEEfotprpo1mfm329ex5TnaZDc9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI3MDExNiBTYWx0ZWRfX9GG5ibw3TD3v lcZgQ84S+oNmRFZeMWVZQyFqX6JmCWjjg6FpXnujJBc5zzSrQbBbErXEShLxE4v1yB5shcGGRS9 yqlDbd0niwAjnk0WKDCmAejQlZbqvwSL7YkOuqQvhJ/P3J9JIhfw3P+DKaZlVRBfIj6r+t+xYfb all+S/lSzkCcIY0r/ejuDzvqIDpwCluFqTeT2bsZmM4jHubBf5RYaSJphViluGV0n2/qJxbZr+q nKmr/qE+7Rbywb+/Gh4Mfn0yZIYH8TB0hJ0rcytiLgrj0VtzHPHKFz+SmxKBbsIDOWJLiiuTpc3 uZ+C+o0G5rddcvc23moyuUsy29Cm/Heds6FUp0DmJQMv+TUMpWM7RHoltb0fEXQ/kGbSZqG5PLi Ae/DSf9WrWeJu3+AIWhkRqrWCM1E0A== X-Authority-Analysis: v=2.4 cv=AJoZt3K7 c=1 sm=1 tr=0 ts=68ff6526 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=pG0Ruh8lDxDpiiRDS04A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: VogsuWEEfotprpo1mfm329ex5TnaZDc9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-27_05,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510270116 As a part of migrating code from the old Venus driver to the new Iris one, add support for the SC7280 platform. It is very similar to SM8250, but it (currently) uses no reset controls (there is an optional GCC-generated reset, it will be added later) and no AON registers region. Extend the VPU ops to support optional clocks and skip the AON shutdown for this platform. Signed-off-by: Dmitry Baryshkov --- .../platform/qcom/iris/iris_platform_common.h | 4 ++ .../media/platform/qcom/iris/iris_platform_gen1.c | 53 ++++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_sc7280.h | 27 +++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ drivers/media/platform/qcom/iris/iris_resources.c | 2 +- drivers/media/platform/qcom/iris/iris_vpu2.c | 6 +++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 34 ++++++++++---- 7 files changed, 120 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 5ffc1874e8c6362b1c650e912c230e9c4e3bd160..8d8cdb56a3c7722c06287d4d10f= eed14ba2b254c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -42,6 +42,7 @@ enum pipe_type { }; =20 extern const struct iris_platform_data qcs8300_data; +extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; extern const struct iris_platform_data sm8550_data; extern const struct iris_platform_data sm8650_data; @@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data; enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ IRIS_CTRL_CLK, + IRIS_AHB_CLK, IRIS_HW_CLK, + IRIS_HW_AHB_CLK, IRIS_AXI1_CLK, IRIS_CTRL_FREERUN_CLK, IRIS_HW_FREERUN_CLK, @@ -224,6 +227,7 @@ struct iris_platform_data { u32 hw_response_timeout; struct ubwc_config_data *ubwc_config; u32 num_vpp_pipe; + bool no_aon; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 805179fba0c41bd7c9e3e5de365912de2b56c182..abe43557b16b3d41ea1360e7fee= 3e10fd13870e3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -12,6 +12,8 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 +#include "iris_platform_sc7280.h" + #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 #define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) @@ -362,3 +364,54 @@ const struct iris_platform_data sm8250_data =3D { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +const struct iris_platform_data sc7280_data =3D { + .get_instance =3D iris_hfi_gen1_get_instance, + .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu2_ops, + .set_preset_registers =3D iris_set_sm8250_preset_registers, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .bw_tbl_dec =3D sc7280_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sc7280_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl =3D sc7280_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p1.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8250, + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), + .tz_cp_config_data =3D &tz_cp_config_sm8250, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 1, + .no_aon =3D true, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps =3D (4096 * 2176 * 2 + 1920 * 1088) / 256 * 60, + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/driv= ers/media/platform/qcom/iris/iris_platform_sc7280.h new file mode 100644 index 0000000000000000000000000000000000000000..9e8ade674ff1a8c4e42b1a05a3d= e3097110e5f0d --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + + +#ifndef __IRIS_PLATFORM_SC7280_H__ +#define __IRIS_PLATFORM_SC7280_H__ + +static const struct bw_info sc7280_bw_table_dec[] =3D { + { ((3840 * 2160) / 256) * 60, 1896000, }, + { ((3840 * 2160) / 256) * 30, 968000, }, + { ((1920 * 1080) / 256) * 60, 618000, }, + { ((1920 * 1080) / 256) * 30, 318000, }, +}; + +static const char * const sc7280_opp_pd_table[] =3D { "cx" }; + +static const struct platform_clk_data sc7280_clk_table[] =3D { + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_HW_CLK, "vcodec_core" }, + {IRIS_HW_AHB_CLK, "vcodec_bus" }, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 00e99be16e087c4098f930151fd76cd381d721ce..9bc9b34c2576581635fa8d87eed= 1965657eb3eb3 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -357,6 +357,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &qcs8300_data, }, #if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS)) + { + .compatible =3D "qcom,sc7280-venus", + .data =3D &sc7280_data, + }, { .compatible =3D "qcom,sm8250-venus", .data =3D &sm8250_data, diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index cf32f268b703c1c042a9bcf146e444fff4f4990d..164490c49c95ee048670981fdab= 014d20436ef85 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -112,7 +112,7 @@ int iris_prepare_enable_clock(struct iris_core *core, e= num platform_clk_type clk =20 clock =3D iris_get_clk_by_type(core, clk_type); if (!clock) - return -EINVAL; + return -ENOENT; =20 return clk_prepare_enable(clock); } diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index de7d142316d2dc9ab0c4ad9cc8161c87ac949b4c..9c103a2e4e4eafee101a8a9b168= fdc8ca76e277d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -3,9 +3,15 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include +#include +#include + #include "iris_instance.h" #include "iris_vpu_common.h" =20 +#include "iris_vpu_register_defines.h" + static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..1460e1683025e49cfa55d1afbe2= 81e5db5a0d898 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -222,12 +222,14 @@ int iris_vpu_power_off_controller(struct iris_core *c= ore) =20 writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); =20 - writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONT= ROL); + if (!core->iris_platform_data->no_aon) { + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CON= TROL); =20 - ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, - val, val & BIT(0), 200, 2000); - if (ret) - goto disable_power; + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STAT= US, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + } =20 writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); =20 @@ -250,6 +252,7 @@ int iris_vpu_power_off_controller(struct iris_core *cor= e) writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); =20 disable_power: + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); @@ -261,6 +264,7 @@ void iris_vpu_power_off_hw(struct iris_core *core) { dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_HW_CLK); } =20 @@ -294,11 +298,17 @@ int iris_vpu_power_on_controller(struct iris_core *co= re) =20 ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); if (ret) - goto err_disable_clock; + goto err_disable_axi_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_AHB_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_ctrl_clock; =20 return 0; =20 -err_disable_clock: +err_disable_ctrl_clock: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); +err_disable_axi_clock: iris_disable_unprepare_clock(core, IRIS_AXI_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); @@ -318,13 +328,19 @@ int iris_vpu_power_on_hw(struct iris_core *core) if (ret) goto err_disable_power; =20 + ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_hw_clock; + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); if (ret) - goto err_disable_clock; + goto err_disable_hw_axi_clock; =20 return 0; =20 -err_disable_clock: +err_disable_hw_axi_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); +err_disable_hw_clock: iris_disable_unprepare_clock(core, IRIS_HW_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); --=20 2.47.3