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Mon, 27 Oct 2025 07:59:36 -0700 (PDT) From: Abel Vesa Date: Mon, 27 Oct 2025 16:59:18 +0200 Subject: [PATCH v3 1/7] dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-glymur-display-v3-1-aa13055818ac@linaro.org> References: <20251027-glymur-display-v3-0-aa13055818ac@linaro.org> In-Reply-To: <20251027-glymur-display-v3-0-aa13055818ac@linaro.org> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The MDSS/MDP display subsystem found on Glymur platform is 2 minor version increase compared to SM8750, which makes it incompatible with all previous platforms. So document it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- .../bindings/display/msm/qcom,glymur-mdss.yaml | 264 +++++++++++++++++= ++++ 1 file changed, 264 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2329ed96e6cb37bf63a686e966a= a81e690fc5dcd --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml @@ -0,0 +1,264 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur Display MDSS + +maintainers: + - Abel Vesa + +description: + Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DP interfaces, etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,glymur-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,glymur-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&dispcc_mdp_clk>; + clock-names =3D "bus", "nrt_bus", "core"; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_AC= TIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,glymur-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc_mdp_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible =3D "qcom,glymur-dp"; + reg =3D <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0x600>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + + clocks =3D <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>; + assigned-clock-parents =3D <&usb_1_ss0_qmpphy QMP_USB43DP_= DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP= _VCO_DIV_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP= _VCO_DIV_CLK>; + + operating-points-v2 =3D <&mdss_dp0_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + ports { + #address-cells =3D <1>; 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Mon, 27 Oct 2025 07:59:39 -0700 (PDT) Received: from hackbox.lan ([86.121.7.169]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952df682sm14624801f8f.43.2025.10.27.07.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 07:59:39 -0700 (PDT) From: Abel Vesa Date: Mon, 27 Oct 2025 16:59:19 +0200 Subject: [PATCH v3 2/7] dt-bindings: display: msm: Document the Glymur Display Processing Unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-glymur-display-v3-2-aa13055818ac@linaro.org> References: <20251027-glymur-display-v3-0-aa13055818ac@linaro.org> In-Reply-To: <20251027-glymur-display-v3-0-aa13055818ac@linaro.org> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add DPU for Qualcomm Glymur SoC which has very few changes compared to SM8750, just enough to make them incompatible. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index 0a46120dd8680371ed031f7773859716f49c3aa1..feb1b8030ae0e381118a9482252= a915199e19383 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,glymur-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu --=20 2.48.1 From nobody Fri Dec 19 20:32:57 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B728830BF6D for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Document the DisplayPort controller found in the Qualcomm Glymur SoC. There are 4 controllers and their new core revision is different when compared to all previous platforms, therefore being incompatible. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index aeb4e4f36044a0ff1e78ad47b867e232b21df509..26f5043748c166aa44be4e62445= a63106edf9578 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - qcom,glymur-dp - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp @@ -195,6 +196,7 @@ allOf: compatible: contains: enum: + - qcom,glymur-dp - qcom,sa8775p-dp - qcom,x1e80100-dp then: @@ -239,6 +241,7 @@ allOf: enum: # these platforms support 2 streams MST on some interfaces, # others are SST only + - qcom,glymur-dp - qcom,sc8280xp-dp - qcom,x1e80100-dp then: --=20 2.48.1 From nobody Fri Dec 19 20:32:57 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F93D30C628 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add Mobile Display Subsystem (MDSS) support for the Glymur platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/gpu/drm/msm/msm_mdss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2d0e3e784c044db8ac0c478446d211a982cf0350..60bd6af83a8846f2ad751ea625a= 20e419c80638b 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -553,6 +553,7 @@ static const struct msm_mdss_data data_153k6 =3D { =20 static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,mdss", .data =3D &data_153k6 }, + { .compatible =3D "qcom,glymur-mdss", .data =3D &data_57k }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,sa8775p-mdss", .data =3D &data_74k }, --=20 2.48.1 From nobody Fri Dec 19 20:32:57 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06EE93093CD for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add DPU version v12.2 support for the Glymur platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- .../drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 541 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 5 files changed, 550 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h new file mode 100644 index 0000000000000000000000000000000000000000..13bb43ba67d3f4f63ac492e0e1c= 5757b55e7b61b --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h @@ -0,0 +1,541 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Linaro Limited + */ + +#ifndef _DPU_12_2_GLYMUR_H +#define _DPU_12_2_GLYMUR_H + +static const struct dpu_caps glymur_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg glymur_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg glymur_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, { + .name =3D "ctl_6", .id =3D CTL_6, + .base =3D 0x1b000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 14), + }, { + .name =3D "ctl_7", .id =3D CTL_7, + .base =3D 0x1c000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 15), + }, +}; + +static const struct dpu_sspp_cfg glymur_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg glymur_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x4a000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x4b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg glymur_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_4", .id =3D DSPP_4, + .base =3D 0x5c000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_5", .id =3D DSPP_5, + .base =3D 0x5e000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_6", .id =3D DSPP_6, + .base =3D 0x60000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_7", .id =3D DSPP_7, + .base =3D 0x62000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg glymur_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x6f000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x70000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, +}; + +static const struct dpu_merge_3d_cfg glymur_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x51000, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg glymur_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x83000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x83000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, + +}; + +static const struct dpu_wb_cfg glymur_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg glymur_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7e200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7e600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg glymur_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x400, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x400, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x400, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x400, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name =3D "intf_4", .id =3D INTF_4, + .base =3D 0x38000, .len =3D 0x400, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + }, { + .name =3D "intf_5", .id =3D INTF_5, + .base =3D 0x39000, .len =3D 0x400, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_3, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + }, { + .name =3D "intf_6", .id =3D INTF_6, + .base =3D 0x3A000, .len =3D 0x400, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), + }, { + .name =3D "intf_7", .id =3D INTF_7, + .base =3D 0x3b000, .len =3D 0x400, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), + }, { + .name =3D "intf_8", .id =3D INTF_8, + .base =3D 0x3c000, .len =3D 0x400, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_perf_cfg glymur_perf_data =3D { + .max_bw_low =3D 18900000, + .max_bw_high =3D 28500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version glymur_mdss_ver =3D { + .core_major_ver =3D 12, + .core_minor_ver =3D 2, +}; + +const struct dpu_mdss_cfg dpu_glymur_cfg =3D { + .mdss_ver =3D &glymur_mdss_ver, + .caps =3D &glymur_dpu_caps, + .mdp =3D &glymur_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(glymur_ctl), + .ctl =3D glymur_ctl, + .sspp_count =3D ARRAY_SIZE(glymur_sspp), + .sspp =3D glymur_sspp, + .mixer_count =3D ARRAY_SIZE(glymur_lm), + .mixer =3D glymur_lm, + .dspp_count =3D ARRAY_SIZE(glymur_dspp), + .dspp =3D glymur_dspp, + .pingpong_count =3D ARRAY_SIZE(glymur_pp), + .pingpong =3D glymur_pp, + .dsc_count =3D ARRAY_SIZE(glymur_dsc), + .dsc =3D glymur_dsc, + .merge_3d_count =3D ARRAY_SIZE(glymur_merge_3d), + .merge_3d =3D glymur_merge_3d, + .wb_count =3D ARRAY_SIZE(glymur_wb), + .wb =3D glymur_wb, + .cwb_count =3D ARRAY_SIZE(glymur_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(glymur_intf), + .intf =3D glymur_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &glymur_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 6641455c4ec6a2d082644f1488ea5f5605ccc208..64e2f8a765530c7181292b3b3a7= d54c4e9431963 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -726,3 +726,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_10_0_sm8650.h" #include "catalog/dpu_12_0_sm8750.h" +#include "catalog/dpu_12_2_glymur.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f0768f54e9b3d5a3f5a7bec4b66127f2e2284cfd..4964e70610d1b6a2bf6456e767c= c30a8ea653349 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; }; =20 +extern const struct dpu_mdss_cfg dpu_glymur_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 175639c8bfbb9bbd02ed35f1780bcbd869f08c36..1ca22971aa9cb684648e492b4c5= 38fdfbfa6b5e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -149,6 +149,10 @@ enum dpu_dspp { DSPP_1, DSPP_2, DSPP_3, + DSPP_4, + DSPP_5, + DSPP_6, + DSPP_7, DSPP_MAX }; =20 @@ -159,6 +163,8 @@ enum dpu_ctl { CTL_3, CTL_4, CTL_5, + CTL_6, + CTL_7, CTL_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 4e5a8ecd31f7570beb45fd1629a131e70aaefea8..f4c9767c418d38eb487934da03b= 352ce7063df16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,glymur-dpu", .data =3D &dpu_glymur_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.48.1 From nobody Fri Dec 19 20:32:57 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8172030E824 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Qualcomm Glymur platform comes with 4 DisplayPort controllers, which have a different core revision compared to all previous platforms. Describe them and add the compatible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d87d47cc7ec3eb757ac192c411000bc50b824c59..9bd9cd5c1e03cc17598b222177b= 6682bbcd89f0c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -130,6 +130,14 @@ struct msm_dp_desc { bool wide_bus_supported; }; =20 +static const struct msm_dp_desc msm_dp_desc_glymur[] =3D { + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af64000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af6c000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, + {} +}; + static const struct msm_dp_desc msm_dp_desc_sa8775p[] =3D { { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, @@ -187,6 +195,7 @@ static const struct msm_dp_desc msm_dp_desc_x1e80100[] = =3D { }; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Describe the Universal Bandwidth Compression (UBWC) configuration for the new Glymur platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa --- drivers/soc/qcom/ubwc_config.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 15d373bff231d770e00fe0aee1b5a95c7b8a6305..7cca2afb68e3e9d33f3066f1deb= 3b9fcc01641a1 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -218,11 +218,23 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = =3D { .macrotile_mode =3D true, }; =20 +static const struct qcom_ubwc_cfg_data glymur_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ + .highest_bank_bit =3D 16, + .macrotile_mode =3D true, +}; + static const struct of_device_id qcom_ubwc_configs[] __maybe_unused =3D { { .compatible =3D "qcom,apq8016", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,apq8026", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,apq8074", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,apq8096", .data =3D &msm8998_data }, + { .compatible =3D "qcom,glymur", .data =3D &glymur_data}, { .compatible =3D "qcom,msm8226", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8916", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8917", .data =3D &no_ubwc_data }, --=20 2.48.1