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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:13 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:03 -0700 Subject: [PATCH 01/12] dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-1-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=4225; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=PPtBIz8qEFvPp66GNhz5hdu3RpRfVBfYsLuidxR205M=; b=xr2MpTWnfc1z9/DYs0lmEaPgzO67s3OtRkMFlUDMRC0QKViHGXoLtClSlhp7erTCm29OL1zn3 8IE3NPo0bKqDB+lxtdSRdV7bNd5lvpqfA9voMhVZAzwas3ZA4x0zJFk X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: vrqk3Bxa0tMZkptu2RExKjCmxNrhruOr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX9vTqt8hzFmWy AxLCXwkDzHPMb8Nw5UuD6wjZILdRdU2txEJR42T6d9mumb9a9IjjrAUmCGTLvo1M6wwJdNloOVb qN22U8spyEwOuBoeCY4FOkBFpNWx/hZ9WHmyiA/TTsbIzWIfLCBmKbbQMT/jkZ4iOKB+YbPvfRC ICDDAs1qsiLS1GQ+pAX907CMV8TMyeWYQyQ3jPw9dGNLDCQbCKj48zzaMWDs8XaRr/RSbQ3uGt4 SMoh+kLSghm3lCFdlnkowoYh0mehHfV9auFT+g7/q+n6R3mHY6M0bhSyi51DsS1L1zqj1cDScTD 0BDICfl123XVpdweaxuC5EeeqettFCSMV4Wxdsgmfp53Tk3Honxj/HUpZ9zYxOVkoQxG1j0ThB+ C/ZpQL7dWrRTatr7wrtnzh7Hg2XDMw== X-Proofpoint-GUID: vrqk3Bxa0tMZkptu2RExKjCmxNrhruOr X-Authority-Analysis: v=2.4 cv=fL40HJae c=1 sm=1 tr=0 ts=6900627e cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=G4amIDmpmRGM4OpAro8A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 Add the following compatible strings to the bindings: - arm,coresight-cpu-funnel - arm,coresight-cpu-replicator - arm,coresight-cpu-tmc Each requires 'power-domains' when used. Signed-off-by: Yuanfang Zhang --- .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +++++++++++++++++-= ---- .../arm/arm,coresight-dynamic-replicator.yaml | 22 +++++++++++++++++-= --- .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +++++++++++++++++-= --- 3 files changed, 54 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-fu= nnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-fun= nel.yaml index b74db15e5f8af2226b817f6af5f533b1bfc74736..8f32d4e3bbb750f5a6262db0032= 318875739cf81 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.ya= ml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.ya= ml @@ -28,19 +28,32 @@ select: properties: compatible: contains: - const: arm,coresight-dynamic-funnel + enum: + - arm,coresight-dynamic-funnel + - arm,coresight-cpu-funnel required: - compatible =20 allOf: - $ref: /schemas/arm/primecell.yaml# =20 + - if: + properties: + compatible: + contains: + const: arm,coresight-cpu-funnel + then: + required: + - power-domains + properties: compatible: - items: - - const: arm,coresight-dynamic-funnel - - const: arm,primecell - + oneOf: + - items: + - const: arm,coresight-dynamic-funnel + - const: arm,primecell + - items: + - const: arm,coresight-cpu-funnel reg: maxItems: 1 =20 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-re= plicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic= -replicator.yaml index 17ea936b796fd42bb885e539201276a11e91028c..5ce30c4e9c415f487ee61dceaf5= b8ad12c78e671 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicato= r.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicato= r.yaml @@ -28,18 +28,32 @@ select: properties: compatible: contains: - const: arm,coresight-dynamic-replicator + enum: + - arm,coresight-dynamic-replicator + - arm,coresight-cpu-replicator required: - compatible =20 allOf: - $ref: /schemas/arm/primecell.yaml# =20 + - if: + properties: + compatible: + contains: + const: arm,coresight-cpu-replicator + then: + required: + - power-domains + properties: compatible: - items: - - const: arm,coresight-dynamic-replicator - - const: arm,primecell + oneOf: + - items: + - const: arm,coresight-dynamic-replicator + - const: arm,primecell + - items: + - const: arm,coresight-cpu-replicator =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b= /Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index 96dd5b5f771a39138df9adde0c9c9a6f5583d9da..d7c0b618fe98a3ca584041947fb= 5c0f80f1ade6e 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -29,18 +29,32 @@ select: properties: compatible: contains: - const: arm,coresight-tmc + enum: + - arm,coresight-tmc + - arm,coresight-cpu-tmc required: - compatible =20 allOf: - $ref: /schemas/arm/primecell.yaml# =20 + - if: + properties: + compatible: + contains: + const: arm,coresight-cpu-tmc + then: + required: + - power-domains + properties: compatible: - items: - - const: arm,coresight-tmc - - const: arm,primecell + oneOf: + - items: + - const: arm,coresight-tmc + - const: arm,primecell + - items: + - const: arm,coresight-cpu-tmc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Mon Feb 9 01:07:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6E9C29E110 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:14 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:04 -0700 Subject: [PATCH 02/12] coresight-funnel: Add support for CPU cluster funnel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-2-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=9298; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=0zJwLJ/CbFy+0o+vHzhKVbidP9iIvwNMjcD10+y0AC0=; b=MKYeSZfllSCAj//ygPXLgxpCdpi1CxWUmnZ5rZenRMYxbbKXHdYy2Pm2qzgHEvBd4YeaO4lre AT5ZZPRozVGCbZfkKhuPkacdE22frWOA+U+QXk8mMa7fpA8SlfitfSt X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Authority-Analysis: v=2.4 cv=XIY9iAhE c=1 sm=1 tr=0 ts=69006280 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=mZjCGalVderqEPr0BrkA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: NfeEUHFMoGNpLvl9xVdWEnXD9guhtdxu X-Proofpoint-ORIG-GUID: NfeEUHFMoGNpLvl9xVdWEnXD9guhtdxu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX6XfI/lK/+/2R xrkeXqEg21ZVSviPkklBeanZNoZpPliBoRm1ZrFm0X8PQrLDN9avrAWVqcrt06HyN1cMMeGDFvn PdkX/v/8+kWUEBCQFKy1+XCcsUD9CTe8siLMcex6FRNPeRbqfGr5+8zaEou8tcXoyE3xFTjnM9p hapzqBg8uoT4anMWYlNfehIqbgg20ySwh70qqkHwIrixuBSYDUTSyFq/h7ZCbvq5NTvBauhvbRS 5FjyCTEoPyZuKynwwj1GF15lpTESFy3NV6qMDdmeEG/gDXJsuJVaEusQBay+qJ7OfosrHTTF1H8 R+dFfDyWErGM91k4yHsGmXaNPDXCluZE7Gg91Qc3HhDdHUkY+44wDEDVS8WlzahrfkNTGNUXvWA Z7SIOyW2hXolAweKglxeTuNpkPBRtw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 The CPU cluster funnel is a type of CoreSight funnel that resides inside the CPU cluster's power domain. Unlike dynamic funnels, CPU funnels are coupled with CPU clusters and share their power management characteristics. When the CPU cluster enters low-power mode (LPM), the funnel's registers become inaccessible. Moreover, runtime PM operations alone cannot bring the CPU cluster out of LPM, making standard register access unreliable. This patch enhances the existing CoreSight funnel platform driver to support CPU cluster funnels by: - Add cpumask to funnel_drvdata to store CPU cluster's mask for CPU cluster funnel. - Retrieving the associated CPU cluster's cpumask from the power domain. - Using smp_call_function_single() to do clear self claim tag operation. - Refactoring funnel_enable function. For cluster funnels, use smp_call_function_single() to ensure register visibility. - Encapsulating coresight registration in funnel_add_coresight_dev(). - Reusing the existing platform driver infrastructure to minimize duplication and maintain compatibility with static funnel devices. This ensures funnel operations are safe and functional even when the CPU cluster is in low-power mode. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-funnel.c | 185 ++++++++++++++++++++-= ---- 1 file changed, 154 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 3b248e54471a38f501777fe162fea850d1c851b3..12c29eb98b2122a3ade4cbed9a0= d91c67ec777ed 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,7 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @csdev: component vitals needed by the framework. * @priority: port selection order. * @spinlock: serialize enable/disable operations. + * @cpumask: CPU mask representing the CPUs related to this funnel. */ struct funnel_drvdata { void __iomem *base; @@ -48,6 +50,13 @@ struct funnel_drvdata { struct coresight_device *csdev; unsigned long priority; raw_spinlock_t spinlock; + struct cpumask *cpumask; +}; + +struct funnel_smp_arg { + struct funnel_drvdata *drvdata; + int port; + int rc; }; =20 static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int po= rt) @@ -76,6 +85,33 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdat= a *drvdata, int port) return rc; } =20 +static void funnel_enable_hw_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D dynamic_funnel_enable_hw(arg->drvdata, arg->port); +} + +static int funnel_enable_hw(struct funnel_drvdata *drvdata, int port) +{ + int cpu, ret; + struct funnel_smp_arg arg =3D { 0 }; + + if (!drvdata->cpumask) + return dynamic_funnel_enable_hw(drvdata, port); + + arg.drvdata =3D drvdata; + arg.port =3D port; + + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + funnel_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -86,19 +122,24 @@ static int funnel_enable(struct coresight_device *csde= v, bool first_enable =3D false; =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (in->dest_refcnt =3D=3D 0) { - if (drvdata->base) - rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); - if (!rc) - first_enable =3D true; - } - if (!rc) + + if (in->dest_refcnt =3D=3D 0) + first_enable =3D true; + else in->dest_refcnt++; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", - in->dest_port); + if (first_enable) { + if (drvdata->base) + rc =3D funnel_enable_hw(drvdata, in->dest_port); + if (!rc) { + in->dest_refcnt++; + dev_dbg(&csdev->dev, "FUNNEL inport %d enabled\n", + in->dest_port); + } + } + return rc; } =20 @@ -188,15 +229,39 @@ static u32 get_funnel_ctrl_hw(struct funnel_drvdata *= drvdata) return functl; } =20 +static void get_funnel_ctrl_smp_call(void *info) +{ + struct funnel_smp_arg *arg =3D info; + + arg->rc =3D get_funnel_ctrl_hw(arg->drvdata); +} + static ssize_t funnel_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf) { u32 val; + int cpu, ret; struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct funnel_smp_arg arg =3D { 0 }; =20 pm_runtime_get_sync(dev->parent); - - val =3D get_funnel_ctrl_hw(drvdata); + if (!drvdata->cpumask) { + val =3D get_funnel_ctrl_hw(drvdata); + } else { + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + get_funnel_ctrl_smp_call, &arg, 1); + if (!ret) + break; + } + if (!ret) { + val =3D arg.rc; + } else { + pm_runtime_put(dev->parent); + return ret; + } + } =20 pm_runtime_put(dev->parent); =20 @@ -211,22 +276,68 @@ static struct attribute *coresight_funnel_attrs[] =3D= { }; ATTRIBUTE_GROUPS(coresight_funnel); =20 +static void funnel_clear_self_claim_tag(struct funnel_drvdata *drvdata) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void funnel_init_on_cpu(void *info) +{ + struct funnel_drvdata *drvdata =3D info; + + funnel_clear_self_claim_tag(drvdata); +} + +static int funnel_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc =3D { 0 }; + struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups =3D coresight_funnel_groups; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops =3D &funnel_cs_ops; + desc.pdata =3D dev->platform_data; + desc.dev =3D dev; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + return 0; +} + +static struct cpumask *funnel_get_cpumask(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int funnel_probe(struct device *dev, struct resource *res) { void __iomem *base; struct coresight_platform_data *pdata =3D NULL; struct funnel_drvdata *drvdata; - struct coresight_desc desc =3D { 0 }; - int ret; + int cpu, ret; =20 if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-funnel")) dev_warn_once(dev, "Uses OBSOLETE CoreSight funnel binding\n"); =20 - desc.name =3D coresight_alloc_device_name(&funnel_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -244,9 +355,6 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base =3D base; - desc.groups =3D coresight_funnel_groups; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } =20 dev_set_drvdata(dev, drvdata); @@ -258,23 +366,37 @@ static int funnel_probe(struct device *dev, struct re= source *res) dev->platform_data =3D pdata; =20 raw_spin_lock_init(&drvdata->spinlock); - desc.type =3D CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.ops =3D &funnel_cs_ops; - desc.pdata =3D pdata; - desc.dev =3D dev; - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); =20 - return 0; + if (is_of_node(dev_fwnode(dev)) && + of_device_is_compatible(dev->of_node, "arm,coresight-cpu-funnel")) { + drvdata->cpumask =3D funnel_get_cpumask(dev); + if (!drvdata->cpumask) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + funnel_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + + if (ret) + return 0; + } else if (res) { + funnel_clear_self_claim_tag(drvdata); + } + + return funnel_add_coresight_dev(dev); } =20 static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); =20 return 0; } @@ -341,6 +463,7 @@ static void funnel_platform_remove(struct platform_devi= ce *pdev) =20 static const struct of_device_id funnel_match[] =3D { {.compatible =3D "arm,coresight-static-funnel"}, + {.compatible =3D "arm,coresight-cpu-funnel"}, {} }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:15 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:05 -0700 Subject: [PATCH 03/12] coresight-funnel: Handle delay probe for CPU cluster funnel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-3-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=4160; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=TMPIo9r3GKbM4/XsJ/eT0bym94bCuMEsVFDyTCJ0GQE=; b=GugX3k+ihfKyUBUqtYh1X+pw96lNXr/5f0/RSTbu9cBkZhi71QQJKr8CSmV3S1zYjioYc7gJN u+Pcw81DtinB6++tLNNOcS6Ou3iIHF7jRRdAtVGIPMdw74WXe+L4j+y X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX2jeZDnDqB7HG HCMeEJMa1rkKkLt3iGp6vGc2TGwq5fiwKFaVtSLHhweKh1yNmqWhLEg/BPksWwnt3Ulyy4zjkEB Bw3S5XPoPFawStZaLdRDoPVxn7m5bJtH7nRSomI9/YkAPvS145mEjp/wjydmJhuqs6mjsprt6ST WowUnXrqyZGimxS4IxhbT53y2Y1Xq1SgbSCqviHjhuEbbcpAydDJRIJocD6EfJJTyExmxiROO46 gINf+NtnyOn18TGVIyB7TXIENowRFu9oLBi2ZCa2MGMvH7DtPceT5lodZ7S8sBaxdHTOuEb/feg E9jCmrBTMRacfBD1HUqyVKwD1o6oRvH63jEQKHwjE6qWqkbGXZ4htXF6ZYMHJ6ZwNxGFYK0KQK8 VgZ7/Ilcep+My0t7oXwpMgossv4Gsw== X-Proofpoint-ORIG-GUID: JpUCbDmlphN1hfEIEg5tmzeOyiAnASS- X-Authority-Analysis: v=2.4 cv=U9WfzOru c=1 sm=1 tr=0 ts=69006281 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=B8lwgTuz66jIMM7eRW8A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: JpUCbDmlphN1hfEIEg5tmzeOyiAnASS- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 Delay probe the cpu cluster funnel when all CPUs of this cluster are offline, re-probe the funnel when any CPU in the cluster comes online. Key changes: - Introduce a global list to track delayed funnels waiting for CPU online. - Add CPU hotplug callback to retry registration when the CPU comes up. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-funnel.c | 62 ++++++++++++++++++++++= +--- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 12c29eb98b2122a3ade4cbed9a0d91c67ec777ed..43b9287a865eb26ce021521e4a5= f193c48188bba 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -32,6 +32,9 @@ #define FUNNEL_ENSx_MASK 0xff =20 DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); +static LIST_HEAD(funnel_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 /** * struct funnel_drvdata - specifics associated to a funnel component @@ -42,6 +45,8 @@ DEFINE_CORESIGHT_DEVLIST(funnel_devs, "funnel"); * @priority: port selection order. * @spinlock: serialize enable/disable operations. * @cpumask: CPU mask representing the CPUs related to this funnel. + * @dev: pointer to the device associated with this funnel. + * @link: list node for adding this funnel to the delayed probe list. */ struct funnel_drvdata { void __iomem *base; @@ -51,6 +56,8 @@ struct funnel_drvdata { unsigned long priority; raw_spinlock_t spinlock; struct cpumask *cpumask; + struct device *dev; + struct list_head link; }; =20 struct funnel_smp_arg { @@ -372,7 +379,7 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) drvdata->cpumask =3D funnel_get_cpumask(dev); if (!drvdata->cpumask) return -EINVAL; - + drvdata->dev =3D dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->cpumask) { ret =3D smp_call_function_single(cpu, @@ -380,10 +387,15 @@ static int funnel_probe(struct device *dev, struct re= source *res) if (!ret) break; } - cpus_read_unlock(); =20 - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &funnel_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { funnel_clear_self_claim_tag(drvdata); } @@ -395,9 +407,12 @@ static int funnel_remove(struct device *dev) { struct funnel_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); - + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } return 0; } =20 @@ -535,8 +550,41 @@ static struct amba_driver dynamic_funnel_driver =3D { .id_table =3D dynamic_funnel_ids, }; =20 +static int funnel_online_cpu(unsigned int cpu) +{ + struct funnel_drvdata *drvdata, *tmp; + int ret; + + list_for_each_entry_safe(drvdata, tmp, &funnel_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->cpumask)) { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + funnel_clear_self_claim_tag(drvdata); + funnel_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + } + } + return 0; +} + static int __init funnel_init(void) { + int ret; + + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-funnel:online", + funnel_online_cpu, NULL); + + if (ret > 0) + hp_online =3D ret; + else + return ret; + return coresight_init_driver("funnel", &dynamic_funnel_driver, &funnel_dr= iver, THIS_MODULE); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:17 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:06 -0700 Subject: [PATCH 04/12] coresight-replicator: Add support for CPU cluster replicator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-4-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=10262; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=E0SDWUZhZFagugdNgdZOT1J748JhKJGJROZqnLwgGz0=; b=LxELFMmOq8/u9m/7p0savfS77WPdQkZIi18XPd+4dmDwx6eytPfzie538K4qbfI6xrK1ddBZM LFnxSO39YFzA/w+OzauTWT/TPv8SzKfLvYuCeIGjNNkauzeNAeAnfqp X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: gKKfXdLwUiS6nlhNc1fRiCocJX0DEnBn X-Proofpoint-GUID: gKKfXdLwUiS6nlhNc1fRiCocJX0DEnBn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX1gflgOlrf65q qsY/SbkvW6YU8RcwQVxS54QslM99W3DGuvkPNwFO7uDkXE95aXDCmTOyDckKVXnXvMoDlu3pqoI iag8i77H5irACQuwTn/Qjxcw6374esb01Y9j2Uw9va9V9oxKZhrrGQNwoqqYWqY58GCjjRuOz/b m13lRrDVpofdenG4LFILn4RwYxM8T/awxbEnbpt8MZVqIS5w+nIZuzgvYU6LYfEJEIkzJX3Q5uH ygjzlOchcOOdUxC+pvhesf4A0wMhSkTkhFSgjL+46y1sOUGEtOkwhUjGPiwYWRt32m7GyEUC9j4 JCcVUlF6fHYjZEya95Iz5gWd/TcnQQewqkMcrr5+B2hjRnlclQNH+A9HwlccNSeZNdWQ4EMFMn9 Wg/CTn6aFfX5YTVvzosqppQj53nKZg== X-Authority-Analysis: v=2.4 cv=R60O2NRX c=1 sm=1 tr=0 ts=69006283 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=WnTABDZRLdPeFdqLaHUA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 The CPU cluster replicator is a type of CoreSight replicator that resides inside the CPU cluster's power domain. Unlike system-wide replicators, CPU replicators are tightly coupled with CPU clusters and inherit their power management characteristics. When the CPU cluster enters low-power mode (LPM), the replicator registers become inaccessible. Moreover, runtime PM alone cannot bring the CPU cluster out of LPM, making standard register access unreliable. This patch enhances the existing CoreSight replicator platform driver to support CPU cluster replicators by: - Adding replicator_claim/disclaim_device_unlocked() to handle device claim/disclaim before CoreSight device registration. - Wrapping replicator_reset and clear_clear_tag in replicator_init_hw. For cluster replicators, use smp_call_function_single() to ensure register visibility. - Encapsulating csdev registration in replicator_add_coresight_dev(). - Refactoring replicator_enable function. For cluster replicators, use smp_call_function_single() to ensure register visibility. - Maintaining compatibility with existing static/dynamic replicators while minimizing duplication. This ensures replicator operations remain safe and functional even when the CPU cluster is in low-power states. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 202 +++++++++++++++++= ---- 1 file changed, 169 insertions(+), 33 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index e6472658235dc479cec91ac18f3737f76f8c74f0..c5a9c7a2adfa90ae22890ed730f= c008fe6901778 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,7 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @csdev: component vitals needed by the framework * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. + * @cpumask: CPU mask representing the CPUs related to this replicator. */ struct replicator_drvdata { void __iomem *base; @@ -43,18 +45,61 @@ struct replicator_drvdata { struct coresight_device *csdev; raw_spinlock_t spinlock; bool check_idfilter_val; + struct cpumask *cpumask; }; =20 -static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +struct replicator_smp_arg { + struct replicator_drvdata *drvdata; + int outport; + int rc; +}; + +static void replicator_clear_self_claim_tag(struct replicator_drvdata *drv= data) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static int replicator_claim_device_unlocked(struct replicator_drvdata *drv= data) +{ + struct coresight_device *csdev =3D drvdata->csdev; + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + u32 claim_tag; + + if (csdev) + return coresight_claim_device_unlocked(csdev); + + writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, drvdata->base + CORESIGHT_CLA= IMSET); + + claim_tag =3D readl_relaxed(drvdata->base + CORESIGHT_CLAIMCLR); + if (claim_tag !=3D CORESIGHT_CLAIM_SELF_HOSTED) { + coresight_clear_self_claim_tag_unlocked(&access); + return -EBUSY; + } + + return 0; +} + +static void replicator_disclaim_device_unlocked(struct replicator_drvdata = *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + if (csdev) + return coresight_disclaim_device_unlocked(csdev); =20 + coresight_clear_self_claim_tag_unlocked(&access); +} + +static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +{ CS_UNLOCK(drvdata->base); =20 - if (!coresight_claim_device_unlocked(csdev)) { + if (!replicator_claim_device_unlocked(drvdata)) { writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(csdev); + replicator_disclaim_device_unlocked(drvdata); } =20 CS_LOCK(drvdata->base); @@ -116,6 +161,34 @@ static int dynamic_replicator_enable(struct replicator= _drvdata *drvdata, return rc; } =20 +static void replicator_enable_hw_smp_call(void *info) +{ + struct replicator_smp_arg *arg =3D info; + + arg->rc =3D dynamic_replicator_enable(arg->drvdata, 0, arg->outport); +} + +static int replicator_enable_hw(struct replicator_drvdata *drvdata, + int inport, int outport) +{ + int cpu, ret; + struct replicator_smp_arg arg =3D { 0 }; + + if (!drvdata->cpumask) + return dynamic_replicator_enable(drvdata, 0, outport); + + arg.drvdata =3D drvdata; + arg.outport =3D outport; + + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, replicator_enable_hw_smp_call, &ar= g, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, struct coresight_connection *out) @@ -126,19 +199,24 @@ static int replicator_enable(struct coresight_device = *csdev, bool first_enable =3D false; =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); - if (out->src_refcnt =3D=3D 0) { - if (drvdata->base) - rc =3D dynamic_replicator_enable(drvdata, in->dest_port, - out->src_port); - if (!rc) - first_enable =3D true; - } - if (!rc) + + if (out->src_refcnt =3D=3D 0) + first_enable =3D true; + else out->src_refcnt++; raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 - if (first_enable) - dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + if (first_enable) { + if (drvdata->base) + rc =3D replicator_enable_hw(drvdata, in->dest_port, + out->src_port); + if (!rc) { + out->src_refcnt++; + dev_dbg(&csdev->dev, "REPLICATOR enabled\n"); + return rc; + } + } + return rc; } =20 @@ -217,23 +295,69 @@ static const struct attribute_group *replicator_group= s[] =3D { NULL, }; =20 +static int replicator_add_coresight_dev(struct device *dev) +{ + struct coresight_desc desc =3D { 0 }; + struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev); + + if (drvdata->base) { + desc.groups =3D replicator_groups; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + } + + desc.name =3D coresight_alloc_device_name(&replicator_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; + desc.ops =3D &replicator_cs_ops; + desc.pdata =3D dev->platform_data; + desc.dev =3D dev; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + return 0; +} + +static void replicator_init_hw(struct replicator_drvdata *drvdata) +{ + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); +} + +static void replicator_init_on_cpu(void *info) +{ + struct replicator_drvdata *drvdata =3D info; + + replicator_init_hw(drvdata); +} + +static struct cpumask *replicator_get_cpumask(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + static int replicator_probe(struct device *dev, struct resource *res) { struct coresight_platform_data *pdata =3D NULL; struct replicator_drvdata *drvdata; - struct coresight_desc desc =3D { 0 }; void __iomem *base; - int ret; + int cpu, ret; =20 if (is_of_node(dev_fwnode(dev)) && of_device_is_compatible(dev->of_node, "arm,coresight-replicator")) dev_warn_once(dev, "Uses OBSOLETE CoreSight replicator binding\n"); =20 - desc.name =3D coresight_alloc_device_name(&replicator_devs, dev); - if (!desc.name) - return -ENOMEM; - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; @@ -251,9 +375,6 @@ static int replicator_probe(struct device *dev, struct = resource *res) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base =3D base; - desc.groups =3D replicator_groups; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - coresight_clear_self_claim_tag(&desc.access); } =20 if (fwnode_property_present(dev_fwnode(dev), @@ -268,25 +389,39 @@ static int replicator_probe(struct device *dev, struc= t resource *res) dev->platform_data =3D pdata; =20 raw_spin_lock_init(&drvdata->spinlock); - desc.type =3D CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; - desc.ops =3D &replicator_cs_ops; - desc.pdata =3D dev->platform_data; - desc.dev =3D dev; =20 - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) - return PTR_ERR(drvdata->csdev); + if (is_of_node(dev_fwnode(dev)) && + of_device_is_compatible(dev->of_node, "arm,coresight-cpu-replicator")= ) { + drvdata->cpumask =3D replicator_get_cpumask(dev); + if (!drvdata->cpumask) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + replicator_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); =20 - replicator_reset(drvdata); - return 0; + if (ret) + return 0; + } else if (res) { + replicator_init_hw(drvdata); + } + + ret =3D replicator_add_coresight_dev(dev); + + return ret; } =20 static int replicator_remove(struct device *dev) { struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); return 0; } =20 @@ -354,6 +489,7 @@ static const struct dev_pm_ops replicator_dev_pm_ops = =3D { static const struct of_device_id replicator_match[] =3D { {.compatible =3D "arm,coresight-replicator"}, {.compatible =3D "arm,coresight-static-replicator"}, + {.compatible =3D "arm,coresight-cpu-replicator"}, {} }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:18 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:07 -0700 Subject: [PATCH 05/12] coresight-replicator: Handle delayed probe for CPU cluster replicator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-5-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=4448; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=qIU3aNCwc/5hLOTjRkewyXRoR9HF6h6FxhePov1nhio=; b=WfK40WV2y8LNmku++Vn6N1Zf/2VTmZeY7+ENZ6akJVkIVwtz+hRg9mjsmdR993NMUEjTIetb/ hI7bYBE9VN+CY2JUPDMelBWe28EKfG4FMUBKyANLLsrBS08X7hezlyf X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX8kPMi+U5ZRB1 p4EGZsZBo6rSHolrzrF6Ay8YtfqiMqfDUNRvFb9E1Ojyc+jRULXhG4Yn/hTdMuk1aFD2zLhKfGV 7FZxKxcz7QJoW97EZ62l/Ko+x/3/P3NF4+wTFx13rIlJYmZNxvNjSEriHnEI/OoLzAt2apoMGkL 9yIzO/rXzlYgEOjtf1l+5ehoWMelywWaMsZ7bSjpr/ZGSjU6CRbFAJO1galCfUZiUQ4ZW9j0Lcl QhKbIaC6Ad/EgVtOrDRRzqpWjunXS+PHCndSfXlF4gn2uTPFYWK2D7rig23uClth9vDjK951zKs IPEeWMgPe7NfmTw7Y/MSWkC1qLeR+bkqHN8zRom632DzIZnfVmSZVn7Yj+BVYjwOMk7ZBzHXmoH hZDpEzulmSqtIVRJMdPYTIyLFg2Qvg== X-Proofpoint-ORIG-GUID: y_RavLrOyRQ4wYOanvS7RjKZzx7-P-XG X-Authority-Analysis: v=2.4 cv=U9WfzOru c=1 sm=1 tr=0 ts=69006286 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=GdHxG0adR5Xe-XRRLWYA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: y_RavLrOyRQ4wYOanvS7RjKZzx7-P-XG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 Delay probe the CPU cluster replicator when all CPUs of the cluster are offline, and re-probe the replicator when any CPU in the cluster comes online. Key changes: - Maintain a global list to track delayed replicators waiting for CPU online. - Add a CPU hotplug callback to retry registration on CPU online events. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 65 ++++++++++++++++++= ++-- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index c5a9c7a2adfa90ae22890ed730fc008fe6901778..1dfe11940cd6001db3cf17249b0= 493027b65e19c 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -26,6 +26,9 @@ #define REPLICATOR_IDFILTER1 0x004 =20 DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); +static LIST_HEAD(replicator_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 /** * struct replicator_drvdata - specifics associated to a replicator compon= ent @@ -37,6 +40,8 @@ DEFINE_CORESIGHT_DEVLIST(replicator_devs, "replicator"); * @spinlock: serialize enable/disable operations. * @check_idfilter_val: check if the context is lost upon clock removal. * @cpumask: CPU mask representing the CPUs related to this replicator. + * @dev: pointer to the device associated with this replicator. + * @link: link to the delay_probed list. */ struct replicator_drvdata { void __iomem *base; @@ -46,6 +51,8 @@ struct replicator_drvdata { raw_spinlock_t spinlock; bool check_idfilter_val; struct cpumask *cpumask; + struct device *dev; + struct list_head link; }; =20 struct replicator_smp_arg { @@ -395,7 +402,7 @@ static int replicator_probe(struct device *dev, struct = resource *res) drvdata->cpumask =3D replicator_get_cpumask(dev); if (!drvdata->cpumask) return -EINVAL; - + drvdata->dev =3D dev; cpus_read_lock(); for_each_cpu(cpu, drvdata->cpumask) { ret =3D smp_call_function_single(cpu, @@ -403,10 +410,15 @@ static int replicator_probe(struct device *dev, struc= t resource *res) if (!ret) break; } - cpus_read_unlock(); =20 - if (ret) + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &replicator_delay_probe); + cpus_read_unlock(); return 0; + } + + cpus_read_unlock(); } else if (res) { replicator_init_hw(drvdata); } @@ -420,8 +432,13 @@ static int replicator_remove(struct device *dev) { struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } + return 0; } =20 @@ -554,8 +571,44 @@ static struct amba_driver dynamic_replicator_driver = =3D { .id_table =3D dynamic_replicator_ids, }; =20 +static int replicator_online_cpu(unsigned int cpu) +{ + struct replicator_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &replicator_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->cpumask)) { + list_del(&drvdata->link); + spin_unlock(&delay_lock); + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + replicator_clear_self_claim_tag(drvdata); + replicator_reset(drvdata); + replicator_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init replicator_init(void) { + int ret; + + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-replicator:online", + replicator_online_cpu, NULL); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:22 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:08 -0700 Subject: [PATCH 06/12] coresight-replicator: Update mgmt_attrs for CPU cluster replicator compatibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-6-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=2874; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=wrtq8428nZWzeJ2YM87p20K7H7FcxcHonAVQhsF4btU=; b=n1XFP/EYxn0Wrkm/FhLrkJPZ1Y/amwYC2N3lVShkOdDVseUu8Y5JQriQZy2P5STM6yEHYntwF /iWXOi7L3MICOcvUcKbift/V4Hvz+PTq/q04qbju4hzYZurophy3iDJ X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: TENPR-3pt1rf4PDgaj8do6Gc1LkdT1t2 X-Proofpoint-GUID: TENPR-3pt1rf4PDgaj8do6Gc1LkdT1t2 X-Authority-Analysis: v=2.4 cv=QuFTHFyd c=1 sm=1 tr=0 ts=69006287 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ViDxg2sRvTZTAOTQKJ0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfX75EA8yAVmqJw pSPijXR04hTF2aBs8onrwMdKuFpFp9NZQfIuNHyVF6LsTS0ysVd+tc4TsfdV3Ne5XmGr5z/bbd+ bJJfu8yOJjRdgdrzXfF78fL9OAWxN1gmIwUvLCKCT0xEeNo4yi122YUaaiC2BFc8BT//mwxrFWP oQlW6uxuOzjlpy6Zdk1L0r7xe13m5/4dRUu2732b++9OcD9aU4xnh6u55sOgzlL9j1OtTrmTfRL Ii0NLuewspOqNdNyRyRBevbgigoLINdRbgPnMPB0zH6ZOPkFwL3w/+b/ReVwOiFYvrJlQ0gEahO KQruECsJcWoKvhhhXWJSHs6PG84zCkQDdiR2ieSUN+U6WK5vjoTLFThiA6dUUaTq3qn386/j5R0 Yigk6QS2h0qXzds6+9TrFFVJw0U7VQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 This patch refactors the sysfs interfaces to ensure compatibility with CPU cluster replicators. For CPU cluster replicators, register reads are performed via smp_call_function_single(). Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-replicator.c | 61 ++++++++++++++++++= +++- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index 1dfe11940cd6001db3cf17249b0493027b65e19c..22c9bc71817d238c2d4ddffbb42= 678bf792b29af 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -58,6 +58,7 @@ struct replicator_drvdata { struct replicator_smp_arg { struct replicator_drvdata *drvdata; int outport; + u32 offset; int rc; }; =20 @@ -286,9 +287,65 @@ static const struct coresight_ops replicator_cs_ops = =3D { .link_ops =3D &replicator_link_ops, }; =20 +static void replicator_read_register_smp_call(void *info) +{ + struct replicator_smp_arg *arg =3D info; + + arg->rc =3D readl_relaxed(arg->drvdata->base + arg->offset); +} + +static ssize_t coresight_replicator_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct replicator_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr =3D container_of(attr, struct cs_off_att= ribute, attr); + unsigned long flags; + struct replicator_smp_arg arg =3D { 0 }; + u32 val; + int ret, cpu; + + pm_runtime_get_sync(dev->parent); + + if (!drvdata->cpumask) { + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + val =3D readl_relaxed(drvdata->base + cs_attr->off); + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + } else { + arg.drvdata =3D drvdata; + arg.offset =3D cs_attr->off; + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + replicator_read_register_smp_call, + &arg, 1); + if (!ret) + break; + } + if (!ret) { + val =3D arg.rc; + } else { + pm_runtime_put_sync(dev->parent); + return ret; + } + } + + pm_runtime_put_sync(dev->parent); + + return sysfs_emit(buf, "0x%x\n", val); +} + +#define coresight_replicator_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_replicator_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) + static struct attribute *replicator_mgmt_attrs[] =3D { - coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0), - coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1), + coresight_replicator_reg32(idfilter0, REPLICATOR_IDFILTER0), + coresight_replicator_reg32(idfilter1, REPLICATOR_IDFILTER1), NULL, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:23 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:09 -0700 Subject: [PATCH 07/12] coresight-tmc: Add support for CPU cluster ETF and refactor probe flow Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-7-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=10579; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=2oaRzZpkpBcaDL+LXhi7LqTRCwRt9ypQSujziItZ0/o=; b=VbRLKaV4ZZf4K+mfX6223CCeK+C08cMMtg5ExiBoeA7d7WYQ+SrZBEsI6X/0m+K1BD90HjSrP YrqnvJpPDTjCu/4Ah1MCMgwVDHRCo6qdyWZXPDGgsCIUD3y2jzNnZv/ X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: ArB9J_VMjLjN82Pkk8L6Dng-d87D2LC1 X-Proofpoint-GUID: ArB9J_VMjLjN82Pkk8L6Dng-d87D2LC1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfXxGHj588ZF2BK mJyLh+mYL37IZ2Uk8dPJYkXIJyJ73D/mUJVeNTzKvaLOoRbuywodHFPfIjtmOffYgrQEtgbwmmw dPLpOGJHQ2PO+9/7j9zOC2r6/9vNeMcZN1grP9Yx1WKX14LJYTlP3GOpBUfePq3/frYNY8EWh4f E7ZTjqM6g9C9MbfgCc54bbVx8Jfo00IV8lrBfXvN32yWp78+l3rBWJ6lRZCUz1ggIkzX46JADQk giJ9nIfD1CM3vJobzfve3v9q1wIdeoa7GCxn5gcOUT2uVYwFfV9IltLnLmngebCD+S0Rg2ZX1w8 m0L3FKjWgrMbvIRBjGkArAJsrCasGKkWybbDPfyVgeeAr8Q4y8cIHnq4yGPtljtOL8Gg0TSAuBI qwALC2GJoKYkSKMb2AzuGH+5jfUOsw== X-Authority-Analysis: v=2.4 cv=R60O2NRX c=1 sm=1 tr=0 ts=6900628a cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ko4GrPIkLBdci27uQwEA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 spamscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 The CPU cluster ETF is a type of Coresight ETF that resides inside the CPU cluster's power domain. Unlike system-level ETFs, these devices share the CPU cluster's power management behavior: when the cluster enters low-power mode, ETF registers become inaccessible. Runtime PM alone cannot bring the cluster out of LPM, making standard register access unreliable. This patch adds support for CPU cluster ETF and restructures the probe sequence to handle such cases safely: - Wrap hardware access in tmc_init_hw_config(). For cluster TMCs, use smp_call_function_single() to ensure register visibility. - Encapsulate CoreSight device registration and misc_register setup in tmc_add_coresight_dev(). This ensures TMC initialization and runtime operations remain safe even when the CPU cluster is in low-power states, while maintaining compatibility with existing system-level TMCs. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 204 +++++++++++++++----= ---- drivers/hwtracing/coresight/coresight-tmc.h | 6 + 2 files changed, 141 insertions(+), 69 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 36599c431be6203e871fdcb8de569cc6701c52bb..d00f23f9a479ee9d4bdb4e051ed= 895d266bcc116 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -769,56 +770,14 @@ static void register_crash_dev_interface(struct tmc_d= rvdata *drvdata, "Valid crash tracedata found\n"); } =20 -static int __tmc_probe(struct device *dev, struct resource *res) +static int tmc_add_coresight_dev(struct device *dev) { - int ret =3D 0; - u32 devid; - void __iomem *base; - struct coresight_platform_data *pdata =3D NULL; - struct tmc_drvdata *drvdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev); struct coresight_desc desc =3D { 0 }; struct coresight_dev_list *dev_list =3D NULL; + int ret =3D 0; =20 - drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - dev_set_drvdata(dev, drvdata); - - ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); - if (ret) - return ret; - - ret =3D -ENOMEM; - - /* Validity for the resource is already checked by the AMBA core */ - base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret =3D PTR_ERR(base); - goto out; - } - - drvdata->base =3D base; - desc.access =3D CSDEV_ACCESS_IOMEM(base); - - raw_spin_lock_init(&drvdata->spinlock); - - devid =3D readl_relaxed(drvdata->base + CORESIGHT_DEVID); - drvdata->config_type =3D BMVAL(devid, 6, 7); - drvdata->memwidth =3D tmc_get_memwidth(devid); - /* This device is not associated with a session */ - drvdata->pid =3D -1; - drvdata->etr_mode =3D ETR_MODE_AUTO; - - if (drvdata->config_type =3D=3D TMC_CONFIG_TYPE_ETR) { - drvdata->size =3D tmc_etr_get_default_buffer_size(dev); - drvdata->max_burst_size =3D tmc_etr_get_max_burst_size(dev); - } else { - drvdata->size =3D readl_relaxed(drvdata->base + TMC_RSZ) * 4; - } - - tmc_get_reserved_region(dev); - + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); desc.dev =3D dev; =20 switch (drvdata->config_type) { @@ -834,9 +793,9 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.type =3D CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops =3D &tmc_etr_cs_ops; - ret =3D tmc_etr_setup_caps(dev, devid, &desc.access); + ret =3D tmc_etr_setup_caps(dev, drvdata->devid, &desc.access); if (ret) - goto out; + return ret; idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D &etr_devs; @@ -851,44 +810,142 @@ static int __tmc_probe(struct device *dev, struct re= source *res) break; default: pr_err("%s: Unsupported TMC config\n", desc.name); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 desc.name =3D coresight_alloc_device_name(dev_list, dev); - if (!desc.name) { - ret =3D -ENOMEM; + if (!desc.name) + return -ENOMEM; + + drvdata->desc_name =3D desc.name; + + desc.pdata =3D dev->platform_data; + + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name =3D desc.name; + drvdata->miscdev.minor =3D MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops =3D &tmc_fops; + ret =3D misc_register(&drvdata->miscdev); + if (ret) + coresight_unregister(drvdata->csdev); + + return ret; +} + +static void tmc_clear_self_claim_tag(struct tmc_drvdata *drvdata) +{ + struct csdev_access access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + + coresight_clear_self_claim_tag(&access); +} + +static void tmc_init_hw_config(struct tmc_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl_relaxed(drvdata->base + CORESIGHT_DEVID); + drvdata->config_type =3D BMVAL(devid, 6, 7); + drvdata->memwidth =3D tmc_get_memwidth(devid); + drvdata->devid =3D devid; + drvdata->size =3D readl_relaxed(drvdata->base + TMC_RSZ) * 4; + tmc_clear_self_claim_tag(drvdata); +} + +static void tmc_init_on_cpu(void *info) +{ + struct tmc_drvdata *drvdata =3D info; + + tmc_init_hw_config(drvdata); +} + +static struct cpumask *tmc_get_cpumask(struct device *dev) +{ + struct generic_pm_domain *pd; + + pd =3D pd_to_genpd(dev->pm_domain); + if (pd) + return pd->cpus; + + return NULL; +} + +static int __tmc_probe(struct device *dev, struct resource *res) +{ + int cpu, ret =3D 0; + void __iomem *base; + struct coresight_platform_data *pdata =3D NULL; + struct tmc_drvdata *drvdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + dev_set_drvdata(dev, drvdata); + + ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk); + if (ret) + return ret; + + ret =3D -ENOMEM; + + /* Validity for the resource is already checked by the AMBA core */ + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret =3D PTR_ERR(base); goto out; } =20 + drvdata->base =3D base; + + raw_spin_lock_init(&drvdata->spinlock); + /* This device is not associated with a session */ + drvdata->pid =3D -1; + drvdata->etr_mode =3D ETR_MODE_AUTO; + tmc_get_reserved_region(dev); + pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) { ret =3D PTR_ERR(pdata); goto out; } dev->platform_data =3D pdata; - desc.pdata =3D pdata; =20 - coresight_clear_self_claim_tag(&desc.access); - drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) { - ret =3D PTR_ERR(drvdata->csdev); - goto out; + if (is_of_node(dev_fwnode(dev)) && + of_device_is_compatible(dev->of_node, "arm,coresight-cpu-tmc")) { + drvdata->cpumask =3D tmc_get_cpumask(dev); + if (!drvdata->cpumask) + return -EINVAL; + + cpus_read_lock(); + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + tmc_init_on_cpu, drvdata, 1); + if (!ret) + break; + } + cpus_read_unlock(); + if (ret) { + ret =3D 0; + goto out; + } + } else { + tmc_init_hw_config(drvdata); } =20 - drvdata->miscdev.name =3D desc.name; - drvdata->miscdev.minor =3D MISC_DYNAMIC_MINOR; - drvdata->miscdev.fops =3D &tmc_fops; - ret =3D misc_register(&drvdata->miscdev); - if (ret) { - coresight_unregister(drvdata->csdev); - goto out; + if (drvdata->config_type =3D=3D TMC_CONFIG_TYPE_ETR) { + drvdata->size =3D tmc_etr_get_default_buffer_size(dev); + drvdata->max_burst_size =3D tmc_etr_get_max_burst_size(dev); } =20 + ret =3D tmc_add_coresight_dev(dev); + out: if (is_tmc_crashdata_valid(drvdata) && !tmc_prepare_crashdata(drvdata)) - register_crash_dev_interface(drvdata, desc.name); + register_crash_dev_interface(drvdata, drvdata->desc_name); return ret; } =20 @@ -934,10 +991,12 @@ static void __tmc_remove(struct device *dev) * etb fops in this case, device is there until last file * handler to this device is closed. */ - misc_deregister(&drvdata->miscdev); + if (!drvdata->cpumask) + misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - coresight_unregister(drvdata->csdev); + if (drvdata->csdev) + coresight_unregister(drvdata->csdev); } =20 static void tmc_remove(struct amba_device *adev) @@ -992,7 +1051,6 @@ static void tmc_platform_remove(struct platform_device= *pdev) =20 if (WARN_ON(!drvdata)) return; - __tmc_remove(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1029,6 +1087,13 @@ static const struct dev_pm_ops tmc_dev_pm_ops =3D { SET_RUNTIME_PM_OPS(tmc_runtime_suspend, tmc_runtime_resume, NULL) }; =20 +static const struct of_device_id tmc_match[] =3D { + {.compatible =3D "arm,coresight-cpu-tmc"}, + {} +}; + +MODULE_DEVICE_TABLE(of, tmc_match); + #ifdef CONFIG_ACPI static const struct acpi_device_id tmc_acpi_ids[] =3D { {"ARMHC501", 0, 0, 0}, /* ARM CoreSight ETR */ @@ -1043,6 +1108,7 @@ static struct platform_driver tmc_platform_driver =3D= { .remove =3D tmc_platform_remove, .driver =3D { .name =3D "coresight-tmc-platform", + .of_match_table =3D tmc_match, .acpi_match_table =3D ACPI_PTR(tmc_acpi_ids), .suppress_bind_attrs =3D true, .pm =3D &tmc_dev_pm_ops, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index cbb4ba43915855a8acbb9205167e87185c9a8c6c..f5c76ca2dc9733daa020b79b1dc= fc495045a2618 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -243,6 +243,9 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @cpumask: CPU mask representing the CPUs related to this TMC. + * @devid: TMC variant ID inferred from the device configuration register. + * @desc_name: Name to be used while creating crash interface. */ struct tmc_drvdata { struct clk *atclk; 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To ensure safe ETF enable sequences on such devices, split tmc_etf/etb_enable_hw function into two variants: - tmc_etf/etb_enable_hw_local: replaces the old tmc_etf/etb_enable_hw for normal ETF cases - tmc_etf/etb_enable_hw_smp_call: executes CPU cluster ETF enable on a CPU within the cluster via smp_call_function_single Also add a check to ensure the current CPU belongs to the cluster before calling tmc_etb_enable_hw_local for CPU cluster ETF. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 86 +++++++++++++++++++++= +--- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 0f45ab5e5249933ce7059dfee7fe7376ab33ed2d..b8a1c10d4b4c49144449b33f267= 10cf11713b338 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -47,7 +47,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdat= a) return rc; } =20 -static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etb_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -60,6 +60,36 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) return rc; } =20 +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + int rc; +}; + +static void tmc_etb_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etb_enable_hw_local(arg->drvdata); +} + +static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->cpumask) + return tmc_etb_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + tmc_etb_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { char *bufp; @@ -130,7 +160,7 @@ static int __tmc_etf_enable_hw(struct tmc_drvdata *drvd= ata) return rc; } =20 -static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int tmc_etf_enable_hw_local(struct tmc_drvdata *drvdata) { int rc =3D coresight_claim_device(drvdata->csdev); =20 @@ -143,6 +173,32 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvda= ta) return rc; } =20 +static void tmc_etf_enable_hw_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D tmc_etf_enable_hw_local(arg->drvdata); +} + +static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +{ + int cpu, ret; + struct tmc_smp_arg arg =3D { 0 }; + + if (!drvdata->cpumask) + return tmc_etf_enable_hw_local(drvdata); + + arg.drvdata =3D drvdata; + + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + tmc_etf_enable_hw_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + return ret; +} + static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; @@ -228,7 +284,11 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_= device *csdev) used =3D true; drvdata->buf =3D buf; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + ret =3D tmc_etb_enable_hw(drvdata); + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); csdev->refcnt++; @@ -290,7 +350,10 @@ static int tmc_enable_etf_sink_perf(struct coresight_d= evice *csdev, void *data) break; } =20 - ret =3D tmc_etb_enable_hw(drvdata); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:26 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:11 -0700 Subject: [PATCH 09/12] coresight-tmc: Update tmc_mgmt_attrs for CPU cluster TMC compatibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-9-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=4826; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=4+85nU8xoAz0ySe0tncInYyQsGyUu39pardgvBh8hvk=; b=wxyUwqrzqepTBHvSNDoVG1J5TCtBtVofgulY7h8uIIFRx6LVPZ2z4HU6ZzJRzpZURhWASLs00 86cQ1kU7FdkDaS9taTrSS7RKGeoMl1joGb6OwLlagIPIOgezuc2XZQ/ X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfXyNvVlCYGDa8F z5ppkX2ZrFvqyD7Q7hD/4JRZzP7SXD2z7bX/NS9kGXfbd2eqTeCi68eRZfqBX1nfANl01I9tOpy CB7dnwRhUSQm5MkVk7UBZH/Oq2+B1fkWosmsSGYYBU+E/cO7FzXQYEtuCRIygMhN4mks7ZlPi1u yKPVRyMb6KKIZPZ/wjkQ+y4annWCaSJu9JtDN84FBeoMcNf8f5jSg7SqQ3R9qRx2jlmdz/M9ylP cjhpNjCBYJZI5MwXkzsEEiZ6enOejO6nNSu53Y+8mrAyiJLztQUgi6Gfp58bUnx6L8LuZCPgC58 ajFwaBI1hnUk/MiLFRlub5h0u4iSaPxHTUeD7MRwfCOMQhyJobq47ZnmoD9ayIS4S+hcJZu1+Q0 Ec7noON6osrpngL915FLIz8qVwZBPA== X-Proofpoint-ORIG-GUID: WEVq2g6I-5lCvrOJ3j1-jaVVk3bCXqoY X-Proofpoint-GUID: WEVq2g6I-5lCvrOJ3j1-jaVVk3bCXqoY X-Authority-Analysis: v=2.4 cv=c9CmgB9l c=1 sm=1 tr=0 ts=6900628c cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=C6fT43XAjLT6VXuj5BkA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 priorityscore=1501 adultscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 This patch refactors the sysfs interfaces to ensure compatibility with CPU cluster TMC. When operating on a CPU cluster TMC, register reads are performed via `smp_call_function_single()`. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 137 +++++++++++++++++++= +--- 1 file changed, 123 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index d00f23f9a479ee9d4bdb4e051ed895d266bcc116..685a64d8ba1b5df4cff91694eee= 45c6d6a147bc1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -458,21 +458,130 @@ static enum tmc_mem_intf_width tmc_get_memwidth(u32 = devid) return memwidth; } =20 +struct tmc_smp_arg { + struct tmc_drvdata *drvdata; + u32 offset; + int rc; +}; + +static void tmc_read_reg_smp_call(void *info) +{ + struct tmc_smp_arg *arg =3D info; + + arg->rc =3D readl_relaxed(arg->drvdata->base + arg->offset); +} + +static u32 cpu_tmc_read_reg(struct tmc_drvdata *drvdata, u32 offset) +{ + struct tmc_smp_arg arg =3D { + .drvdata =3D drvdata, + .offset =3D offset, + }; + int cpu, ret =3D 0; + + for_each_cpu(cpu, drvdata->cpumask) { + ret =3D smp_call_function_single(cpu, + tmc_read_reg_smp_call, &arg, 1); + if (!ret) + return arg.rc; + } + + return ret; +} + +static ssize_t coresight_tmc_reg32_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_off_attribute *cs_attr =3D container_of(attr, struct cs_off_att= ribute, attr); + int ret; + u32 val; + + ret =3D pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + + if (!drvdata->cpumask) + val =3D readl_relaxed(drvdata->base + cs_attr->off); + else + val =3D cpu_tmc_read_reg(drvdata, cs_attr->off); + + pm_runtime_put(dev->parent); + + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%x\n", val); +} + +static ssize_t coresight_tmc_reg64_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + struct cs_pair_attribute *cs_attr =3D container_of(attr, struct cs_pair_a= ttribute, attr); + int ret; + u64 val; + + ret =3D pm_runtime_resume_and_get(dev->parent); + if (ret < 0) + return ret; + if (!drvdata->cpumask) { + val =3D readl_relaxed(drvdata->base + cs_attr->lo_off) | + ((u64)readl_relaxed(drvdata->base + cs_attr->hi_off) << 32); + } else { + ret =3D cpu_tmc_read_reg(drvdata, cs_attr->lo_off); + + if (ret < 0) + goto out; + + val =3D ret; + + ret =3D cpu_tmc_read_reg(drvdata, cs_attr->hi_off); + if (ret < 0) + goto out; + + val |=3D ((u64)ret << 32); + } + +out: + pm_runtime_put_sync(dev->parent); + if (ret < 0) + return ret; + else + return sysfs_emit(buf, "0x%llx\n", val); +} + +#define coresight_tmc_reg32(name, offset) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg32_show, NULL), \ + offset \ + } \ + })[0].attr.attr) +#define coresight_tmc_reg64(name, lo_off, hi_off) \ + (&((struct cs_pair_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_tmc_reg64_show, NULL), \ + lo_off, hi_off \ + } \ + })[0].attr.attr) static struct attribute *coresight_tmc_mgmt_attrs[] =3D { - coresight_simple_reg32(rsz, TMC_RSZ), - coresight_simple_reg32(sts, TMC_STS), - coresight_simple_reg64(rrp, TMC_RRP, TMC_RRPHI), - coresight_simple_reg64(rwp, TMC_RWP, TMC_RWPHI), - coresight_simple_reg32(trg, TMC_TRG), - coresight_simple_reg32(ctl, TMC_CTL), - coresight_simple_reg32(ffsr, TMC_FFSR), - coresight_simple_reg32(ffcr, TMC_FFCR), - coresight_simple_reg32(mode, TMC_MODE), - coresight_simple_reg32(pscr, TMC_PSCR), - coresight_simple_reg32(devid, CORESIGHT_DEVID), - coresight_simple_reg64(dba, TMC_DBALO, TMC_DBAHI), - coresight_simple_reg32(axictl, TMC_AXICTL), - coresight_simple_reg32(authstatus, TMC_AUTHSTATUS), + coresight_tmc_reg32(rsz, TMC_RSZ), + coresight_tmc_reg32(sts, TMC_STS), + coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI), + coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI), + coresight_tmc_reg32(trg, TMC_TRG), + coresight_tmc_reg32(ctl, TMC_CTL), + coresight_tmc_reg32(ffsr, TMC_FFSR), + coresight_tmc_reg32(ffcr, TMC_FFCR), + coresight_tmc_reg32(mode, TMC_MODE), + coresight_tmc_reg32(pscr, TMC_PSCR), + coresight_tmc_reg32(devid, CORESIGHT_DEVID), + coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI), + coresight_tmc_reg32(axictl, TMC_AXICTL), + coresight_tmc_reg32(authstatus, TMC_AUTHSTATUS), NULL, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:28 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:12 -0700 Subject: [PATCH 10/12] coresight-tmc: Handle delayed probe for CPU cluster TMC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-10-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=4560; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=R098UnmnSwcFWaM8MpFroDz5io13u7mQq3HuEtEMZPQ=; b=MK+gKR6IN2X24uvIWsY1xMXMxIZVE842wcZNNGnkMgKDPzom+ZSefRVoWMjEy40EWHpewtHLU g/QLL+O0JUHDC47/muwhdHuzpoFCd9dPIxzXJTfb33k1SkspAMh9EPN X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfXwaxvupVbaYby 9ir0QvdGkEqU5Jwy/Hf+z4HaA2UrJNwJmDS7kUpUVz+TAt3dDxXFJl7XScHKtybhGBFqpsn5x2P cqQOcYV0VP8Vm/v4QnVxXJ/W+I0yUk2O0kAb/yaRIeW414KyTRK6dhdzPhOPMOwG6u7UNWiQXK5 ksuSqxQPzqDxyAh2naaM9SwX1EvCxf0IPIACc5eInrdgrbGMAYfzRCc57hLC/61K6SsZ1hjs0vP vz2bj1cM6F0dwzXEGaiokBKcxaD7KzLfJbfSgNcOdxrZvYy8HIbRBp8dK9x4TmrpbU5JdbUjVH8 SwQd6OQiUCsFchjNjfd0nVAO+y0JYwp38NQtNvg6iJ8Z/prAdGHWdeF5FcNJtc+E6FNYOCTX6xP undiREfdcpkDBlgLdjGAVU4u9G4lVA== X-Proofpoint-ORIG-GUID: Mf_dAylcwNjZczNQqWBa6TvgxjUku5Ws X-Authority-Analysis: v=2.4 cv=U9WfzOru c=1 sm=1 tr=0 ts=6900628e cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fD5cxDGOUVrWaoTO3WMA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: Mf_dAylcwNjZczNQqWBa6TvgxjUku5Ws X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 Delay probe the cpu cluster TMC when all CPUs of this cluster are offline, re-probe the funnel when any CPU in the cluster comes online. Key changes: - Introduce a global list to track delayed TMCs waiting for CPU online. - Add CPU hotplug callback to retry registration when the CPU comes up. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tmc-core.c | 59 ++++++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tmc.h | 4 ++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 685a64d8ba1b5df4cff91694eee45c6d6a147bc1..7274ad07c2b20d2aa6e568b4bab= 0fbb57e331ab8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -36,6 +36,9 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); +static LIST_HEAD(tmc_delay_probe); +static enum cpuhp_state hp_online; +static DEFINE_SPINLOCK(delay_lock); =20 int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { @@ -1028,6 +1031,8 @@ static int __tmc_probe(struct device *dev, struct res= ource *res) if (!drvdata->cpumask) return -EINVAL; =20 + drvdata->dev =3D dev; + cpus_read_lock(); for_each_cpu(cpu, drvdata->cpumask) { ret =3D smp_call_function_single(cpu, @@ -1035,11 +1040,16 @@ static int __tmc_probe(struct device *dev, struct r= esource *res) if (!ret) break; } - cpus_read_unlock(); + if (ret) { + scoped_guard(spinlock, &delay_lock) + list_add(&drvdata->link, &tmc_delay_probe); + cpus_read_unlock(); ret =3D 0; goto out; } + + cpus_read_unlock(); } else { tmc_init_hw_config(drvdata); } @@ -1104,8 +1114,12 @@ static void __tmc_remove(struct device *dev) misc_deregister(&drvdata->miscdev); if (drvdata->crashdev.fops) misc_deregister(&drvdata->crashdev); - if (drvdata->csdev) + if (drvdata->csdev) { coresight_unregister(drvdata->csdev); + } else { + scoped_guard(spinlock, &delay_lock) + list_del(&drvdata->link); + } } =20 static void tmc_remove(struct amba_device *adev) @@ -1224,14 +1238,55 @@ static struct platform_driver tmc_platform_driver = =3D { }, }; =20 +static int tmc_online_cpu(unsigned int cpu) +{ + struct tmc_drvdata *drvdata, *tmp; + int ret; + + spin_lock(&delay_lock); + list_for_each_entry_safe(drvdata, tmp, &tmc_delay_probe, link) { + if (cpumask_test_cpu(cpu, drvdata->cpumask)) { + list_del(&drvdata->link); + + spin_unlock(&delay_lock); + ret =3D pm_runtime_resume_and_get(drvdata->dev); + if (ret < 0) + return 0; + + tmc_init_hw_config(drvdata); + tmc_clear_self_claim_tag(drvdata); + tmc_add_coresight_dev(drvdata->dev); + pm_runtime_put(drvdata->dev); + spin_lock(&delay_lock); + } + } + spin_unlock(&delay_lock); + return 0; +} + static int __init tmc_init(void) { + int ret; + + ret =3D cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight-tmc:online", + tmc_online_cpu, NULL); + + if (ret > 0) + hp_online =3D ret; + else + return ret; + return coresight_init_driver("tmc", &tmc_driver, &tmc_platform_driver, TH= IS_MODULE); } =20 static void __exit tmc_exit(void) { coresight_remove_driver(&tmc_driver, &tmc_platform_driver); + if (hp_online) { + cpuhp_remove_state_nocalls(hp_online); + hp_online =3D 0; + } } module_init(tmc_init); module_exit(tmc_exit); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index f5c76ca2dc9733daa020b79b1dcfc495045a2618..29ccf0b7f4fe90a93d926a2e273= 950bce9834336 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -246,6 +246,8 @@ struct tmc_resrv_buf { * @cpumask: CPU mask representing the CPUs related to this TMC. * @devid: TMC variant ID inferred from the device configuration register. * @desc_name: Name to be used while creating crash interface. + * @dev: pointer to the device associated with this TMC. + * @link: link to the delay_probed list. */ struct tmc_drvdata { struct clk *atclk; @@ -279,6 +281,8 @@ struct tmc_drvdata { struct cpumask *cpumask; u32 devid; const char *desc_name; + struct device *dev; + struct list_head link; }; =20 struct etr_buf_operations { --=20 2.34.1 From nobody Mon Feb 9 01:07:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF6842DF12C for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:29 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:13 -0700 Subject: [PATCH 11/12] coresight: add 'cs_mode' to link enable functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-11-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761632890; l=9332; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=RHNEaGFIW3gpssw+cDFCs3tIQo8VomibUYN0C5T6Wmw=; b=rBSWcpEK5L0N76d9lDJjO+2xVcgd0HyPQtiJDwUETgJrGbIE7jjS4M/bf2UYaV+RH2+5C31OG BZ8U5uDoHp6BeJTY53bqc/p2TOD0qAj1uC9WUYimjqjN69EJhGYhfC9 X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: cfry4l6rox-sL95aLSLQh6IGfl5dxF-6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDA1NCBTYWx0ZWRfXx3SAi70Uwg3p FytyXGWAQ2na31yNQhhP5C6y96aqVl09QGD9Qsvjy8iRybSDNzfRMsAmQ+cIlQBtvgsc2MCcLG7 coIaTTIjuUE0gd0xcmytgP2ZCrrh860QX47FdSNoSjeZT9uvoQUnobNQdN28Q11X26uQXSIvJKP adgyz+JG7FgPFOrjCYfALcmJBK5/9D/vp+zaXnPJ/9XKcSp2qqjgILzDfD8IH5RE5dhHTelDu2b DA9pjgtyGbX9CmpChOBmRik2zFTb3k9nyErIgPhAvKNJ+zcLYWJURysGOEbQJRteyuv6gxEFkH8 H4rVKKG0+aVoHcbPmCo4Y3hyrZkxdRMPSRP53L1FJBqbrx2ji2UFrSoyufr2rs2Mk74WqXHGn6N hi++y87qT5FDPG18ASenV1ZjZGQ/Pw== X-Proofpoint-GUID: cfry4l6rox-sL95aLSLQh6IGfl5dxF-6 X-Authority-Analysis: v=2.4 cv=fL40HJae c=1 sm=1 tr=0 ts=69006291 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=_ycWAoKx6aYVZ7XB0rUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510020000 definitions=main-2510280054 Extend the coresight link enable interfaces to accept an `enum cs_mode` argument. This allows link drivers to distinguish between sysfs and perf coresight modes when enabling links. This change is necessary because enabling CPU cluster links may involve calling `smp_call_function_single()`, which is unsafe in perf mode due to context constraints. By passing the tracing mode explicitly, link drivers can apply mode-specific logic to avoid unsafe operations. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-core.c | 7 ++++--- drivers/hwtracing/coresight/coresight-funnel.c | 21 ++++++++++++++++++= +- drivers/hwtracing/coresight/coresight-replicator.c | 23 ++++++++++++++++++= +++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 19 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tnoc.c | 3 ++- drivers/hwtracing/coresight/coresight-tpda.c | 3 ++- include/linux/coresight.h | 3 ++- 7 files changed, 70 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 3267192f0c1c667b0570b9100c3c449064e7fb5e..2e62005655dbcb9b504a1a5be39= 2a5b00ed567d4 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -313,7 +313,8 @@ static void coresight_disable_sink(struct coresight_dev= ice *csdev) static int coresight_enable_link(struct coresight_device *csdev, struct coresight_device *parent, struct coresight_device *child, - struct coresight_device *source) + struct coresight_device *source, + enum cs_mode mode) { int link_subtype; struct coresight_connection *inconn, *outconn; @@ -330,7 +331,7 @@ static int coresight_enable_link(struct coresight_devic= e *csdev, if (link_subtype =3D=3D CORESIGHT_DEV_SUBTYPE_LINK_SPLIT && IS_ERR(outcon= n)) return PTR_ERR(outconn); =20 - return link_ops(csdev)->enable(csdev, inconn, outconn); + return link_ops(csdev)->enable(csdev, inconn, outconn, mode); } =20 static void coresight_disable_link(struct coresight_device *csdev, @@ -546,7 +547,7 @@ int coresight_enable_path(struct coresight_path *path, = enum cs_mode mode, case CORESIGHT_DEV_TYPE_LINK: parent =3D list_prev_entry(nd, link)->csdev; child =3D list_next_entry(nd, link)->csdev; - ret =3D coresight_enable_link(csdev, parent, child, source); + ret =3D coresight_enable_link(csdev, parent, child, source, mode); if (ret) goto err_disable_helpers; break; diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 43b9287a865eb26ce021521e4a5f193c48188bba..fd8dcd541454bd804210fa0f80f= 2dcc49a908717 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -121,7 +121,8 @@ static int funnel_enable_hw(struct funnel_drvdata *drvd= ata, int port) =20 static int funnel_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct funnel_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -135,6 +136,23 @@ static int funnel_enable(struct coresight_device *csde= v, else in->dest_refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->cpumask && + !cpumask_test_cpu(smp_processor_id(), drvdata->cpumask)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_funnel_enable_hw(drvdata, in->dest_port); + if (!rc) + in->dest_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -183,6 +201,7 @@ static void funnel_disable(struct coresight_device *csd= ev, dynamic_funnel_disable_hw(drvdata, in->dest_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index 22c9bc71817d238c2d4ddffbb42678bf792b29af..6cb57763f9b10b68f9e129adfd6= a448edce2637d 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -199,7 +199,8 @@ static int replicator_enable_hw(struct replicator_drvda= ta *drvdata, =20 static int replicator_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int rc =3D 0; struct replicator_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -212,6 +213,25 @@ static int replicator_enable(struct coresight_device *= csdev, first_enable =3D true; else out->src_refcnt++; + + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->cpumask && + !cpumask_test_cpu(smp_processor_id(), drvdata->cpumask)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + if (drvdata->base) + rc =3D dynamic_replicator_enable(drvdata, in->dest_port, + out->src_port); + if (!rc) + out->src_refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (first_enable) { @@ -272,6 +292,7 @@ static void replicator_disable(struct coresight_device = *csdev, out->src_port); last_disable =3D true; } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 if (last_disable) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index b8a1c10d4b4c49144449b33f26710cf11713b338..281c3b316dc3c0d4fab4f06b709= 3825b741cf595 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -424,7 +424,8 @@ static int tmc_disable_etf_sink(struct coresight_device= *csdev) =20 static int tmc_enable_etf_link(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { int ret =3D 0; unsigned long flags; @@ -443,6 +444,22 @@ static int tmc_enable_etf_link(struct coresight_device= *csdev, if (!first_enable) csdev->refcnt++; =20 + if (mode =3D=3D CS_MODE_PERF) { + if (first_enable) { + if (drvdata->cpumask && + !cpumask_test_cpu(smp_processor_id(), drvdata->cpumask)) { + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EINVAL; + } + + ret =3D tmc_etf_enable_hw_local(drvdata); + if (!ret) + csdev->refcnt++; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); if (first_enable) { ret =3D tmc_etf_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index ff9a0a9cfe96e5f5e3077c750ea2f890cdd50d94..48e9e685b9439d92bdaae9e40d3= b3bc2d1ac1cd2 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -73,7 +73,8 @@ static void trace_noc_enable_hw(struct trace_noc_drvdata = *drvdata) } =20 static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, - struct coresight_connection *outport) + struct coresight_connection *outport, + enum cs_mode mode) { struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index 333b3cb236859f0feb1498f4ab81037c772143fd..4af433145728c9e5b600a4e58df= e8931447200f8 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -197,7 +197,8 @@ static int __tpda_enable(struct tpda_drvdata *drvdata, = int port) =20 static int tpda_enable(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out) + struct coresight_connection *out, + enum cs_mode mode) { struct tpda_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); int ret =3D 0; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6de59ce8ef8ca45c29e2f09c1b979eb7686b685f..f4d522dc096cb9d0f8d2d8b7ce8= a90574bf7c5e1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -385,7 +385,8 @@ struct coresight_ops_sink { struct coresight_ops_link { int (*enable)(struct coresight_device *csdev, struct coresight_connection *in, - struct coresight_connection *out); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498cf359asm102503265ad.12.2025.10.27.23.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Oct 2025 23:28:32 -0700 (PDT) From: Yuanfang Zhang Date: Mon, 27 Oct 2025 23:28:14 -0700 Subject: [PATCH 12/12] arm64: dts: qcom: x1e80100: add Coresight nodes for APSS debug block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251027-cpu_cluster_component_pm-v1-12-31355ac588c2@oss.qualcomm.com> References: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> In-Reply-To: <20251027-cpu_cluster_component_pm-v1-0-31355ac588c2@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Leo Yan , Alexander Shishkin , Bjorn Andersson , Konrad Dybcio Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Yuanfang Zhang , Jie Gan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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}; =20 + port@4 { + reg =3D <4>; + + funnel1_in4: endpoint { + remote-endpoint =3D <&apss_funnel_out>; + }; + }; + port@5 { reg =3D <5>; =20 @@ -7887,6 +7895,883 @@ ddr_funnel1_out: endpoint { }; }; =20 + apss_funnel: funnel@12080000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x12080000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + apss_funnel_in0: endpoint { + remote-endpoint =3D <&ncc0_etf_out>; + }; + }; + + port@1 { + reg =3D <1>; + + apss_funnel_in1: endpoint { + remote-endpoint =3D <&ncc1_etf_out>; + }; + }; + + port@2 { + reg =3D <2>; + + apss_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_etf_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint =3D + <&funnel1_in4>; + }; + }; + }; + }; + + etm@13021000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint =3D <&ncc0_0_rep_in>; + }; + }; + }; + }; + + etm@13121000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint =3D <&ncc0_1_rep_in>; + }; + }; + }; + }; + + etm@13221000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint =3D <&ncc0_2_rep_in>; + }; + }; + }; + }; + + etm@13321000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint =3D <&ncc0_3_rep_in>; + }; + }; + }; + }; + + funnel@13401000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x13401000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc0_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc0_etf_in>; + }; + }; + }; + }; + + tmc@13409000 { + compatible =3D "arm,coresight-cpu-tmc"; + reg =3D <0x0 0x13409000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + port { + ncc0_etf_in: endpoint { + remote-endpoint =3D <&ncc0_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc0_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in0>; + }; + }; + }; + }; + + replicator@13490000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13490000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + port { + ncc0_0_rep_in: endpoint { + remote-endpoint =3D <&etm0_out>; + }; + }; + }; + + out-ports { + port { + ncc0_0_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in0>; + }; + }; + }; + }; + + replicator@134a0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x134a0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + port { + ncc0_1_rep_in: endpoint { + remote-endpoint =3D <&etm1_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in1>; + }; + }; + }; + }; + + replicator@134b0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x134b0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + port { + ncc0_2_rep_in: endpoint { + remote-endpoint =3D <&etm2_out>; + }; + }; + }; + + out-ports { + port { + ncc0_2_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in2>; + }; + }; + }; + }; + + replicator@134c0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x134c0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + port { + ncc0_3_rep_in: endpoint { + remote-endpoint =3D <&etm3_out>; + }; + }; + }; + + out-ports { + port { + ncc0_3_rep_out: endpoint { + remote-endpoint =3D <&ncc0_1_funnel_in3>; + }; + }; + }; + }; + + funnel@134d0000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x134d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd0>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc0_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc0_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc0_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc0_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc0_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc0_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc0_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc0_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc0_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc0_2_funnel_in2>; + }; + }; + }; + }; + + etm@13521000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu4>; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint =3D <&ncc1_0_rep_in>; + }; + }; + }; + }; + + etm@13621000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu5>; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint =3D <&ncc1_1_rep_in>; + }; + }; + }; + }; + + etm@13721000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu6>; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint =3D <&ncc1_2_rep_in>; + }; + }; + }; + }; + + etm@13821000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu7>; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint =3D <&ncc1_3_rep_in>; + }; + }; + }; + }; + + funnel@13901000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x13901000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc1_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc1_etf_in>; + }; + }; + }; + }; + + tmc@13909000 { + compatible =3D "arm,coresight-cpu-tmc"; + reg =3D <0x0 0x13909000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + port { + ncc1_etf_in: endpoint { + remote-endpoint =3D <&ncc1_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc1_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in1>; + }; + }; + }; + }; + + replicator@13990000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13990000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + port { + ncc1_0_rep_in: endpoint { + remote-endpoint =3D <&etm4_out>; + }; + }; + }; + + out-ports { + port { + ncc1_0_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in0>; + }; + }; + }; + }; + + replicator@139a0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x139a0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + port { + ncc1_1_rep_in: endpoint { + remote-endpoint =3D <&etm5_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in1>; + }; + }; + }; + }; + + replicator@139b0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x139b0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + port { + ncc1_2_rep_in: endpoint { + remote-endpoint =3D <&etm6_out>; + }; + }; + }; + + out-ports { + port { + ncc1_2_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in2>; + }; + }; + }; + }; + + replicator@139c0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x139c0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + port { + ncc1_3_rep_in: endpoint { + remote-endpoint =3D <&etm7_out>; + }; + }; + }; + + out-ports { + port { + ncc1_3_rep_out: endpoint { + remote-endpoint =3D <&ncc1_1_funnel_in3>; + }; + }; + }; + }; + + funnel@139d0000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x139d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd1>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc1_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc1_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc1_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc1_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc1_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc1_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc1_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc1_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc1_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc1_2_funnel_in2>; + }; + }; + }; + }; + + etm8: etm@13a21000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu8>; + qcom,skip-power-up; + + out-ports { + port { + etm8_out: endpoint { + remote-endpoint =3D <&ncc2_0_rep_in>; + }; + }; + }; + }; + + etm9: etm@13b21000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu9>; + qcom,skip-power-up; + + out-ports { + port { + etm9_out: endpoint { + remote-endpoint =3D <&ncc2_1_rep_in>; + }; + }; + }; + }; + + etm10: etm@13c21000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu10>; + qcom,skip-power-up; + + out-ports { + port { + etm10_out: endpoint { + remote-endpoint =3D <&ncc2_2_rep_in>; + }; + }; + }; + }; + + etm11: etm@13d21000 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu11>; + qcom,skip-power-up; + + out-ports { + port { + etm11_out: endpoint { + remote-endpoint =3D <&ncc2_3_rep_in>; + }; + }; + }; + }; + + cluster2_funnel_l2: funnel@13e01000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x13e01000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + ncc2_2_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_funnel_out: endpoint { + remote-endpoint =3D <&ncc2_etf_in>; + }; + }; + }; + }; + + cluster2_etf: tmc@13e09000 { + compatible =3D "arm,coresight-cpu-tmc"; + reg =3D <0x0 0x13e09000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + port { + ncc2_etf_in: endpoint { + remote-endpoint =3D <&ncc2_2_funnel_out>; + }; + }; + }; + + out-ports { + port { + ncc2_etf_out: endpoint { + remote-endpoint =3D <&apss_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_0: replicator@13e90000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13e90000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + port { + ncc2_0_rep_in: endpoint { + remote-endpoint =3D <&etm8_out>; + }; + }; + }; + + out-ports { + port { + ncc2_0_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in0>; + }; + }; + }; + }; + + cluster2_rep_2_1: replicator@13ea0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13ea0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + port { + ncc2_1_rep_in: endpoint { + remote-endpoint =3D <&etm9_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in1>; + }; + }; + }; + }; + + cluster2_rep_2_2: replicator@13eb0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13eb0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + port { + ncc2_2_rep_in: endpoint { + remote-endpoint =3D <&etm10_out>; + }; + }; + }; + + out-ports { + port { + ncc2_2_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in2>; + }; + }; + }; + }; + + cluster2_rep_2_3: replicator@13ec0000 { + compatible =3D "arm,coresight-cpu-replicator"; + reg =3D <0x0 0x13ec0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + port { + ncc2_3_rep_in: endpoint { + remote-endpoint =3D <&etm11_out>; + }; + }; + }; + + out-ports { + port { + ncc2_3_rep_out: endpoint { + remote-endpoint =3D <&ncc2_1_funnel_in3>; + }; + }; + }; + }; + + cluster2_funnel_l1: funnel@13ed0000 { + compatible =3D "arm,coresight-cpu-funnel"; + reg =3D <0x0 0x13ed0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + power-domains =3D <&cluster_pd2>; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ncc2_1_funnel_in0: endpoint { + remote-endpoint =3D <&ncc2_0_rep_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ncc2_1_funnel_in1: endpoint { + remote-endpoint =3D <&ncc2_1_rep_out>; + }; + }; + + port@2 { + reg =3D <2>; + + ncc2_1_funnel_in2: endpoint { + remote-endpoint =3D <&ncc2_2_rep_out>; + }; + }; + + port@3 { + reg =3D <3>; + + ncc2_1_funnel_in3: endpoint { + remote-endpoint =3D <&ncc2_3_rep_out>; + }; + }; + }; + + out-ports { + port { + ncc2_1_funnel_out: endpoint { + remote-endpoint =3D <&ncc2_2_funnel_in2>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0 0x15000000 0 0x100000>; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/q= com/x1p42100.dtsi index 9af9e707f982fe45f62a9420b1e6baa1fef4d2fa..9b5fe04ed05cc33fe6d0a353564= 8d318f6cc3a80 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -19,6 +19,18 @@ /delete-node/ &cpu_pd11; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; +/delete-node/ &etm8; +/delete-node/ &etm9; +/delete-node/ &etm10; +/delete-node/ &etm11; +/delete-node/ &cluster2_funnel_l1; +/delete-node/ &cluster2_funnel_l2; +/delete-node/ &cluster2_etf; +/delete-node/ &cluster2_rep_2_0; +/delete-node/ &cluster2_rep_2_1; +/delete-node/ &cluster2_rep_2_2; +/delete-node/ &cluster2_rep_2_3; +/delete-node/ &apss_funnel_in2; =20 &gcc { compatible =3D "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; --=20 2.34.1