From nobody Sat Feb 7 23:00:25 2026 Received: from mxout3.routing.net (mxout3.routing.net [134.0.28.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CBF310E3; Sun, 26 Oct 2025 12:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481846; cv=none; b=uvWBXBqDoG7L+bDqonmIRCF1hHoD5D18bG+MACzUMaRNYVKLz0xmg61LhhcdJqq9TV4czYo+VU4AilOWIcAFlAlwgPqA4qJCWBnrBtkl58jVgtSLrxc4pSIhiWXmaTeVi6ojTNAcH0N6ISM21d/EZgtdxjbzumtnMgod0NLSNxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481846; c=relaxed/simple; bh=FYbtBW4yebr7GZlwdi/roTYzRuQuBFijpmv4L+YCcvM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C1VRr3p77TtPi7zYRHLJdCYd7UtVnPBmoSN2fUJyTsiKUQE5BZekH34jpZT1AW7+E4sBfFw9/kPtGzrs3Zv0b5SzgBjU+qxRJMhNgS0Cf4zeg2E9pqJU2FDMNSgTinstzIXUIEKFPk5u+xk028jbkqmXtWrT5PaDIaForycUyTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=jzFkCQ0r; arc=none smtp.client-ip=134.0.28.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="jzFkCQ0r" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout3.routing.net (Postfix) with ESMTP id EAA3160666; Sun, 26 Oct 2025 12:22:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1761481325; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=utgZIgZouZ2rivSw9fdUqvFMGknqClgIGWmWeoQd928=; b=jzFkCQ0rm5xX/AZDOCLrqTZSn5am4MENCC0H+Ho2xlaXNHXFgJ+AKsYvXjQeqZpOg6wnjb sPKmZvIwR5nnDZUB+kEYwVgNSXKErXUBoXuXLCUBbExorNtKZaNfeUL24rDCftc4ry0Poo b96b3Ur9mhDC6x3sKXiF1rhmN9LZh1Q= Received: from frank-u24.. (fttx-pool-217.61.154.70.bambit.de [217.61.154.70]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id AA9F51226F7; Sun, 26 Oct 2025 12:22:04 +0000 (UTC) From: Frank Wunderlich To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Mason Chang , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Balsam CHIHI , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 1/5] dt-bindings: thermal: mediatek: make interrupt only required for current SoCs Date: Sun, 26 Oct 2025 13:21:30 +0100 Message-ID: <20251026122143.71100-2-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026122143.71100-1-linux@fw-web.de> References: <20251026122143.71100-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Upcoming MT7987 does not have a IRQ we have to make interrupt-property only required for current supported SoCs. Signed-off-by: Frank Wunderlich --- .../bindings/thermal/mediatek,lvts-thermal.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-therma= l.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.ya= ml index 0259cd3ce9c5..7ec9c46eef22 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -58,6 +58,16 @@ properties: allOf: - $ref: thermal-sensor.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt7988-lvts-ap + then: + required: + - interrupts + - if: properties: compatible: @@ -75,6 +85,9 @@ allOf: nvmem-cell-names: maxItems: 1 =20 + required: + - interrupts + - if: properties: compatible: @@ -91,10 +104,12 @@ allOf: nvmem-cell-names: minItems: 2 =20 + required: + - interrupts + required: - compatible - reg - - interrupts - clocks - resets - nvmem-cells --=20 2.43.0 From nobody Sat Feb 7 23:00:25 2026 Received: from mxout2.routing.net (mxout2.routing.net [134.0.28.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F17328724D; Sun, 26 Oct 2025 12:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481911; cv=none; b=GLjKAfrTIl2LmxHSJbZs9NdWldkGzOYWpBH/t7I4bfpqQyDJchDf0KY8DsNemvUgr0VcANrBFsubz+QTxkuTcv20XSMoVaALogB6URqvOCouTMFDoeJs0HhKTBPmF9C6QIBNRx34w9BVDz2L/ybQjSI+FQAcSoRRwpI4mdZ4YWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481911; c=relaxed/simple; bh=3A6NWFIsP5XoXA/AEOYp2kgioSTLb9Q2LPR3Gx5m+3Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RrhBPn+Vig0iIAK3IryDcvHVDEDUb/dJ0NPs9gZxXnM5CTkdKqGCTwPeOiPK5C1ftu3tH0E2n3A/uSQRwdP0OHqEs1WY7bTZ0mv+hJsJhvdyDd14d+K/0Rz6UhXBsZ/ytUf2NTlMMnuS4W98Z/08RAJRW37IiyRNuo6IVpzDW7U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=nVr8C+Vn; arc=none smtp.client-ip=134.0.28.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="nVr8C+Vn" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout2.routing.net (Postfix) with ESMTP id 34C575FE3B; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1761481325; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ho+w8/wSlfCk13S0AyROefe1juINq8GVHtpVrKG2OZs=; b=nVr8C+Vn+KAo+Bd+a4p465nQp0MfJnNckoX0+J3zBPfUZ6730yJqjkPXPOg0gVrNqSd9BL lUDlXaRy/xNHuOhNc/qQni2AWjgh+izzFJKxFSbygcy92F83hU7sXkgqz29unsA5hvsHp8 offO6xk3GadQLvRKQsoHWPjvUBrLfVc= Received: from frank-u24.. (fttx-pool-217.61.154.70.bambit.de [217.61.154.70]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id E847A122700; Sun, 26 Oct 2025 12:22:04 +0000 (UTC) From: Frank Wunderlich To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Mason Chang , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Balsam CHIHI , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 2/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT7987 Date: Sun, 26 Oct 2025 13:21:31 +0100 Message-ID: <20251026122143.71100-3-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026122143.71100-1-linux@fw-web.de> References: <20251026122143.71100-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add thermal controller definition for MT7987. Signed-off-by: Frank Wunderlich Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/thermal/mediatek,lvts-thermal.yaml | 1 + include/dt-bindings/thermal/mediatek,lvts-thermal.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-therma= l.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.ya= ml index 7ec9c46eef22..13e948a2a909 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - mediatek,mt7987-lvts-ap - mediatek,mt7988-lvts-ap - mediatek,mt8186-lvts - mediatek,mt8188-lvts-ap diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index ddc7302a510a..e9780edcd26c 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -7,6 +7,9 @@ #ifndef __MEDIATEK_LVTS_DT_H #define __MEDIATEK_LVTS_DT_H =20 +#define MT7987_CPU 0 +#define MT7987_ETH2P5G 1 + #define MT7988_CPU_0 0 #define MT7988_CPU_1 1 #define MT7988_ETH2P5G_0 2 --=20 2.43.0 From nobody Sat Feb 7 23:00:25 2026 Received: from mxout2.routing.net (mxout2.routing.net [134.0.28.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0C7428BA83; Sun, 26 Oct 2025 12:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481912; cv=none; b=HRpKYrQ579lsreNM6dmT++4GvQ131UMp2YuYGkgzPY8JLdRdEd5vAf4aWHE7GduR3PeYBybFTf1pdFljWx/ZbjL4w6vZ+QWbZ8sGjM3591itkDGu1NFQTF4dy+GARlcFgK47MD3UhnJw1J30Wsc32VN3mM9n7RDh9Bb9r2vzneA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481912; c=relaxed/simple; bh=zwniZlxloGKkihQAQmGZNdKCwt+F5x7WAUh5EQNZHjE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hx2cTMkTnuob35HrnN941DcAEJHKgqqEUVarxFS9iZsEe0iHeRj0kwMsTlAC8PobxtqFX3a5+FImDHH6XZKj0O4I6TQdbrNBzm4sMFKM6nJL8atkSjjWmNr5It8nnyauf6D+XG575ev047n8NQHEbykgAlt4gW8YxExG5xQT3fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=H5fyZmsx; arc=none smtp.client-ip=134.0.28.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="H5fyZmsx" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout2.routing.net (Postfix) with ESMTP id 6A3535FE85; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1761481325; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BBBB63EbQu+3f69j7eVhdhDTMGpiISE40F1PbWVxzkk=; b=H5fyZmsxeTaTkwjUhvyWEMIY+V43xldUQTi4lENvCw/BoYIq5r0akakLk6SFNtUyyHDcHX +4qHOsMVIT2u5ZSYMAHvF4Y/Iey116ekP0R/bSknUR7Y6ZVBALu/L8oE4nTfuQs4NnLyNz 2Ep6/ysaC3vmoA01tUeTb6FsPiNGwy8= Received: from frank-u24.. (fttx-pool-217.61.154.70.bambit.de [217.61.154.70]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 310831226BC; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) From: Frank Wunderlich To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Mason Chang , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Balsam CHIHI , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 3/5] thermal/drivers/mediatek/lvts_thermal: Add no-irq-mode for mt7987 Date: Sun, 26 Oct 2025 13:21:32 +0100 Message-ID: <20251026122143.71100-4-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026122143.71100-1-linux@fw-web.de> References: <20251026122143.71100-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Upcoming MT7987 does not have IRQ for thermal. Add a field in lvts_data to configure this based on SoC. Signed-off-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++++++----- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index ab55b20cda47..9413b30f7b69 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -94,6 +94,8 @@ #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) =20 +#define LVTS_HW_RESET_TEMP 125000 + #define LVTS_MINIMUM_THRESHOLD 20000 =20 static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; @@ -134,6 +136,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + bool irq_enable; }; =20 struct lvts_sensor { @@ -151,6 +154,7 @@ struct lvts_ctrl { const struct lvts_data *lvts_data; u32 calibration[LVTS_SENSOR_MAX]; u8 valid_sensor_mask; + u32 hw_reset_raw_temp; int mode; void __iomem *base; int low_thresh; @@ -410,6 +414,9 @@ static int lvts_set_trips(struct thermal_zone_device *t= z, int low, int high) } lvts_update_irq_mask(lvts_ctrl); =20 + if (!lvts_data->irq_enable) + return 0; + if (!should_update_thresh) return 0; =20 @@ -859,6 +866,14 @@ static int lvts_ctrl_init(struct device *dev, struct l= vts_domain *lvts_td, */ lvts_ctrl[i].mode =3D lvts_data->lvts_ctrl[i].mode; =20 + /* + * The temperature to raw temperature must be done + * after initializing the calibration. + */ + lvts_ctrl[i].hw_reset_raw_temp =3D + lvts_temp_to_raw(LVTS_HW_RESET_TEMP, + lvts_data->temp_factor); + lvts_ctrl[i].low_thresh =3D INT_MIN; lvts_ctrl[i].high_thresh =3D INT_MIN; } @@ -915,12 +930,13 @@ static void lvts_write_config(struct lvts_ctrl *lvts_= ctrl, const u32 *cmds, int */ for (i =3D 0; i < nr_cmds; i++) { writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); - usleep_range(2, 4); + usleep_range(5, 15); } } =20 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) { + const struct lvts_data *lvts_data =3D lvts_ctrl->lvts_data; /* * LVTS_PROTCTL : Thermal Protection Sensor Selection * @@ -954,8 +970,12 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS * register, except we set the bits to enable the interrupt. */ - writel(0, LVTS_MONINT(lvts_ctrl->base)); - + if (lvts_data->irq_enable) { + writel(0, LVTS_MONINT(lvts_ctrl->base)); + } else { + writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); + writel(lvts_ctrl->hw_reset_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); + } return 0; } =20 @@ -1338,9 +1358,11 @@ static int lvts_probe(struct platform_device *pdev) if (IS_ERR(lvts_td->reset)) return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset = control\n"); =20 - irq =3D platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (lvts_data->irq_enable) { + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } =20 golden_temp_offset =3D lvts_data->temp_offset; =20 @@ -1352,10 +1374,12 @@ static int lvts_probe(struct platform_device *pdev) * At this point the LVTS is initialized and enabled. We can * safely enable the interrupt. */ - ret =3D devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, - IRQF_ONESHOT, dev_name(dev), lvts_td); - if (ret) - return dev_err_probe(dev, ret, "Failed to request interrupt\n"); + if (lvts_data->irq_enable) { + ret =3D devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, + IRQF_ONESHOT, dev_name(dev), lvts_td); + if (ret) + return dev_err_probe(dev, ret, "Failed to request interrupt\n"); + } =20 platform_set_drvdata(pdev, lvts_td); =20 @@ -1763,6 +1787,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, + .irq_enable =3D true, //SDK false }; =20 static const struct lvts_data mt8186_lvts_data =3D { @@ -1776,6 +1801,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .temp_offset =3D LVTS_COEFF_B_MT7988, .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8188_lvts_mcu_data =3D { @@ -1789,6 +1815,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8188_lvts_ap_data =3D { @@ -1802,6 +1829,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8192_lvts_mcu_data =3D { @@ -1815,6 +1843,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8192_lvts_ap_data =3D { @@ -1828,6 +1857,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8195_lvts_mcu_data =3D { @@ -1841,6 +1871,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .temp_offset =3D LVTS_COEFF_B_MT8195, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, + .irq_enable =3D true, }; =20 static const struct lvts_data mt8195_lvts_ap_data =3D { --=20 2.43.0 From nobody Sat Feb 7 23:00:25 2026 Received: from mxout1.routing.net (mxout1.routing.net [134.0.28.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5AA41DA23; Sun, 26 Oct 2025 12:31:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.0.28.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481877; cv=none; b=Msgw5xRjHvij0B+F6w08zXOp4HvhxHfmQCvsgmGAIDDu4qUlM+o8cmpss3rXlYWLdRUvupMJaZEYZj/vAmwob04xt8nlG8bdxTS8/0KFb5rlhAxY6dCBj7kqNtGWtp61MUHjIsKR9hHNkRmwSlyFZ2qo4FvWHU/uojyD/D/uQIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761481877; c=relaxed/simple; bh=WKw7dDEx74rUPEVO41nKsVffxoxsW+xqBWzteYJXNFQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCiiSsQzs4Mhjrxg5Ke+aDJsO0XvAHcmf8YU5aMpjsRTAanRyArAsvns/8rtEQZ9apEJTDrRS0b4TBc41/6sGIEErMP6KM1e358TE5j4El/56EqCEFs5aDsq9AhrJPSkTlIG0++prvV7AHsgyESGtwutRomcm808seBiBJ3xbHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de; spf=pass smtp.mailfrom=fw-web.de; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b=slZAivgU; arc=none smtp.client-ip=134.0.28.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fw-web.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fw-web.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mailerdienst.de header.i=@mailerdienst.de header.b="slZAivgU" Received: from mxbulk.masterlogin.de (unknown [192.168.10.85]) by mxout1.routing.net (Postfix) with ESMTP id AE13F40027; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailerdienst.de; s=routing; t=1761481325; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2xhSctYjH9Rr38j6lYic7dZqTUlNx7v9z2EjOasSd8c=; b=slZAivgUGmXS6MXAwMunhdNmLh1re0Cepb/YihkUrtunpWcf2mfGvV+82+C2zd+Ww2gCTB IPe+N1tyT8sEskbkt4ADY/8PktYZNDOPKJe/XmNOUkHMyY9Eda9b0tFDME457o084HlT8C YVMNgfrcE3XNgvR2sgyWCG9qhGuOfbc= Received: from frank-u24.. (fttx-pool-217.61.154.70.bambit.de [217.61.154.70]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id 70EA71226F7; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) From: Frank Wunderlich To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Mason Chang , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Balsam CHIHI , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 4/5] thermal/drivers/mediatek/lvts_thermal: Add SoC based golden Temp Date: Sun, 26 Oct 2025 13:21:33 +0100 Message-ID: <20251026122143.71100-5-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026122143.71100-1-linux@fw-web.de> References: <20251026122143.71100-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add SoC based golden temp for invalid efuse data. This is a preliminary patch for mt7987 support where goldentemp is slightly higher than other SOCs. Signed-off-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 9413b30f7b69..544941e8219a 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -134,6 +134,7 @@ struct lvts_data { int num_init_cmd; int temp_factor; int temp_offset; + int golden_temp; int gt_calib_bit_offset; unsigned int def_calibration; bool irq_enable; @@ -811,8 +812,10 @@ static int lvts_golden_temp_init(struct device *dev, u= 8 *calib, gt =3D (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; =20 /* A zero value for gt means that device has invalid efuse data */ - if (gt && gt < LVTS_GOLDEN_TEMP_MAX) + if (gt && gt <=3D LVTS_GOLDEN_TEMP_MAX) golden_temp =3D gt; + else + golden_temp =3D lvts_data->golden_temp; =20 golden_temp_offset =3D golden_temp * 500 + lvts_data->temp_offset; =20 @@ -1786,6 +1789,7 @@ static const struct lvts_data mt7988_lvts_ap_data =3D= { .num_init_cmd =3D ARRAY_SIZE(mt7988_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .irq_enable =3D true, //SDK false }; @@ -1799,6 +1803,7 @@ static const struct lvts_data mt8186_lvts_data =3D { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT7988, .temp_offset =3D LVTS_COEFF_B_MT7988, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .def_calibration =3D 19000, .irq_enable =3D true, @@ -1813,6 +1818,7 @@ static const struct lvts_data mt8188_lvts_mcu_data = =3D { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .irq_enable =3D true, @@ -1827,6 +1833,7 @@ static const struct lvts_data mt8188_lvts_ap_data =3D= { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 20, .def_calibration =3D 35000, .irq_enable =3D true, @@ -1841,6 +1848,7 @@ static const struct lvts_data mt8192_lvts_mcu_data = =3D { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .irq_enable =3D true, @@ -1855,6 +1863,7 @@ static const struct lvts_data mt8192_lvts_ap_data =3D= { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .irq_enable =3D true, @@ -1869,6 +1878,7 @@ static const struct lvts_data mt8195_lvts_mcu_data = =3D { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, .irq_enable =3D true, @@ -1883,6 +1893,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { .num_init_cmd =3D ARRAY_SIZE(default_init_cmds), .temp_factor =3D LVTS_COEFF_A_MT8195, .temp_offset =3D LVTS_COEFF_B_MT8195, + .golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT, .gt_calib_bit_offset =3D 24, .def_calibration =3D 35000, }; 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(fttx-pool-217.61.154.70.bambit.de [217.61.154.70]) by mxbulk.masterlogin.de (Postfix) with ESMTPSA id AFA1A1226BC; Sun, 26 Oct 2025 12:22:05 +0000 (UTC) From: Frank Wunderlich To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Mason Chang , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Balsam CHIHI , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 5/5] thermal/drivers/mediatek/lvts_thermal: Add mt7987 support Date: Sun, 26 Oct 2025 13:21:34 +0100 Message-ID: <20251026122143.71100-6-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251026122143.71100-1-linux@fw-web.de> References: <20251026122143.71100-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add support for MT7987. Signed-off-by: Frank Wunderlich --- drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 544941e8219a..1d800bdf4a24 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -87,6 +87,8 @@ #define LVTS_COEFF_B_MT8195 250460 #define LVTS_COEFF_A_MT7988 -204650 #define LVTS_COEFF_B_MT7988 204650 +#define LVTS_COEFF_A_MT7987 -204650 +#define LVTS_COEFF_B_MT7987 204650 =20 #define LVTS_MSR_IMMEDIATE_MODE 0 #define LVTS_MSR_FILTERED_MODE 1 @@ -1400,6 +1402,20 @@ static void lvts_remove(struct platform_device *pdev) lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); } =20 +static const struct lvts_ctrl_data mt7987_lvts_ap_data_ctrl[] =3D { + { + .lvts_sensor =3D { + { .dt_id =3D MT7987_CPU, + .cal_offsets =3D { 0x04, 0x05, 0x06 } }, + { .dt_id =3D MT7987_ETH2P5G, + .cal_offsets =3D { 0x08, 0x09, 0x0a } }, + }, + VALID_SENSOR_MAP(1, 1, 0, 0), + .offset =3D 0x0, + .mode =3D LVTS_MSR_FILTERED_MODE, + }, +}; + static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] =3D { { .lvts_sensor =3D { @@ -1482,6 +1498,12 @@ static const u32 default_init_cmds[] =3D { 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 }; =20 +static const u32 mt7987_init_cmds[] =3D { + 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC10308C7, + 0xC103098D, 0xC1030C7C, 0xC1030AA8, 0xC10308CE, 0xC10308C7, + 0xC1030B04, 0xC1030E01, 0xC10306B8 +}; + static const u32 mt7988_init_cmds[] =3D { 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, @@ -1780,6 +1802,21 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_data mt7987_lvts_ap_data =3D { + .lvts_ctrl =3D mt7987_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt7987_lvts_ap_data_ctrl), + .conn_cmd =3D mt7988_conn_cmds, + .init_cmd =3D mt7987_init_cmds, + .num_conn_cmd =3D ARRAY_SIZE(mt7988_conn_cmds), + .num_init_cmd =3D ARRAY_SIZE(mt7987_init_cmds), + .temp_factor =3D LVTS_COEFF_A_MT7987, + .temp_offset =3D LVTS_COEFF_B_MT7987, + .golden_temp =3D 60, + .gt_calib_bit_offset =3D 32, + .def_calibration =3D 19380, + .irq_enable =3D false, +}; + static const struct lvts_data mt7988_lvts_ap_data =3D { .lvts_ctrl =3D mt7988_lvts_ap_data_ctrl, .conn_cmd =3D mt7988_conn_cmds, @@ -1899,6 +1936,7 @@ static const struct lvts_data mt8195_lvts_ap_data =3D= { }; =20 static const struct of_device_id lvts_of_match[] =3D { + { .compatible =3D "mediatek,mt7987-lvts-ap", .data =3D &mt7987_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt7988-lvts-ap", .data =3D &mt7988_lvts_ap_da= ta }, { .compatible =3D "mediatek,mt8186-lvts", .data =3D &mt8186_lvts_data }, { .compatible =3D "mediatek,mt8188-lvts-mcu", .data =3D &mt8188_lvts_mcu_= data }, --=20 2.43.0