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Sat, 25 Oct 2025 14:07:23 -0700 (PDT) From: Sergey Matyukevich To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Shuah Khan , Thomas Huth , Charlie Jenkins , Andy Chiu , Samuel Holland , Joel Granados , Conor Dooley , Yong-Xuan Wang , Heiko Stuebner , Sergey Matyukevich Subject: [PATCH v3 7/9] selftests: riscv: verify ptrace rejects invalid vector csr inputs Date: Sun, 26 Oct 2025 00:06:40 +0300 Message-ID: <20251025210655.43099-8-geomatsi@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251025210655.43099-1-geomatsi@gmail.com> References: <20251025210655.43099-1-geomatsi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test to v_ptrace test suite to verify that ptrace rejects the invalid input combinations of vector csr registers. Use kselftest fixture variants to create multiple invalid inputs for the test. Signed-off-by: Sergey Matyukevich --- .../testing/selftests/riscv/vector/v_ptrace.c | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) diff --git a/tools/testing/selftests/riscv/vector/v_ptrace.c b/tools/testin= g/selftests/riscv/vector/v_ptrace.c index 9fea29f7b686..6f3f228c0954 100644 --- a/tools/testing/selftests/riscv/vector/v_ptrace.c +++ b/tools/testing/selftests/riscv/vector/v_ptrace.c @@ -183,4 +183,236 @@ TEST(ptrace_v_early_debug) } } =20 +FIXTURE(v_csr_invalid) +{ +}; + +FIXTURE_SETUP(v_csr_invalid) +{ +} + +FIXTURE_TEARDOWN(v_csr_invalid) +{ +} + +/* modifications of the initial 'vsetvli x0, x0, e8, m8, tu, mu' settings = */ +FIXTURE_VARIANT(v_csr_invalid) +{ + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + unsigned long vlenb_mul; + unsigned long vlenb_min; + unsigned long vlenb_max; +}; + +/* unexpected vlenb value */ +FIXTURE_VARIANT_ADD(v_csr_invalid, new_vlenb) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x2, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid reserved bits in vcsr */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vcsr_invalid_reserved_bits) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x3, + .vcsr =3D 0x1UL << 8, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid reserved bits in vtype */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vtype_invalid_reserved_bits) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D (0x1UL << 8) | 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* set vill bit */ +FIXTURE_VARIANT_ADD(v_csr_invalid, invalid_vill_bit) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D (0x1UL << (__riscv_xlen - 1)) | 0x3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* reserved vsew value: vsew > 3 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vsew) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x4UL << 3, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* reserved vlmul value: vlmul =3D=3D 4 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, reserved_vlmul) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x4, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x0, +}; + +/* invalid fractional LMUL for VLEN <=3D 256: LMUL=3D 1/8, SEW =3D 64 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, frac_lmul1) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x1d, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x20, +}; + +/* invalid integral LMUL for VLEN <=3D 16: LMUL=3D 2, SEW =3D 64 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, int_lmul1) +{ + .vstart =3D 0x0, + .vl =3D 0x0, + .vtype =3D 0x19, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x2, +}; + +/* invalid VL for VLEN <=3D 128: LMUL=3D 2, SEW =3D 64, VL =3D 8 */ +FIXTURE_VARIANT_ADD(v_csr_invalid, vl1) +{ + .vstart =3D 0x0, + .vl =3D 0x8, + .vtype =3D 0x19, + .vcsr =3D 0x0, + .vlenb_mul =3D 0x1, + .vlenb_min =3D 0x0, + .vlenb_max =3D 0x10, +}; + +TEST_F(v_csr_invalid, ptrace_v_invalid_values) +{ + unsigned long vlenb; + pid_t pid; + + if (!is_vector_supported()) + SKIP(return, "Vector not supported"); + + asm volatile("csrr %[vlenb], vlenb" : [vlenb] "=3Dr"(vlenb)); + if (variant->vlenb_min) { + if (vlenb < variant->vlenb_min) + SKIP(return, "This test does not support VLEN < %lu\n", + variant->vlenb_min * 8); + } + if (variant->vlenb_max) { + if (vlenb > variant->vlenb_max) + SKIP(return, "This test does not support VLEN > %lu\n", + variant->vlenb_max * 8); + } + + chld_lock =3D 1; + pid =3D fork(); + ASSERT_LE(0, pid) + TH_LOG("fork: %m"); + + if (pid =3D=3D 0) { + while (chld_lock =3D=3D 1) + asm volatile("" : : "g"(chld_lock) : "memory"); + + asm(".option arch, +zve32x\n"); + asm(".option arch, +c\n"); + asm volatile("vsetvli x0, x0, e8, m8, tu, mu\n"); + + while (1) { + asm volatile("c.ebreak"); + asm volatile("c.nop"); + } + } else { + struct __riscv_v_regset_state *regset_data; + size_t regset_size; + struct iovec iov; + int status; + int ret; + + /* attach */ + + ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL)); + ASSERT_EQ(pid, waitpid(pid, &status, 0)); + ASSERT_TRUE(WIFSTOPPED(status)); + + /* unlock */ + + ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0)); + + /* resume and wait for the 1st c.ebreak */ + + ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL)); + ASSERT_EQ(pid, waitpid(pid, &status, 0)); + ASSERT_TRUE(WIFSTOPPED(status)); + + /* read tracee vector csr regs using ptrace GETREGSET */ + + regset_size =3D sizeof(*regset_data) + vlenb * 32; + regset_data =3D calloc(1, regset_size); + + iov.iov_base =3D regset_data; + iov.iov_len =3D regset_size; + + ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, &iov)); + + /* verify initial vsetvli x0, x0, e8, m8, tu, mu settings */ + + EXPECT_EQ(vlenb, regset_data->vlenb); + EXPECT_EQ(0UL, regset_data->vstart); + EXPECT_EQ(3UL, regset_data->vtype); + EXPECT_EQ(0UL, regset_data->vcsr); + EXPECT_EQ(0UL, regset_data->vl); + + /* apply invalid settings from fixture variants */ + + regset_data->vlenb *=3D variant->vlenb_mul; + regset_data->vstart =3D variant->vstart; + regset_data->vtype =3D variant->vtype; + regset_data->vcsr =3D variant->vcsr; + regset_data->vl =3D variant->vl; + + iov.iov_base =3D regset_data; + iov.iov_len =3D regset_size; + + errno =3D 0; + ret =3D ptrace(PTRACE_SETREGSET, pid, NT_RISCV_VECTOR, &iov); + ASSERT_EQ(errno, EINVAL); + ASSERT_EQ(ret, -1); + + /* cleanup */ + + ASSERT_EQ(0, kill(pid, SIGKILL)); + } +} + TEST_HARNESS_MAIN --=20 2.51.0