From nobody Sun Feb 8 12:43:03 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010032.outbound.protection.outlook.com [52.101.84.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71A752F0696 for ; Fri, 24 Oct 2025 20:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.32 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337330; cv=fail; b=nv7WoOwxzyGK1SRt+/C3fblaEIDmOVUkiX9HMi0Zi3i/IwMuX28T7v1wo7JHiM1JQVY0z551p8tq4de3A2kzBHtb1QInIkruBnPUUPfIi90fRDlE5lW/DaoxKLFy5VhlwyaLqrWSXnImrfsVsTSM0OP2XjYpLDnR4xJKTpD1voE= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337330; c=relaxed/simple; bh=oHyUVYxM/zdC31T++ZuXamAxqFK30rB0zsl993hRi2M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Oz1d4JyZfJJCQYSigglliiiTmKLSoT1QUlGJnA0r9gs/nztzwJrUHG2HLbBb64I/FJmjlDpp19mFttOHiKDemmiXIk5lrBhZtzI0tYnuvY0jWyz6PbQazDG4DogW3d1qgB22ftLyAR7c6OWFEryQsLfR3QogBFOjbqFv6jb8fjk= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=m2jVA9pl; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=m2jVA9pl; arc=fail smtp.client-ip=52.101.84.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="m2jVA9pl"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="m2jVA9pl" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=Cw/bvsLKZ+lDWYW6ZhagmMP/fBYEd4SySgtwli2jWyB0r5f9Txo2tGwXURMqXlDl0Tddtph1F7fwJXfPQJ7zr6LgZlgYEoW86rIQcv6Jr9qAwImUzYQMl9ebFBo5b6VcX0u1nOilsug18gNLL7uYOuQ/BdcGI6L/zn9+p7THWS+ILgmK9W7vH/ExP30L/IgE34RnAAmbEbI3Ij0vscmdQBw8DoMXuYMhPMqoggpTkdKIGpIvi8REYcGyrhnaER/ZqEB70jNOdL6h3NWBKuHMTPvzz/ipYOHprhOupZIZO0hCUyBqxKtbN7/BUlNEuLCJZFWjP8QpQ0GyDtD++EdPzQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hYfs/O49/TcoUU/EuXXUYCayxvFNFP1959nYcP1jho8=; b=BZzJGepU3Aia/FXjrOJ1gibjWlBxceioxDJad8ZJSNVfId75uV83SDXbLuGrq4Lz0AwJc/TpY+LsUYjyqMrBe7791UPTVqU+U69+/LwV8gy1qCTznuDACMvOmyESJBGlraN7eWIQFtF4cqWrIsJQOGnk7vS8DvZPjXpWPrIJElTEKX8kV1wBbA0kzN+7POx7lIdy0vxmRVjzT4D0nUwC9I6s9dUvvlvc98lmoUQCY4DCPoDu4gYF8ptsb1VKSuLRyMNr8L4LUgtq+JJJ4iESdRyY6G9vdowfIGE0ok0vVieMBrwXbDt9E3BkekSpUNv/H6B0NiDE6eJyEkh2GGxcfA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hYfs/O49/TcoUU/EuXXUYCayxvFNFP1959nYcP1jho8=; b=m2jVA9plRQzvzdNbHA5drtg5eC8dQ44FxsKGxAvOVJ0u1MsAETDMNoNQlKSkq7v9ZDatOFMbuCO5y4HI+XIN2wcqrIQDAhu5VZoq20vNCt7TFMlGzITjkkBlWHZZ5iHls33YlWzNNJfWlZ2RxVcY+P0Y0L1n02SEzv6OTPmltVk= Received: from AM9P195CA0011.EURP195.PROD.OUTLOOK.COM (2603:10a6:20b:21f::16) by AM8PR08MB5668.eurprd08.prod.outlook.com (2603:10a6:20b:1d0::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:03 +0000 Received: from AM4PEPF00027A60.eurprd04.prod.outlook.com (2603:10a6:20b:21f:cafe::fb) by AM9P195CA0011.outlook.office365.com (2603:10a6:20b:21f::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9228.16 via Frontend Transport; Fri, 24 Oct 2025 20:22:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AM4PEPF00027A60.mail.protection.outlook.com (10.167.16.68) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:02 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wiLhF5jhNX37qw/BugfvDsMz7vkjqNvdV+jP+wSDiYnY7A0k1djHlq7hAAhpRZ6qe4RbOfVWKsI9uBHHR0HDGXU0Evg0el02l0A/unalez05vD+/g3UaYTBa7r8IaU7iAwqB32qDD4a2lck8lpHzeyaraQGT70typcgldzgj2EoNV9+5jbiJzH1XCBQttvm02tH0ImcIwnS6gFHsK4zJ3bgroeTsVTxzxxIh9TI7AxlH+eRp9zgsjUbR3CSHcrIhM6EvddIBY1HeOyZ5lKvNi0OPgscQCoXPIVAjUlOsfvDc1XJCIf/Gh+jbgfSHF0TWo2JxeY/+Ru9531BMBcPjOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hYfs/O49/TcoUU/EuXXUYCayxvFNFP1959nYcP1jho8=; b=vV80Jrru2dVh9LuQw/aORBWhlwtKToIFRol2Vvm4RxZTucGaNqtPy4YY1GqYwLBltRoKD7D0Md1CwyRmD6/rLDURbVEqzDlprQQKbrjeYSGqKV3HRu+pBtC+6+ORFb1fi9f/3aFcLjHhjwpCmJKfoHiPU/lk1Vs0uQFRIBfXMK72zr31N1v9X42moq3yw+IYEqo7It5fRxISqVl+AMET2ztr39HCCo8iGD9M6+f5p5NbH1EM0/J+eAbkP1eEYkRMzbOduDN5TthdL2wyMrtGEmuzyhvJISWDPv0w/uIkAbgXk/pLmu6zAzGWD6mSX/Kdphkkd6UoVrqIzsjAqU+s2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hYfs/O49/TcoUU/EuXXUYCayxvFNFP1959nYcP1jho8=; b=m2jVA9plRQzvzdNbHA5drtg5eC8dQ44FxsKGxAvOVJ0u1MsAETDMNoNQlKSkq7v9ZDatOFMbuCO5y4HI+XIN2wcqrIQDAhu5VZoq20vNCt7TFMlGzITjkkBlWHZZ5iHls33YlWzNNJfWlZ2RxVcY+P0Y0L1n02SEzv6OTPmltVk= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:26 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:26 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] drm/panthor: Add arch-specific panthor_hw binding Date: Fri, 24 Oct 2025 21:21:10 +0100 Message-ID: <20251024202117.3241292-2-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P265CA0205.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:318::19) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|AM4PEPF00027A60:EE_|AM8PR08MB5668:EE_ X-MS-Office365-Filtering-Correlation-Id: 444b045f-38a4-49a8-2e0b-08de133afe20 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?NyEKApwqQ3TRCyC63l91AI49Igom6rkaNmd+2amylim6h36o4Xfa/B0XM1Nn?= =?us-ascii?Q?TRuIEZOqXpuxHm3CjcBkNE0tW8i8rcw6LCRe2B41e3InIIn9RqRLSstb/627?= =?us-ascii?Q?TjEwPmGrR2b8k/0XOM3Yvmp3QKEZSM81xc+rqslLqtaNZXw5NCQiabP8yBZL?= =?us-ascii?Q?Me3z0hsTM1kX8zc4F7vRyyPTpN6L4aSy8viOdSzQ67xNGwPAYmqD+AlQJP5w?= =?us-ascii?Q?ZFMhja+SUdmNsqy4WQX81L/dJfLI2Ob9CR0dXdH+gkAynCVM9YagZGYBZeCW?= =?us-ascii?Q?Gnf5BwTNFqttZE/4Zq/QQm8iL6X03Qg0ReZ5VznuqjxPXzEFJ43iBt0hrEK7?= =?us-ascii?Q?Q+XAbxkai0+TUaNzTYxtiIvCXq/XSCc/7bsMLA0I0DkDzPy2JGNkDIXguk8w?= =?us-ascii?Q?pNYIIHrT1hLyk4HX3Ymm+1qF2jKrtRjplv2BAptJIuvZlXIE02yNh2/eO3CW?= =?us-ascii?Q?9D5FmPhxQtsqmpQvFjRTrghzv77CTiEtrs0EmOdYj8UjZBx4QNgbSDGrJ/vu?= =?us-ascii?Q?t6yiMBJU3dl2/z5YKy3LiTaLP0pHXOHZ5vZkJMQILgjKo15G9LxfeCuVl/ML?= =?us-ascii?Q?zLlMFTAI65FgO4veH7sp7hDLWg1szR9cIPr0+i9McSbYRB43bKoEeE8M6leY?= =?us-ascii?Q?pl+dBFhb4uDtcqzVyeMUq949n/tdalQbJ48rI+qkYg1hig2XGT30cyhmEFDH?= =?us-ascii?Q?IpPWGtPhSZpD8URPw9gvS3k2Xaw2ttcHZIY1MJmePfM2G/zqmHThBTqhpVmE?= =?us-ascii?Q?qRfoUNI3DbPlldhH+JxKCBWPPIw5PgZXHNsEdYhl+PB9HP/MaRW7E752+Ji6?= =?us-ascii?Q?1pLN3Ti9G2poyhEfVLU9hbYULBUd6V8ldnYonXZW2dr6W76/sWIgUduyxDnu?= =?us-ascii?Q?YVTthKX1lkb2lWGW6/9qq6VF/tf2KY6U3V8m/FYau/g7AsW4mWVVRs8k8b6o?= =?us-ascii?Q?HE8+HUIQgh9JXdIPTTTjocLlBntshYz1xUzA3CHRjzgqs+rI8btFQDJkhPro?= =?us-ascii?Q?p4qsMw6OaT4uN7DLtcSehCnEeuwtQs0iyYI3pqaDp6OpUdObEopznNthW7FF?= =?us-ascii?Q?YFvJgrFnEXa7llrWOYNL+/t+zF092K64H+x2EyP7C1sFWWC6gQp3ZkAF+GLE?= =?us-ascii?Q?hTAjYUbNglYewXdTQlcJnqCupNh5nNAEWYzK62feEZSjGL9Jt9ajXwRFjg0M?= =?us-ascii?Q?NRDMAc5CU5CogNk2V5rSasfErR88bNTjFWbC5/L4A6KNI9kX1gM1elc349yt?= =?us-ascii?Q?7bHlqHyICs6g5hT+79Kuq2W8MgoLRLAjLKA1UT3Id9xIduKT2/uFiHKTdIY+?= =?us-ascii?Q?pmbPRbQ84YNfaG5YzQN5Q8HQHMmFh+MCD0T9DwmevkYLyQ2Uo0Epb+alm4UB?= =?us-ascii?Q?x1NsqLjpiwJ8d0yoFNw9t7ANXaU/xkdN2dvliuQh3PeSQNYz3jcAsZ2d7ple?= =?us-ascii?Q?422WOlfXU53q4TNlXqd3yjD1fnjCLdYK?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM4PEPF00027A60.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 74599367-9b3b-4a7b-f459-08de133ae850 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|35042699022|14060799003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9ttw/ScdTP4Nas0HboqEDJj9F58CeJ3aF8OONQESS58DWfiARh2hKIQOWIdv?= =?us-ascii?Q?/5V2KCPCYDJVwMiztCGOKp1Ug5fg3VrUjo0o3AfUaPy8e3BDEzo6WUt8B85v?= =?us-ascii?Q?UczNQ64RDucylSJBZ2AvYvHwU8fOunttLQ9I2SUjqJd77w1O15Vtv8V36pcM?= =?us-ascii?Q?ciZAtRuesTerHyv9iEuZ/WtsBbwBvDMlrgCayV8hWMcxY/OpeIeEzbc9qA3H?= =?us-ascii?Q?KvRo7zwyUzgH5eq1/U9sCQ82SaDXlMHu1Hde3mrK4UqY7wrH1he0TLK9mrPr?= =?us-ascii?Q?d6EBD4u6Q5y2uHBDinZot891Ej89UPGladMhmR9BRBOnlz3MzuyDu5aF66I3?= =?us-ascii?Q?DiPsVmWEZ7aC8mE089LrlH+sdVxuYgCmJ0xUQC7dvuxD71CPdo8RfVCr2r/z?= =?us-ascii?Q?5tZ9SHcsLX+p7Kpm59w5URq5WvA36DvDk7j9VIFinQs9QjdVzUOJvsSUGP3U?= =?us-ascii?Q?SbGUALhy/o4dCjxAAGrC3PATQ/LwIQjqfDRWWsw+2MeUCka1py8vdh1lPaeX?= =?us-ascii?Q?cLBlzGYs6Iji9PgdJVSiVzGuv5cqLlVwy6m6dFCf9I1R50yheM+uMUcORh71?= =?us-ascii?Q?wtGxx+xGkf84hRHWTdIaokR730mZTvIwxN28PC2rYMMuOjZKY95i9aH++G6A?= =?us-ascii?Q?sDo8aV3a0/kn4q2ZUgiPik/KM/S2JOghME1Jitmlm9QZe7MGnWO943i1xz3c?= =?us-ascii?Q?Nm6vTU4gerbSPdSYf1Gez6LBhmaMlwO1osEdgyXOI8+ANDsIS9rizLkH52QO?= =?us-ascii?Q?kdGBbokPWTPDwCZPCpfw8uTIS1LM54yOaq38GCpCrTwEWyaBG3LR5zh5F/N6?= =?us-ascii?Q?ncYcLXYHtaYzFTaSzQQtqIVli0iuRFkJADwkHvRCpOwBXxCwkh2+J9SPXmqt?= =?us-ascii?Q?Ome8dCY84KNUNIzHdGEntwF43PMSiDzpSkdfno/zSJqHHcn9cLSgaTZkur7U?= =?us-ascii?Q?RZL6LR2HXZHHktzxaTy6PSzDm4tFMtTsw8nyRAa3egGImm1lKn2YnPsE3Owy?= =?us-ascii?Q?7dnQtWmpocqFWOSKXe6OpwrQcoh/HUr0Lx99UdcnTGOUt90o+rc2r3CzgT98?= =?us-ascii?Q?+rwJUVL7ah7+O+pc21lGwQ9XdWfVxI7XmdP9+4XvItd06mZCB0FVqNiVJ+tw?= =?us-ascii?Q?4UnkR0AKVVG9blyyYBISW4779hAeRR1lT+oRyEuUQ9s/LhWN+/qWoa4ZaF3D?= =?us-ascii?Q?/T/q50I7IQqaLsEG+wwDlq8vF//wGGoQvfw6vL0CQ40ua+vFSTAK14rg0cto?= =?us-ascii?Q?ssyI/hzwl7YqT4TMvkGOfC6KJHjl4arMA2CTQi6O00ZUrAglZJkFKv1sDU4L?= =?us-ascii?Q?j7PMjG/ESO9yhRUKVZS6skDj4vNkdw1woKKxGyE1OwzFLOPdZ2kbHYpE4JJo?= =?us-ascii?Q?nu37VhMuY00qkSDC9nGr1wKPxa2Wkf8Js43Uz//pdd/Kly+ey03H6xs9OPHH?= =?us-ascii?Q?9XT4jCP1B1fnnqhMD2bCN70rW9gWuQHd53QzgNI8XCWpT07HukghhZTSjxgF?= =?us-ascii?Q?BWtnPj8JRn9Ku9sMfRy6fhRxx6Spttakn06QHqcQsXxScC2YVgkiJ1pit9D1?= =?us-ascii?Q?+2+x4uOX46hqj7sEXK4=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(35042699022)(14060799003);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:02.4864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 444b045f-38a4-49a8-2e0b-08de133afe20 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A60.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5668 Content-Type: text/plain; charset="utf-8" This patch adds the framework for binding to a specific panthor_hw structure based on the architecture major value parsed from the GPU_ID register. This is in preparation of enabling architecture-specific behaviours based on GPU_ID. As such, it also splits the GPU_ID register read operation into its own helper function. This framework allows a single panthor_hw structure to be shared across multiple architectures should there be minimal changes between them via the arch_min and arch_max field of the panthor_hw_entry structure, instead of duplicating the structure across multiple architectures. Signed-off-by: Karunika Choo --- v2: * merged GPU_ID refactoring patch with the arch-specific panthor_hw binding patch (PATCH 01/10 and PATCH 02/10 in v1). --- drivers/gpu/drm/panthor/panthor_device.h | 4 ++ drivers/gpu/drm/panthor/panthor_hw.c | 65 +++++++++++++++++++++++- drivers/gpu/drm/panthor/panthor_hw.h | 6 +++ 3 files changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index a764111359d2..1457c1255f1f 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -26,6 +26,7 @@ struct panthor_device; struct panthor_gpu; struct panthor_group_pool; struct panthor_heap_pool; +struct panthor_hw; struct panthor_job; struct panthor_mmu; struct panthor_fw; @@ -122,6 +123,9 @@ struct panthor_device { /** @csif_info: Command stream interface information. */ struct drm_panthor_csif_info csif_info; + /** @hw: GPU-specific data. */ + struct panthor_hw *hw; + /** @gpu: GPU management data. */ struct panthor_gpu *gpu; diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 4f2858114e5e..b6e7401327c3 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -8,6 +8,28 @@ #define GPU_PROD_ID_MAKE(arch_major, prod_major) \ (((arch_major) << 24) | (prod_major)) +/** struct panthor_hw_entry - HW arch major to panthor_hw binding entry */ +struct panthor_hw_entry { + /** @arch_min: Minimum supported architecture major value (inclusive) */ + u8 arch_min; + + /** @arch_max: Maximum supported architecture major value (inclusive) */ + u8 arch_max; + + /** @hwdev: Pointer to panthor_hw structure */ + struct panthor_hw *hwdev; +}; + +static struct panthor_hw panthor_hw_arch_v10 =3D {}; + +static struct panthor_hw_entry panthor_hw_match[] =3D { + { + .arch_min =3D 10, + .arch_max =3D 13, + .hwdev =3D &panthor_hw_arch_v10, + }, +}; + static char *get_gpu_model_name(struct panthor_device *ptdev) { const u32 gpu_id =3D ptdev->gpu_info.gpu_id; @@ -62,7 +84,6 @@ static void panthor_gpu_info_init(struct panthor_device *= ptdev) { unsigned int i; - ptdev->gpu_info.gpu_id =3D gpu_read(ptdev, GPU_ID); ptdev->gpu_info.csf_id =3D gpu_read(ptdev, GPU_CSF_ID); ptdev->gpu_info.gpu_rev =3D gpu_read(ptdev, GPU_REVID); ptdev->gpu_info.core_features =3D gpu_read(ptdev, GPU_CORE_FEATURES); @@ -117,8 +138,50 @@ static void panthor_hw_info_init(struct panthor_device= *ptdev) ptdev->gpu_info.tiler_present); } +static int panthor_hw_bind_device(struct panthor_device *ptdev) +{ + struct panthor_hw *hdev =3D NULL; + const u32 arch_major =3D GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id); + int i =3D 0; + + for (i =3D 0; i < ARRAY_SIZE(panthor_hw_match); i++) { + struct panthor_hw_entry *entry =3D &panthor_hw_match[i]; + + if (arch_major >=3D entry->arch_min && arch_major <=3D entry->arch_max) { + hdev =3D entry->hwdev; + break; + } + } + + if (!hdev) + return -EOPNOTSUPP; + + ptdev->hw =3D hdev; + + return 0; +} + +static int panthor_hw_gpu_id_init(struct panthor_device *ptdev) +{ + ptdev->gpu_info.gpu_id =3D gpu_read(ptdev, GPU_ID); + if (!ptdev->gpu_info.gpu_id) + return -ENXIO; + + return 0; +} + int panthor_hw_init(struct panthor_device *ptdev) { + int ret =3D 0; + + ret =3D panthor_hw_gpu_id_init(ptdev); + if (ret) + return ret; + + ret =3D panthor_hw_bind_device(ptdev); + if (ret) + return ret; + panthor_hw_info_init(ptdev); return 0; diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor= /panthor_hw.h index 0af6acc6aa6a..39752de3e7ad 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.h +++ b/drivers/gpu/drm/panthor/panthor_hw.h @@ -6,6 +6,12 @@ struct panthor_device; +/** + * struct panthor_hw - GPU specific register mapping and functions + */ +struct panthor_hw { +}; + int panthor_hw_init(struct panthor_device *ptdev); #endif /* __PANTHOR_HW_H__ */ -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazon11011069.outbound.protection.outlook.com [40.107.130.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F11712F069E for ; Fri, 24 Oct 2025 20:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.130.69 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; cv=fail; b=b9HxAgH0ogwzcTf3SHZVpC74lvVNKf9rfsCDPCXKnt0JY5FWScA54DMuFmSs3KHQ3UVLNa/+MoeQtlpDkKJND7aoKVaFi2NQVJFZ+j9959c7AUK8Q/mYo2IFJBHScFAchHsjWhFBIiXlbTBrRUMjYSOtghqJacu6Otx0buH5SHo= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; c=relaxed/simple; bh=IYwNZFG8BsudB+EkFDfw/xxK8/mdEGndnjV23dAsrKw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Fke6466egRhVnSFdX+rzvF/iCYWuqNIzfUqfbU+N39yghBjhUOrQKA8s3lf57J8REJUXYn6djsgDatEozFj8WqrPPYIaIbUgRMGYivK/zBeKSkdUIeX268+LafhjTp9LYcbFHBTymJbWGeZPC3Ol9XTilCSDcWeybJqjX9hvYyY= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Dg+8qIYm; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Dg+8qIYm; arc=fail smtp.client-ip=40.107.130.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Dg+8qIYm"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Dg+8qIYm" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=X6Ob28R+faH/rlO+jtzap2BZIbVBP4ESZyOkGCSLoJEAydunWGVNptnyDUlYspn0Ms1Uwru9sP+qLFgDLrcgRWaviM6F5PmITgcW4YZ/KpYQPoqbI4n+XTVVGAmIHemgm6HXLQ3bp4qzph25Wi/8QvXuNRJNqciAP3ukgxWPYXaI9NJGOV7J1Guwy5WMAaCNVVaXVyMJHn0ugK6GAGG+lvI/zjh3RIbj+QuHXBBpVUisgdHTT1ajc6c2URiXLmiFTLOlqLsXUArItiHyimrkKCT9O0SuKlOuqQBIiyCETanPovE9N86rKiQuOUlTtcHAb4KBhknybvCsdDJgacBIIw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hNRNVo77zgNnztlSw16Enyd75GeV/yMVHigKmnYeuFA=; b=IqV6ocwpiCL1SjYlmqtRntkP3qVnJE+ZKXgCdsvCOUSA5SfY4wxPZR6sdoPFS2bxWTuRvUv94+si26VJqOwgWYLZvGjHKDiXh8kQFZx9NAm5W+gN/AYEsN4RluDbetQotLscNzuXgKBxGiVGw6w/sctoB5wnPK04SpqI1+QIVWJGJ85RRxBEKAZ9U0R/VyRXn3lc1ovS4vPKxTMDD7Vre9NuhcQxNHCkBNUslC1yWCixiclZ6y9qjI7vvqhXNKvGDqCyHZPMSI16DXI55OpgKqM6NmfP4R4kB8bepKzmWchCOjYTF7sx3qwBh10z1Ql9aOMxnKgtua9DhXBfJTyw3A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hNRNVo77zgNnztlSw16Enyd75GeV/yMVHigKmnYeuFA=; b=Dg+8qIYmXQfmq3BG8ws7xGfNSxSgcuHcknwDe6hh9PT2AWHTjIUmvyd823Tu0S9hDsyWij+nOKU+Kg4fPSjzEe15Vtc74qpM3oYzPEz3Mbd14gREy/CopbCBMZsSW/ANbAQ126ELcLF0/krHjHvMgiimE1KRs9SOqjWntmRNxx4= Received: from AS4P190CA0002.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:5de::11) by PAVPR08MB9403.eurprd08.prod.outlook.com (2603:10a6:102:300::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:01 +0000 Received: from AMS0EPF000001A1.eurprd05.prod.outlook.com (2603:10a6:20b:5de:cafe::70) by AS4P190CA0002.outlook.office365.com (2603:10a6:20b:5de::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.13 via Frontend Transport; Fri, 24 Oct 2025 20:21:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AMS0EPF000001A1.mail.protection.outlook.com (10.167.16.231) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:21:59 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gLhXlMpD9WieMt6aJwDdTYLg8DWU2J67G4oeGjt/0xiE98QvTDb4s5KqPuXFfGh0WlVeNbkPPpoFPIYcF8gptwm9f/yWx3sEDcTgcUmiCORmKjgObAwKllki/XIGWCgkg1oXG09sFB5CEnSb2uz6EoXsuKj1K4+DOtdaaPOkVVE9AYMsrIyNFDr8oJf4n8/j6q2BEYXlnJDSPCwBIsV9KwCqlq1DWFatNENOhVGPTSrgcALqsd7x1qv4r6SfCLJBKMu1EUpDoFDwxBeZ3J7JNopjRs26aejv3xA6EsyplPmAkRJKrSTgl821E08gMpX1d+omPGwI7fi7fESoYvhzIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hNRNVo77zgNnztlSw16Enyd75GeV/yMVHigKmnYeuFA=; b=uzbLcNR22uG8wq7+ZXpO4JDooy2hwUvh/hmsrHdb6qy6Bscxyr447Iu67tnUrmbIKUO5pVEXwjZgASNgtYaJWql3dmh9GQOW89mjoeILlVTsa+VnizjQFSUQOOpHrABSGOWFKYlip14PmBNvHjPT5GSH3D4wWVkAay5T7v0SiAgF4IMZds4tVCF7yoi/+VVCT3RIbJHbLExRziCCC/RVuzytevRY3Axk2Km/OD2Qb9x+PA/oHytRoIEi01HWL0gMfe9ujqLI3bVXYDi/eepoChhswuCK0hvsCIO2AErEpAqGdF1pc/8XNwlzqpsVPxNof1g2URRRnYINVur8EQK+CQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hNRNVo77zgNnztlSw16Enyd75GeV/yMVHigKmnYeuFA=; b=Dg+8qIYmXQfmq3BG8ws7xGfNSxSgcuHcknwDe6hh9PT2AWHTjIUmvyd823Tu0S9hDsyWij+nOKU+Kg4fPSjzEe15Vtc74qpM3oYzPEz3Mbd14gREy/CopbCBMZsSW/ANbAQ126ELcLF0/krHjHvMgiimE1KRs9SOqjWntmRNxx4= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:27 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:27 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] drm/panthor: Add architecture-specific function operations Date: Fri, 24 Oct 2025 21:21:11 +0100 Message-ID: <20251024202117.3241292-3-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO2P265CA0090.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::30) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|AMS0EPF000001A1:EE_|PAVPR08MB9403:EE_ X-MS-Office365-Filtering-Correlation-Id: e2a24dd6-d4ac-4396-8f35-08de133afca0 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?sns+7DQnd7Wv/MmaUarprWdlh/1u1DHx7PVHu8GMBIUqjBeAUEVykamLZ8aA?= =?us-ascii?Q?IUPIasrZhZyguBobvHMS1aoMEulBTxtFU6aYZB2y2qzxo/oKej+qFopl8psx?= =?us-ascii?Q?D6rkc0no85qh8jWNpScLnBG1riuUlEKunJza0X1Rqq7R0B4ALNAE9shun0uE?= =?us-ascii?Q?vcT4G+yBo7gKgw9d/EcfMf4K5WBourz0ufdccvfsz3bOBHUu6vEQnewZJp6P?= =?us-ascii?Q?fYjlsvUcyaFgVhdSV8cr27zhCPk3jFntkYQXomhTMgRSz2mQTfauRBtHLdw0?= =?us-ascii?Q?hOSLDvcBDhD+GucrwhsgN6oQZhxzAeeGFCxuF744gToSJzMAjJuWHyb3x6sf?= =?us-ascii?Q?etjmj6jE1csm/cR3VflYMyJ+dCeVYFebpmnFOxLxJA1ca/qEyeV+Cr6JWcIG?= =?us-ascii?Q?b6KflUPXnGov0mN9n/WnXOIzs2BJgbLftl60Z0dePdC3YXTMYQPzDupq57Nz?= =?us-ascii?Q?6wo3k5kLeoq9U75nyWR6+IzQC5lt7gZD5ywGgO4nP0lgiJ1/MhGpYO2o0cCg?= =?us-ascii?Q?pjMvZWk18GM6C2Rqdxv7HZlK62EryyipoyUMAnfUeaTZdZ/AJbJrPMedlzGH?= =?us-ascii?Q?Hej8+rTV262HyZm+GoVPKZdfeO6nURxtzrqOnXQdBtxYqRhFfEl0jtjXYcwT?= =?us-ascii?Q?isav+tu5RJqxJ3KMMRh+w4M3W9xr1aj43vBf2EmP7CQd2Gr/FytjMKRTW7WC?= =?us-ascii?Q?sFKvtWREAXScX2pPRcd4jRAjXcS80L/BhBHsbbcj5W2tgphYc1lpZySVlGvE?= =?us-ascii?Q?PtLWQ+OkUw6OKVVB5KbC96gdqasPoCTGg4GqtgflZkomxdRVj6NqWthJDa6B?= =?us-ascii?Q?3AphuqgQ4gjKwf+GAv8Vy7aWqSYGHyeDtrDiPYGko1fDgDX++2759lWV+6/z?= =?us-ascii?Q?LpkSrFjvxlCHVphwv3X1HULzJv2N77DzQ6uwp34ihdeGgQcJ8J/+Y4S4VjBj?= =?us-ascii?Q?Z79g4OKHBndMzlu2duP4jFkAilU6bV/W57wMB8ngR9s/GzQnnUBidkkGSssC?= =?us-ascii?Q?ToGRt+6LuXZ07roMv0jpZmaR4RSWy/gamjKBPrI0g5HbI3RiVbYybyrBbfN5?= =?us-ascii?Q?LWOXWCt0pxrF0i5g474i4s2EjWn7BwOgY6wh8tRvoxWtrHcNssiR+6ScNoMR?= =?us-ascii?Q?e4efO9FrkaQFAEN9eiknsVvmx3iktKGEYWd0mXhNoMAFY55PNnXHb7c2dHFM?= =?us-ascii?Q?H8XlRwxiWduuFllcV42/choWTZjUv4LbjPougu2xvg2oxmxvUfIZ6HS2nlOn?= =?us-ascii?Q?v1zM5p/rW3kINXxZOPurY0I4hdmHXdtaMhIM8vJ3OktdJHm9kuj1x0p4K+wq?= =?us-ascii?Q?n4AHBqGpFJB/uxEJesMJ/eWnCMFgbqo6L9nNDNtgQkE4B20kikXn89UmfcKg?= =?us-ascii?Q?TgihyV64Z7WmGH4kwZ5F4khdAtoiHfv8fPpXkFHFbOnE4KJSlfOm2RgpOXTM?= =?us-ascii?Q?BQ/KyV8Hvz9DvJQ+SkdBj9aybqk2PunU?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS0EPF000001A1.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 67c0ba07-b18d-47d1-8159-08de133ae922 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|35042699022|1800799024|14060799003|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?oFGyF+fzOWhKHJIvDrANQJqcrlZlZa0pIYtPXBDPgW0GkxE+kP4HHbwcRZfi?= =?us-ascii?Q?7mhns6JdUHlpoSJhOz8cB/GnWAbSD3h15HRSui8Jqw97X/18rYSBUFaE2Mka?= =?us-ascii?Q?2rhlGpQZfH5+AqIBV1oGIx3jqezJEZq0mo8mGeoO1b1PX1nbyokPoXzx9446?= =?us-ascii?Q?3nMGh2mrKPmWRBPgmFs1U/KeM4AiRiH11dlHatixRgrV+m/REByIS4Nj4JxE?= =?us-ascii?Q?gUtv4+Q/r280QDEjIANc1ChO8QkfrXBy+BYHBC4HWnGREuJ6eE/hDRIYEqBM?= =?us-ascii?Q?MW6NjRkrQkLde55NgNASD6d2uxR7ZeWDo174lbsLlK8UiB9hQeFhXkoYom+U?= =?us-ascii?Q?c3lC2X2uU1a812nqalaBBz+GZ1F3KeFo69g37DISME0zgbjOQGkAhNS8eJV0?= =?us-ascii?Q?KBeFhbUQq+UKCo66o2LGW2Hn+4tmj5yqHfjuuYYlHg0GPbv7sAdqwF4UFEtq?= =?us-ascii?Q?NvO35QSIMMR4uoqtJXJrT6z+cEUO7TCArkHACTbO6Lk6CeczfP1loGKarOGj?= =?us-ascii?Q?D8KTAGFdXclAHOaFTZnRLbSydQSE+qgJ3f6A56g/eZGvt/W/5EvsLmD5nM7e?= =?us-ascii?Q?GeTq3py85zxVfhNv//FbXqusiV/Su5CyhGlZDOHidOdwORHwSruy7sqa/NnV?= =?us-ascii?Q?3+xzumyB/H5tnRyH2kLmvQqZmaXk+mP9VFYQ4I9BxVpAX0U6OVi5X4r13a5P?= =?us-ascii?Q?8BjeQQQNqqXDX23dZo1E4SdoM+rqPUiQ9SXVyZvNl4mi7O2RWuLRsVyBTyGc?= =?us-ascii?Q?XWYqTlFuDMBMbayYMwAfniL/N2FWCI8WHmLN8ZGeeErbcDy7NFGWLXeNneVS?= =?us-ascii?Q?K+6MYrIH+KiLmrK2cnop1u/bF2VQsOJI6X8VkxcJ0NwBWjZdXdYx2X1o5TXI?= =?us-ascii?Q?1268hk07Kw+JgumdBzH354zLpsh1h5Zgj3/dbXQnLzNl1pGXQfvSWXLujk1F?= =?us-ascii?Q?uWYFQBxq8JSYC0aUDzXlJO4SIkEGQj5OzlVCoq4M8taslJxFl+D+/ZMi0UEK?= =?us-ascii?Q?bzY2N1D5NscrjaWJzBElBPYOrqEQmLYrtQnxPQDsbH5EFOiSJtftdjqlCcqF?= =?us-ascii?Q?b0dBZATynxIlyF+JHB+y/1RDt9rxVAW2hBIIfTwZdr7PCGYSe3DxS8xs5oyU?= =?us-ascii?Q?sneZdY2FZyFpE8+0BteeRJ4iEOTCE1R3WnlgDx4427j3ND/IHO2i/VrjwQVC?= =?us-ascii?Q?cUgkdbUAOcnevzVK/HlFfRMjXg9ME93ruh0flReDY0rJkVqQkWTuo3gFJQUk?= =?us-ascii?Q?fPSCSOlvxjqpZsoy1JlubcSmWwdiE6g8SBlVVh9TF9Hnn1qkzQ607NfqPd36?= =?us-ascii?Q?7JJpwBx0wbv8MAbJFN5zcaKbU0oIeKLUvhnaQUuaJlzSbKwDUUrULkoc3D4Z?= =?us-ascii?Q?ne3HG3KX4Qjge1MmYATkvCLCIZwybw+A7sOCKzU3NpPkp5lM+YEkkI4sySpX?= =?us-ascii?Q?Z3aeXu5As7RXal3CMONIhGxaS/hk3EP59rrA47NhV8Mku3iC5ZgXiZCRcwB9?= =?us-ascii?Q?vAmuzUmlSURs1YZmrsnAOLJDqA+WaQO02O/Xguc/tQL9/IhhcuxrrnYMywco?= =?us-ascii?Q?nMoFKT1HnfN/x5Qgg+Y=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(35042699022)(1800799024)(14060799003)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:21:59.9569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2a24dd6-d4ac-4396-8f35-08de133afca0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A1.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9403 Content-Type: text/plain; charset="utf-8" Introduce architecture-specific function pointers to support architecture-dependent behaviours. This patch adds the following function pointers and updates their usage accordingly: - soft_reset - l2_power_on - l2_power_off Signed-off-by: Karunika Choo --- v2: * Updated includes for panthor_hw.h to allow static inline function pointer accessor functions instead of MACROs. * updated l2_power_off function signature to void instead of returning int as we have no way of handling a failure in this case. --- drivers/gpu/drm/panthor/panthor_device.c | 5 ++--- drivers/gpu/drm/panthor/panthor_device.h | 18 +++++++++++++++++- drivers/gpu/drm/panthor/panthor_fw.c | 4 ++-- drivers/gpu/drm/panthor/panthor_gpu.c | 11 ++++++++--- drivers/gpu/drm/panthor/panthor_gpu.h | 1 + drivers/gpu/drm/panthor/panthor_hw.c | 10 ++++++++-- drivers/gpu/drm/panthor/panthor_hw.h | 18 ++++++++++++++++++ 7 files changed, 56 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/pan= thor/panthor_device.c index 81df49880bd8..224a9237a2cc 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -18,7 +18,6 @@ #include "panthor_device.h" #include "panthor_fw.h" #include "panthor_gpu.h" -#include "panthor_hw.h" #include "panthor_mmu.h" #include "panthor_regs.h" #include "panthor_sched.h" @@ -141,8 +140,8 @@ static void panthor_device_reset_work(struct work_struc= t *work) panthor_sched_pre_reset(ptdev); panthor_fw_pre_reset(ptdev, true); panthor_mmu_pre_reset(ptdev); - panthor_gpu_soft_reset(ptdev); - panthor_gpu_l2_power_on(ptdev); + panthor_device_soft_reset(ptdev); + panthor_device_l2_power_on(ptdev); panthor_mmu_post_reset(ptdev); ret =3D panthor_fw_post_reset(ptdev); atomic_set(&ptdev->reset.pending, 0); diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 1457c1255f1f..2026cc6532ce 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -20,13 +20,14 @@ #include #include +#include "panthor_hw.h" + struct panthor_csf; struct panthor_csf_ctx; struct panthor_device; struct panthor_gpu; struct panthor_group_pool; struct panthor_heap_pool; -struct panthor_hw; struct panthor_job; struct panthor_mmu; struct panthor_fw; @@ -532,4 +533,19 @@ static inline u64 gpu_read64_counter(struct panthor_de= vice *ptdev, u32 reg) read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ false, dev, reg) +static inline int panthor_device_soft_reset(struct panthor_device *ptdev) +{ + return ptdev->hw->ops.soft_reset(ptdev); +} + +static inline int panthor_device_l2_power_on(struct panthor_device *ptdev) +{ + return ptdev->hw->ops.l2_power_on(ptdev); +} + +static inline void panthor_device_l2_power_off(struct panthor_device *ptde= v) +{ + ptdev->hw->ops.l2_power_off(ptdev); +} + #endif diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 9bf06e55eaee..6b91c3cb6678 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -1184,7 +1184,7 @@ void panthor_fw_unplug(struct panthor_device *ptdev) ptdev->fw->vm =3D NULL; if (!IS_ENABLED(CONFIG_PM) || pm_runtime_active(ptdev->base.dev)) - panthor_gpu_power_off(ptdev, L2, ptdev->gpu_info.l2_present, 20000); + panthor_device_l2_power_off(ptdev); } /** @@ -1363,7 +1363,7 @@ int panthor_fw_init(struct panthor_device *ptdev) return ret; } - ret =3D panthor_gpu_l2_power_on(ptdev); + ret =3D panthor_device_l2_power_on(ptdev); if (ret) return ret; diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index db69449a5be0..f6181462047f 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -218,6 +218,11 @@ int panthor_gpu_block_power_on(struct panthor_device *= ptdev, return 0; } +void panthor_gpu_l2_power_off(struct panthor_device *ptdev) +{ + panthor_gpu_power_off(ptdev, L2, ptdev->gpu_info.l2_present, 20000); +} + /** * panthor_gpu_l2_power_on() - Power-on the L2-cache * @ptdev: Device. @@ -344,9 +349,9 @@ void panthor_gpu_suspend(struct panthor_device *ptdev) { /* On a fast reset, simply power down the L2. */ if (!ptdev->reset.fast) - panthor_gpu_soft_reset(ptdev); + panthor_device_soft_reset(ptdev); else - panthor_gpu_power_off(ptdev, L2, 1, 20000); + panthor_device_l2_power_off(ptdev); panthor_gpu_irq_suspend(&ptdev->gpu->irq); } @@ -361,6 +366,6 @@ void panthor_gpu_suspend(struct panthor_device *ptdev) void panthor_gpu_resume(struct panthor_device *ptdev) { panthor_gpu_irq_resume(&ptdev->gpu->irq, GPU_INTERRUPTS_MASK); - panthor_gpu_l2_power_on(ptdev); + panthor_device_l2_power_on(ptdev); } diff --git a/drivers/gpu/drm/panthor/panthor_gpu.h b/drivers/gpu/drm/pantho= r/panthor_gpu.h index 7c17a8c06858..12e66f48ced1 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.h +++ b/drivers/gpu/drm/panthor/panthor_gpu.h @@ -46,6 +46,7 @@ int panthor_gpu_block_power_off(struct panthor_device *pt= dev, type ## _PWRTRANS, \ mask, timeout_us) +void panthor_gpu_l2_power_off(struct panthor_device *ptdev); int panthor_gpu_l2_power_on(struct panthor_device *ptdev); int panthor_gpu_flush_caches(struct panthor_device *ptdev, u32 l2, u32 lsc, u32 other); diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index b6e7401327c3..092962db5ccd 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -2,7 +2,7 @@ /* Copyright 2025 ARM Limited. All rights reserved. */ #include "panthor_device.h" -#include "panthor_hw.h" +#include "panthor_gpu.h" #include "panthor_regs.h" #define GPU_PROD_ID_MAKE(arch_major, prod_major) \ @@ -20,7 +20,13 @@ struct panthor_hw_entry { struct panthor_hw *hwdev; }; -static struct panthor_hw panthor_hw_arch_v10 =3D {}; +static struct panthor_hw panthor_hw_arch_v10 =3D { + .ops =3D { + .soft_reset =3D panthor_gpu_soft_reset, + .l2_power_off =3D panthor_gpu_l2_power_off, + .l2_power_on =3D panthor_gpu_l2_power_on, + }, +}; static struct panthor_hw_entry panthor_hw_match[] =3D { { diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor= /panthor_hw.h index 39752de3e7ad..2665d6dde2e3 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.h +++ b/drivers/gpu/drm/panthor/panthor_hw.h @@ -6,10 +6,28 @@ struct panthor_device; +/** + * struct panthor_hw_ops - HW operations that are specific to a GPU + */ +struct panthor_hw_ops { + /** @soft_reset: Soft reset function pointer */ + int (*soft_reset)(struct panthor_device *ptdev); + + /** @l2_power_off: L2 power off function pointer */ + void (*l2_power_off)(struct panthor_device *ptdev); + + /** @l2_power_on: L2 power on function pointer */ + int (*l2_power_on)(struct panthor_device *ptdev); +}; + /** * struct panthor_hw - GPU specific register mapping and functions */ struct panthor_hw { + /** @features: Bitmap containing panthor_hw_feature */ + + /** @ops: Panthor HW specific operations */ + struct panthor_hw_ops ops; }; int panthor_hw_init(struct panthor_device *ptdev); -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from AM0PR02CU008.outbound.protection.outlook.com (mail-westeuropeazon11013051.outbound.protection.outlook.com [52.101.72.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E63E2EFDA1 for ; Fri, 24 Oct 2025 20:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.72.51 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337332; cv=fail; b=aTmjLYRPBt2/EapyuuIxR5FWszQ+wR9KNt47SN5nqfi0NnZLjswQSNxc14nGpiU4tc6PdumOx9g7m3gCxQkURYxj6WCGp435NolStjLos+FhM2hZM3wsu6jKvE/Fuj2hANjYWMIDFalw3Wb6F2w8CmfDfX8df3snhzpZY3Dl+AM= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337332; c=relaxed/simple; bh=WXTbSCo0msSFh+HCNfZrGqHBIcDdSILEtrVMFUrpU9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=A97v0W4PSOhwFbFrZ0W70Wb+s3Hr0b6xTy7VsrqEpHRHMW5S8t7bSaPd+EvSUBujdoEU6klqlzIYreX0ddNa+yyvZthJhqYxPNCK08HdmyY7LG3b+uL3LVQDiohvmjOQ5xVWqIHBL9wi1G5bblqNl5CKRH7AhTAqnd65d8/0FuY= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=IuJTuQs7; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=IuJTuQs7; arc=fail smtp.client-ip=52.101.72.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="IuJTuQs7"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="IuJTuQs7" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=DRkhNlkTK0huU6WvraVZ2y8nXX9TmAVCqGr4KeGIESGzY1pRwcZDeBEBaDc60r+CqARjZ6TFe/s2up5t1dzZl5LWcHwsdKB9qnPF3RAm2TQUyJ0clX6r6N+zF1iBjhDj8xeVl1/QFnWGNeJEjEoqxJXgwQBkklAa7erFNR/GE6z3ImfzrI9VxzTUW2JI6OxnBpW7OIvCRM8MhsPj+jZd8WoucrVLQ23su1dVmyM6+VQQJJlRQoQmSuJki2AyXPz/i1f0uogZQ1DN2LtsZg4eqk0qIZNUlZh+qE4w6l7l12BBzhzLmieoSJImRfCu3GkzH8nF1CPKeNPX2pj4ix7BlQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xrcu/Zz0xLClOrjpqGRDoaqCM0hdsVg+84FKO2BmStA=; b=mq2jJ6EQ/Ni/WIZpUt8+XFln6ZIPEuc/G6BDcxBONXCTiQeZYwAPoxVj9cQlb26BU3ABPz5BjfYQPEuUHGA/wGnu7JWeDTKmO2IdFX8gpXBoZZv3qeWMyTwfk7EaBnOlUitWfaVkTYpt+fGJkWsAxwEISNWmkxaMHc1enEqA1EzNqn410e+8lvcmwG/xARc8wmw8AyvwvqgpfzhjEd/JC6JZSj/L6YQiTZ6Ckb2AsnXvI+vsknaBshyZbMuOZGv0Sp3iPlhlrH+2vTyDMmuLEbbJfEuNbQx/Y2nRYUsxidRkj8sFpvszJBx+EfqZ8lS7vfNiFGww2DoFtXp5tMzK1w== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Xrcu/Zz0xLClOrjpqGRDoaqCM0hdsVg+84FKO2BmStA=; b=IuJTuQs73OfQPLwqPNwkKlwGqPvwDnO/qGlPN2Pu7LUJ/YWZFjzmirw74r3GoAst9tEPHPUb+7AnVJ2wCZjQRFkETzsgW/iVHv+IeXl6ql3f8meyID7SYwTyz4hq7lJJ7O+Mt/WBxzQufMBMpP998Cu32WJf2REf4cR6ZeR5iy0= Received: from DB9PR06CA0022.eurprd06.prod.outlook.com (2603:10a6:10:1db::27) by DU0PR08MB8278.eurprd08.prod.outlook.com (2603:10a6:10:40e::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:03 +0000 Received: from DB1PEPF000509F2.eurprd02.prod.outlook.com (2603:10a6:10:1db:cafe::72) by DB9PR06CA0022.outlook.office365.com (2603:10a6:10:1db::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.13 via Frontend Transport; Fri, 24 Oct 2025 20:22:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DB1PEPF000509F2.mail.protection.outlook.com (10.167.242.148) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:01 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iXwuZYvRRyiSKHsu+gAsbdWgmkqHtlk4N5rwAXb7yOAhvzOrEUFSX4/AkWgnLadY0TSB771tv11mkpImcXQTyj7foqwC+imSec7G1VDK+jNfyzf/RY5amX1WS8bhxvrselVowQWcgo4yzucAXQFxmSaEwS5Z7f9gqufcvn1M0qgWZGU7ozplc9KU84B7rZD6RWdSaVwlFRgANTs7h/iSDRPa+sWM34ADpm6tQoK0rzIj6BcWELNY+7fAHRB3bf8ChqveEAvnJMCKrZueBanHlalAGund2g7AviySt7agnNqLBcdiVIhRL0iB1aWNlESVCDHpHV5ho3+pqjwJO6GJ6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xrcu/Zz0xLClOrjpqGRDoaqCM0hdsVg+84FKO2BmStA=; b=JvS+7F5Wqh4pQxhBQi4hso5FQ4OSNDxbHy6AZ9nX6iqWOzSCO4sAHV0MUZdlPlR6q65KTlTUoNlVY68oVIovsmHNundOVgVFzf1A6GAuxW++RtIlAv9WDLQQkUUcSAlkS8Veyt8E3w6YtKY0HeCGJrBKXrQhXmzfmLuc5EeGe7UU1pLfr0tBFdmjkjQPe/XmtKPvLo5rG0E7Up1ZzHh8DjhoouX1LsI1L+U40W9h/d2IqKv/S3s7WFQmupzdUQk5Ax5TvKudPxTC1ILxunxJulzskVEl4LuBR9SELbk41BzwBJCauf0UkAvTU2KfOEu/JNnxv21D4XXJFs7h/w2gwA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Xrcu/Zz0xLClOrjpqGRDoaqCM0hdsVg+84FKO2BmStA=; b=IuJTuQs73OfQPLwqPNwkKlwGqPvwDnO/qGlPN2Pu7LUJ/YWZFjzmirw74r3GoAst9tEPHPUb+7AnVJ2wCZjQRFkETzsgW/iVHv+IeXl6ql3f8meyID7SYwTyz4hq7lJJ7O+Mt/WBxzQufMBMpP998Cu32WJf2REf4cR6ZeR5iy0= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:29 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:29 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] drm/panthor: Introduce panthor_pwr API and power control framework Date: Fri, 24 Oct 2025 21:21:12 +0100 Message-ID: <20251024202117.3241292-4-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO2P123CA0064.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1::28) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|DB1PEPF000509F2:EE_|DU0PR08MB8278:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ae4a140-39d8-451f-8cb1-08de133afd62 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?JBcHp+2DtecD07zf17GWZ54kC/iMYIEXzZL7wYM6fRs2lt3JtVGq5ICi/gpl?= =?us-ascii?Q?mfCXupJBS2pKnoVBqNFHuYNNGPcxMY934fK+I+ywYeD0PAA/WQqZlVhSVtuU?= =?us-ascii?Q?+Xmm353iSyjRgrXSH0NNCqBbuEHJW7HiyZ3SZ8tyhS8GjUyzd+3Poxbn331w?= =?us-ascii?Q?jzg8BkvFUI4xkCIg1gvDa4lseCa2ZMlqWp6gABpQLmuPgPbQKZ9IphMdrFDj?= =?us-ascii?Q?qAnoMGZpUwau584nVpXblexH7U6R4Rxykb2Yv7YJnzx8PV+/iw8GHJt3zHEo?= =?us-ascii?Q?VYWnRahoy2+MPGLjgck5hoxq47tEfgjLcijpJt2PD0edhVSOdLuL9vQrT7Zw?= =?us-ascii?Q?AJJnWQMn4F/UCVPDGH/NZseMm4x3gtALrG0WfFdEnAAwXhxyeKd5Am+bpiJH?= =?us-ascii?Q?Om3met9UTbWGpFOQvxfb2Tlgpl8zdG4gJUWXXHEsbgKujRTWB1nm2gWwLugM?= =?us-ascii?Q?atC7l1k0iNGG/IbjtVWhpm8XuL65XbOVf45YiYvD87gR1Rl5HAfNM/7n7mrf?= =?us-ascii?Q?Y4AYhiHHSyWSkVEm7ln5MppfOzZiQoT4hT7zLp+nRCIl68NvtUGJz6AXGww6?= =?us-ascii?Q?os3CX18EuANt4m2YZSFAckbctVfN0p/orrrHso+oLcEWuIkAriWq7ZaG/qaF?= =?us-ascii?Q?PdvSb5dbxMJNZL1wS9Qa8tb14x/imxePvAtXSNv6d3l4a6vxrChpdBldOp1K?= =?us-ascii?Q?lNXTkDYZ3BYKLFLsB6ahfQAtAK+wVDUhJFtg4EywyrtHXNJXJADQzf1QwoQJ?= =?us-ascii?Q?Fjbik1/R+5OalMR8CTSzLSy4Z1EX8JXdp/8JE6NXqgZEM3u3jVF6EvEHfc99?= =?us-ascii?Q?AB483U2i4o/k8hfKAr+T5nYQkRglwyYokYs97GVPnduJKSYnZIIDwiym5Jk+?= =?us-ascii?Q?2KiksJIuML201VOwqOK+2FVE0FLw7kweZpfBfvepuegUWFPimiyucM75xSb0?= =?us-ascii?Q?6i3qqOFZyWQ5Z3c0HIef6miuknBK6ruRFV15sh7xJwFYR5hkBTN16ziPm2HH?= =?us-ascii?Q?/hMmrTTSABsjnhOsiS4PToodjrZOoG3E3T5DCgYIuWZvOeyTZ8V0sBgB6aoO?= =?us-ascii?Q?og4DguflzGuKLdQBQ1iDWleacfuzxt4qSuH4QOgxNZx4oZgv9LEGSDJXsnQp?= =?us-ascii?Q?mjFQAX/vy2gpBKtKijwDFBaINYHq5fwE9/udpa6hYwiaV1kl1e/j2TW9XGb3?= =?us-ascii?Q?sNlwjl6ijD5bD2dd3byne/zwRAEUykZNXjufrtmp7eMn6VaUnsNd4zSXqD68?= =?us-ascii?Q?zElscS5kkLFR23LT7kcNMs+vDcfGJ5M68PgcaO+a5ZnDVz2uvqGfqw43p45r?= =?us-ascii?Q?AKsjCVfW3Qu/+agFEACexzNnhIBEZnbRF5Gi/RZr+2P8EDH3eWBdCs5bEatO?= =?us-ascii?Q?YGbsNpcBYIz5N9sJNiiyBzq6HIPaW/x1wRKC7OKoBRIGmiKNdCwBdTkugnv9?= =?us-ascii?Q?Zmoy56uFjpNhiC0dsfo6fjSrRrL+qs6A?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB1PEPF000509F2.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: f4db883c-29e1-470e-03f2-08de133ae9f5 X-Microsoft-Antispam: BCL:0;ARA:13230040|14060799003|82310400026|376014|1800799024|35042699022|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8NxItV94WrdHLM/xmXFMod4ylw44PxPXHzAf2ZOVMDn/1ijByW37y8kTM8yt?= =?us-ascii?Q?5XepL3BjORs7jsv1/AFkPVcHl93LJeVZByt+NtJg3U6AhkJGN2eBy+CcZ3wN?= =?us-ascii?Q?SUQ9+QibscRgYIjxCbXzQND4rC4Mg3xGXwMc57DbkDmPhkDYMDMsaIfz+d6m?= =?us-ascii?Q?4xSsEzrhssuNmYsflaEbrRdX5CKUevMkMYTFK2wlpsyosC0WlGihcrEFVOjC?= =?us-ascii?Q?/HlVgLzMIwQ6lmkZUCZ3S5z4XL7F+PzV9UJ5/pHIVB9EraG2nuWLl9tPfNPB?= =?us-ascii?Q?KinGYMbbjFgvpc190VVoT5QLcu6Rw0//dkkYJXK/MzByBqE8PTQV4teLyEpP?= =?us-ascii?Q?Liu/blljxd9k62tJixJjKem7Vb/DnhtAbg2QdlykOjCCpSjvOXi7ypPR2sS6?= =?us-ascii?Q?7ExjBqApGZuipiBnR64PTnIoNLQfippWQK9NkXk5EC+K/eqREKlvLWZ8+K6i?= =?us-ascii?Q?6VaAiUZ1Ma0hzK3SpP2tifNYh1f81RD5dctCPkGvqGL1dLt9SJrY7whUxEh6?= =?us-ascii?Q?QKRLp+PRDcRghG08PirtiK2UJL8G1d0y5IDxmur4fw2FGpjxU47YQSmCgR0A?= =?us-ascii?Q?Ut+xlw5Mp6METOkhmGx5VCxeyVLUYRCAKrMIT4pAdHUvCQcdwSURBP4zAXKP?= =?us-ascii?Q?ayo/WsW0bnD8kVA8VxRQRPAHs31yfjpNTofp1e/oTM1q1vmIB/yx58HvCKj+?= =?us-ascii?Q?3bGupMyKyTJplS8fC1xxdhF/V6lotH+yX8k07293OTp/jUzgD3ACmdDL5xva?= =?us-ascii?Q?4KC4OiZCSF/7Z6KFTdP2q1LNwU3tFCItQKyYTGQc52VsY0wjQNEYLXOd6pMf?= =?us-ascii?Q?cFF/zgmXWZqqaxukGZdHlDIMrBuNVzmne/0RRp88mEZ43XEUsOYDtE9ak+nz?= =?us-ascii?Q?urneX6kO3ENCrw0WUh788LKuYoq979BZ8fVkeNBTQnSeHkJqrb4WMjN1F73P?= =?us-ascii?Q?u9Dihyr1ipsWDvUo3tYomP6C/B2PLWp/yzdao8bKR0ezJoDRUcb64olyeqH2?= =?us-ascii?Q?zOHqhMYtgbjPiXdVssIU7Kk4PvOHZ/twS5kf0L/n8qNHdVeTYmXGxE9rMMwd?= =?us-ascii?Q?RdFBXDR5pfFTSTT1mCUmHubA31Yi/fVMaJ/ijGPipirk2BygVPBglkSaA8Mh?= =?us-ascii?Q?DJ6Yx21kgFlzkUV//zIrC+NTNHH4nJX5/897+UtpmSYbNm/ImuefG/zghxHI?= =?us-ascii?Q?Cl7Y2ePEeqU6Gkbsh5xFsm6eEK3p1ecz67Dl55ooRoPvPl7/Swr4Y6KmXDJ1?= =?us-ascii?Q?cJ/pEf5QE61JcDI0sDRIoqNB3bnp/38sVUvs04Qib7x5Fe/1+xn0UgOkaA6v?= =?us-ascii?Q?85RM4EfX9tX1AljRp8iYXWDTZIZhId/anS6LKJxzLkmXl2JuCgbn9BAjm0Um?= =?us-ascii?Q?sp/jfp3q0gzuBzfC9NJkM6hqf4WaLW/fVCSrqM2oD/W/9DZcG1mWefqmjb9w?= =?us-ascii?Q?p368gvn4o6OuK9CvMyZ5YZcpGLBarYipd2m3+hl493GdTETMVwrr/mXcsrh0?= =?us-ascii?Q?9BsvMxJy/0XK95IHOdOUFwCE21+s/Tt2y7ixuSEQLgoJQtP7rjf7EWwzvpW7?= =?us-ascii?Q?lYFS0szWkOUQqrpsy48=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(14060799003)(82310400026)(376014)(1800799024)(35042699022)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:01.2189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ae4a140-39d8-451f-8cb1-08de133afd62 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509F2.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8278 Content-Type: text/plain; charset="utf-8" Add the new panthor_pwr module, which provides basic power control management for Mali-G1 GPUs. The initial implementation includes infrastructure for initializing the PWR_CONTROL block, requesting and handling its IRQ, and checking for PWR_CONTROL support based on GPU architecture. The patch also integrates panthor_pwr with the device lifecycle (init, suspend, resume, and unplug) through the new API functions. It also registers the IRQ handler under the 'gpu' IRQ as the PWR_CONTROL block is located within the GPU_CONTROL block. Signed-off-by: Karunika Choo --- v2: * Removed stub functions. * Updated BIT() definitions for 64-bit fields to use BIT_U64() to address kernel test robot warnings for 32-bit systems. * Moved GPU_FEATURES_RAY_TRAVERSAL definition to the next patch where it is being used. * Drop the use of feature bits in favour of a function that performs a GPU_ARCH_MAJOR check instead. --- drivers/gpu/drm/panthor/Makefile | 1 + drivers/gpu/drm/panthor/panthor_device.c | 14 ++- drivers/gpu/drm/panthor/panthor_device.h | 4 + drivers/gpu/drm/panthor/panthor_hw.c | 5 + drivers/gpu/drm/panthor/panthor_hw.h | 2 + drivers/gpu/drm/panthor/panthor_pwr.c | 120 +++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_pwr.h | 17 ++++ drivers/gpu/drm/panthor/panthor_regs.h | 78 +++++++++++++++ 8 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/panthor/panthor_pwr.c create mode 100644 drivers/gpu/drm/panthor/panthor_pwr.h diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Mak= efile index 02db21748c12..753a32c446df 100644 --- a/drivers/gpu/drm/panthor/Makefile +++ b/drivers/gpu/drm/panthor/Makefile @@ -10,6 +10,7 @@ panthor-y :=3D \ panthor_heap.o \ panthor_hw.o \ panthor_mmu.o \ + panthor_pwr.o \ panthor_sched.o obj-$(CONFIG_DRM_PANTHOR) +=3D panthor.o diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/pan= thor/panthor_device.c index 224a9237a2cc..9d2adcb5431d 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -19,6 +19,7 @@ #include "panthor_fw.h" #include "panthor_gpu.h" #include "panthor_mmu.h" +#include "panthor_pwr.h" #include "panthor_regs.h" #include "panthor_sched.h" @@ -101,6 +102,7 @@ void panthor_device_unplug(struct panthor_device *ptdev) panthor_fw_unplug(ptdev); panthor_mmu_unplug(ptdev); panthor_gpu_unplug(ptdev); + panthor_pwr_unplug(ptdev); pm_runtime_dont_use_autosuspend(ptdev->base.dev); pm_runtime_put_sync_suspend(ptdev->base.dev); @@ -248,10 +250,14 @@ int panthor_device_init(struct panthor_device *ptdev) if (ret) goto err_rpm_put; - ret =3D panthor_gpu_init(ptdev); + ret =3D panthor_pwr_init(ptdev); if (ret) goto err_rpm_put; + ret =3D panthor_gpu_init(ptdev); + if (ret) + goto err_unplug_pwr; + ret =3D panthor_gpu_coherency_init(ptdev); if (ret) goto err_unplug_gpu; @@ -292,6 +298,9 @@ int panthor_device_init(struct panthor_device *ptdev) err_unplug_gpu: panthor_gpu_unplug(ptdev); +err_unplug_pwr: + panthor_pwr_unplug(ptdev); + err_rpm_put: pm_runtime_put_sync_suspend(ptdev->base.dev); return ret; @@ -445,6 +454,7 @@ static int panthor_device_resume_hw_components(struct p= anthor_device *ptdev) { int ret; + panthor_pwr_resume(ptdev); panthor_gpu_resume(ptdev); panthor_mmu_resume(ptdev); @@ -454,6 +464,7 @@ static int panthor_device_resume_hw_components(struct p= anthor_device *ptdev) panthor_mmu_suspend(ptdev); panthor_gpu_suspend(ptdev); + panthor_pwr_suspend(ptdev); return ret; } @@ -567,6 +578,7 @@ int panthor_device_suspend(struct device *dev) panthor_fw_suspend(ptdev); panthor_mmu_suspend(ptdev); panthor_gpu_suspend(ptdev); + panthor_pwr_suspend(ptdev); drm_dev_exit(cookie); } diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 2026cc6532ce..3231c8154e60 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -32,6 +32,7 @@ struct panthor_job; struct panthor_mmu; struct panthor_fw; struct panthor_perfcnt; +struct panthor_pwr; struct panthor_vm; struct panthor_vm_pool; @@ -127,6 +128,9 @@ struct panthor_device { /** @hw: GPU-specific data. */ struct panthor_hw *hw; + /** @pwr: Power control management data. */ + struct panthor_pwr *pwr; + /** @gpu: GPU management data. */ struct panthor_gpu *gpu; diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 092962db5ccd..09aef34a6ce7 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -192,3 +192,8 @@ int panthor_hw_init(struct panthor_device *ptdev) return 0; } + +bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev) +{ + return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >=3D 14; +} diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor= /panthor_hw.h index 2665d6dde2e3..4c71f27d1c0b 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.h +++ b/drivers/gpu/drm/panthor/panthor_hw.h @@ -32,4 +32,6 @@ struct panthor_hw { int panthor_hw_init(struct panthor_device *ptdev); +bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev); + #endif /* __PANTHOR_HW_H__ */ diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/pantho= r/panthor_pwr.c new file mode 100644 index 000000000000..da64fe006a8b --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_pwr.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* Copyright 2025 ARM Limited. All rights reserved. */ + +#include +#include +#include +#include + +#include + +#include "panthor_device.h" +#include "panthor_hw.h" +#include "panthor_pwr.h" +#include "panthor_regs.h" + +#define PWR_INTERRUPTS_MASK \ + (PWR_IRQ_POWER_CHANGED_SINGLE | \ + PWR_IRQ_POWER_CHANGED_ALL | \ + PWR_IRQ_DELEGATION_CHANGED | \ + PWR_IRQ_RESET_COMPLETED | \ + PWR_IRQ_RETRACT_COMPLETED | \ + PWR_IRQ_INSPECT_COMPLETED | \ + PWR_IRQ_COMMAND_NOT_ALLOWED | \ + PWR_IRQ_COMMAND_INVALID) + +/** + * struct panthor_pwr - PWR_CONTROL block management data. + */ +struct panthor_pwr { + /** @irq: PWR irq. */ + struct panthor_irq irq; + + /** @reqs_lock: Lock protecting access to pending_reqs. */ + spinlock_t reqs_lock; + + /** @pending_reqs: Pending PWR requests. */ + u32 pending_reqs; + + /** @reqs_acked: PWR request wait queue. */ + wait_queue_head_t reqs_acked; +}; + +static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 stat= us) +{ + spin_lock(&ptdev->pwr->reqs_lock); + gpu_write(ptdev, PWR_INT_CLEAR, status); + + if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED)) + drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED"); + + if (unlikely(status & PWR_IRQ_COMMAND_INVALID)) + drm_err(&ptdev->base, "PWR_IRQ: COMMAND_INVALID"); + + if (status & ptdev->pwr->pending_reqs) { + ptdev->pwr->pending_reqs &=3D ~status; + wake_up_all(&ptdev->pwr->reqs_acked); + } + spin_unlock(&ptdev->pwr->reqs_lock); +} +PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler); + +void panthor_pwr_unplug(struct panthor_device *ptdev) +{ + unsigned long flags; + + if (!ptdev->pwr) + return; + + /* Make sure the IRQ handler is not running after that point. */ + panthor_pwr_irq_suspend(&ptdev->pwr->irq); + + /* Wake-up all waiters. */ + spin_lock_irqsave(&ptdev->pwr->reqs_lock, flags); + ptdev->pwr->pending_reqs =3D 0; + wake_up_all(&ptdev->pwr->reqs_acked); + spin_unlock_irqrestore(&ptdev->pwr->reqs_lock, flags); +} + +int panthor_pwr_init(struct panthor_device *ptdev) +{ + struct panthor_pwr *pwr; + int err, irq; + + if (!panthor_hw_has_pwr_ctrl(ptdev)) + return 0; + + pwr =3D drmm_kzalloc(&ptdev->base, sizeof(*pwr), GFP_KERNEL); + if (!pwr) + return -ENOMEM; + + spin_lock_init(&pwr->reqs_lock); + init_waitqueue_head(&pwr->reqs_acked); + ptdev->pwr =3D pwr; + + irq =3D platform_get_irq_byname(to_platform_device(ptdev->base.dev), "gpu= "); + if (irq < 0) + return irq; + + err =3D panthor_request_pwr_irq(ptdev, &pwr->irq, irq, PWR_INTERRUPTS_MAS= K); + if (err) + return err; + + return 0; +} + +void panthor_pwr_suspend(struct panthor_device *ptdev) +{ + if (!ptdev->pwr) + return; + + panthor_pwr_irq_suspend(&ptdev->pwr->irq); +} + +void panthor_pwr_resume(struct panthor_device *ptdev) +{ + if (!ptdev->pwr) + return; + + panthor_pwr_irq_resume(&ptdev->pwr->irq, PWR_INTERRUPTS_MASK); +} diff --git a/drivers/gpu/drm/panthor/panthor_pwr.h b/drivers/gpu/drm/pantho= r/panthor_pwr.h new file mode 100644 index 000000000000..b325e5b7eba3 --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_pwr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 or MIT */ +/* Copyright 2025 ARM Limited. All rights reserved. */ + +#ifndef __PANTHOR_PWR_H__ +#define __PANTHOR_PWR_H__ + +struct panthor_device; + +void panthor_pwr_unplug(struct panthor_device *ptdev); + +int panthor_pwr_init(struct panthor_device *ptdev); + +void panthor_pwr_suspend(struct panthor_device *ptdev); + +void panthor_pwr_resume(struct panthor_device *ptdev); + +#endif /* __PANTHOR_PWR_H__ */ diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panth= or/panthor_regs.h index 8bee76d01bf8..5469eec02178 100644 --- a/drivers/gpu/drm/panthor/panthor_regs.h +++ b/drivers/gpu/drm/panthor/panthor_regs.h @@ -205,4 +205,82 @@ #define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000)) #define CSF_GLB_DOORBELL_ID 0 +/* PWR Control registers */ + +#define PWR_CONTROL_BASE 0x800 +#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x)) + +#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0) +#define PWR_INT_CLEAR PWR_CTRL_REG(0x4) +#define PWR_INT_MASK PWR_CTRL_REG(0x8) +#define PWR_INT_STAT PWR_CTRL_REG(0xc) +#define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0) +#define PWR_IRQ_POWER_CHANGED_ALL BIT(1) +#define PWR_IRQ_DELEGATION_CHANGED BIT(2) +#define PWR_IRQ_RESET_COMPLETED BIT(3) +#define PWR_IRQ_RETRACT_COMPLETED BIT(4) +#define PWR_IRQ_INSPECT_COMPLETED BIT(5) +#define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30) +#define PWR_IRQ_COMMAND_INVALID BIT(31) + +#define PWR_STATUS PWR_CTRL_REG(0x20) +#define PWR_STATUS_ALLOW_L2 BIT_U64(0) +#define PWR_STATUS_ALLOW_TILER BIT_U64(1) +#define PWR_STATUS_ALLOW_SHADER BIT_U64(8) +#define PWR_STATUS_ALLOW_BASE BIT_U64(14) +#define PWR_STATUS_ALLOW_STACK BIT_U64(15) +#define PWR_STATUS_DOMAIN_ALLOWED(x) BIT_U64(x) +#define PWR_STATUS_DELEGATED_L2 BIT_U64(16) +#define PWR_STATUS_DELEGATED_TILER BIT_U64(17) +#define PWR_STATUS_DELEGATED_SHADER BIT_U64(24) +#define PWR_STATUS_DELEGATED_BASE BIT_U64(30) +#define PWR_STATUS_DELEGATED_STACK BIT_U64(31) +#define PWR_STATUS_DELEGATED_SHIFT 16 +#define PWR_STATUS_DOMAIN_DELEGATED(x) BIT_U64((x) + PWR_STATUS_DELEGAT= ED_SHIFT) +#define PWR_STATUS_ALLOW_SOFT_RESET BIT_U64(33) +#define PWR_STATUS_ALLOW_FAST_RESET BIT_U64(34) +#define PWR_STATUS_POWER_PENDING BIT_U64(41) +#define PWR_STATUS_RESET_PENDING BIT_U64(42) +#define PWR_STATUS_RETRACT_PENDING BIT_U64(43) +#define PWR_STATUS_INSPECT_PENDING BIT_U64(44) + +#define PWR_COMMAND PWR_CTRL_REG(0x28) +#define PWR_COMMAND_POWER_UP 0x10 +#define PWR_COMMAND_POWER_DOWN 0x11 +#define PWR_COMMAND_DELEGATE 0x20 +#define PWR_COMMAND_RETRACT 0x21 +#define PWR_COMMAND_RESET_SOFT 0x31 +#define PWR_COMMAND_RESET_FAST 0x32 +#define PWR_COMMAND_INSPECT 0xF0 +#define PWR_COMMAND_DOMAIN_L2 0 +#define PWR_COMMAND_DOMAIN_TILER 1 +#define PWR_COMMAND_DOMAIN_SHADER 8 +#define PWR_COMMAND_DOMAIN_BASE 14 +#define PWR_COMMAND_DOMAIN_STACK 15 +#define PWR_COMMAND_SUBDOMAIN_RTU BIT(0) +#define PWR_COMMAND_DEF(cmd, domain, subdomain) \ + (((subdomain) << 16) | ((domain) << 8) | (cmd)) + +#define PWR_CMDARG PWR_CTRL_REG(0x30) + +#define PWR_L2_PRESENT PWR_CTRL_REG(0x100) +#define PWR_L2_READY PWR_CTRL_REG(0x108) +#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110) +#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118) +#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140) +#define PWR_TILER_READY PWR_CTRL_REG(0x148) +#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150) +#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158) +#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200) +#define PWR_SHADER_READY PWR_CTRL_REG(0x208) +#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210) +#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218) +#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380) +#define PWR_BASE_READY PWR_CTRL_REG(0x388) +#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390) +#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398) +#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0) +#define PWR_STACK_READY PWR_CTRL_REG(0x3c8) +#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0) + #endif -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013027.outbound.protection.outlook.com [40.107.162.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0004C2F0C45 for ; Fri, 24 Oct 2025 20:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.162.27 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; cv=fail; b=cY7KT9Jin3j6FY+hsptKwmrc05EqJHcxOWtWqG1S5FnblyEV8HEx7IcHiwKU9VVd15Zp19YxEXrTyZozqk7QNNVcECPEG8LnOvB/KKbsBtJizNRK3co1HIHO5OJdDWWHa+Is1STsXhrpxUHq5oXK63+yD6Uo9sQBVvsqCjXUju8= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; c=relaxed/simple; bh=JepdiliDjxeimy1FbQPxyBXkifA4pjNCgADzqC6FDSc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=s8CSfKMh9Zpa14pEFMVsqqNohMe6tw5+KHPeSyzo+P/d+2BPMuS1uzIHxgEkYhWn+tKEWD1o7D+uxnISz5EwJdRLRydXVVYTvsSbhfwSlahgrXeWk9b0VITYh49KYM4e7L9iiqvibSDBYfNU8mqb3HsluU3oFPLw00u93gm538c= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=aXK4Tqaq; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=aXK4Tqaq; arc=fail smtp.client-ip=40.107.162.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="aXK4Tqaq"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="aXK4Tqaq" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=YD73ozgJuJ1s1N9fNJFdVqKMUEw5vPD0/MrTlwiJc+jRnUhCEwLPoLn39iNrLTAQGzwQoIANLL8PyVBqKgKui3EB/DhHTt+aSEd+nkyGqZcxF30cK2AWT6jPQiTTLJOsfsQ5vpXMQdV/wHPTrNKbhNox7FeJAuAOaLcVa0uEybUNYFgcKj6uwwpaIzfKElBBQwGOZY6tJgLqjT6xBReUvAqdJLqlToZDWhBlH27AkBn4bE+zF7RcUlX5YC11eNav9s5U09au5Mc2FfNx/EmMLaPR++CkNz6OtX+1gTOUdFHWU/zo/TnqkKdUY2fN2V9pnzjuZGrVfw371WCP2qu6IQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8Jmrw0tdQkdM1p238HpCwZlvslKvE5rn8wqJ1rtx4Nk=; b=okK2QNLXTw6OT8rIdaIOta6g1V4DwVGE1eNniamAamd20WmjCxNppfmLxxuOi8TekTLE9UFIncRO9sNE9vabZ4oTKIH5OSt0AuKfRGWAW/y7Z7KcUHO+4BlfxZMK5Ph/wsjcRxWnHscHyOC8x2hV02aqzX+YHTUPg7AEbN6vvLDQ+R3g5aRpBmPmnwlzIjJHlY0UY3DpNuZQ9XwO+jpPb6cqi2dJzKUZhA/bfJllnbDr7+NifICapj0xvQAMqsO/0DeJ3Z30YQy5ZbjYy0F3UNzbq5Yo1UQPkpYddLQY3t6f4H0gzlc0MdptH3xCU1CA/J+F+QGacociXQwjVKxlUA== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8Jmrw0tdQkdM1p238HpCwZlvslKvE5rn8wqJ1rtx4Nk=; b=aXK4TqaqxPf7ZTzqPrDcv11IDNoLkVuqYqLtFnlEEM9IPheRbOr8En9b4W1IrAoKt2UFo7KC+cK1MFqlW/tFWVsvQLGjsB8qXXIlKHM9NMIuhlIUdAkKdBi7EdWYvUpqzWh26RM5rF9cVJLlHCovUF8bU1iAu1DGaTj2PFwfff8= Received: from DUZPR01CA0219.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b4::16) by AS4PR08MB8244.eurprd08.prod.outlook.com (2603:10a6:20b:51d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:04 +0000 Received: from DB1PEPF000509E2.eurprd03.prod.outlook.com (2603:10a6:10:4b4:cafe::66) by DUZPR01CA0219.outlook.office365.com (2603:10a6:10:4b4::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.13 via Frontend Transport; Fri, 24 Oct 2025 20:22:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DB1PEPF000509E2.mail.protection.outlook.com (10.167.242.52) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:03 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Y106iv8z1xa/dM5wIuSomjnp8i/m/Mg3Wc5bqNiBzSjYpX7TjzyGXrT7ZJu8BRzPOVDUIStcgXF/5ROAw+hAy5/bvG/z6MK8ntudGymBcNtf7n6m8rKQhUN0wQGiGqilNXeltxp9mDcdcOGVL5TBNMfPO56mpV0eZ5+QCdSe0/NR6EBBUcaB8jdY4TkpltsJAxikVyNde0ihSKnIPEPRcZ+4XSArsQXm4rTnCYVFE4v6xF+az7P2Xi6mKKsHtlf67brm+pZHjzXzxflirJEZLZsklyn51AndeCbwWq54lJQd4ff8DB3+KeoncRPkOiP7XAZkAHKK6qc50xRt12z/Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8Jmrw0tdQkdM1p238HpCwZlvslKvE5rn8wqJ1rtx4Nk=; b=TZoLgMYw5jF8+nuEtKfqi+ft7mP8vYysPPTv0XSHJLsSazTgqZA4bzrYmWoOgCmd/hNLByAD9KUtyz8thcslapgfqekaVq+Qwm1ADtcWXfymhOWOOPtQvcs1p9gQfy5fAvmlLdinSPPTMv0gCbFQMc/nZfmUvFNHWVjvRYPMx2QGZunNjq5IgxBt6INBZg3zlynxIPOtmtPRxNzYPaDNc0gH8WOykpdSsqmU/+JXKa0uU2qVxkO4f4odBr95SIS3UCuL+JyJp+W5344KgYhWdzQVr5NCif9Dsj8VFNWKs2KJnhnB5ANzefdFOhgz8/41Qqwowlp1B3NMJ6C5pIVVYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8Jmrw0tdQkdM1p238HpCwZlvslKvE5rn8wqJ1rtx4Nk=; b=aXK4TqaqxPf7ZTzqPrDcv11IDNoLkVuqYqLtFnlEEM9IPheRbOr8En9b4W1IrAoKt2UFo7KC+cK1MFqlW/tFWVsvQLGjsB8qXXIlKHM9NMIuhlIUdAkKdBi7EdWYvUpqzWh26RM5rF9cVJLlHCovUF8bU1iAu1DGaTj2PFwfff8= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:30 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:30 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] drm/panthor: Implement L2 power on/off via PWR_CONTROL Date: Fri, 24 Oct 2025 21:21:13 +0100 Message-ID: <20251024202117.3241292-5-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0395.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18f::22) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|DB1PEPF000509E2:EE_|AS4PR08MB8244:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e388553-0855-4f3e-936a-08de133afe72 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?HdQ0yStik518Pd12jOSqrZltZQivFgsdTwWudUfRt7zK+O4ZS2c3c1gGZacx?= =?us-ascii?Q?neVW2lo8rRbahs/XRxzW9yCVIPfFBLguLACIH/OiTNx7cwWdDxI6Va94EA9w?= =?us-ascii?Q?3EjT9fzVesJp2hVBmB2UGVdbfwC+/apwzfXTEOSXNb9pSIyLoIVl4NaSHK4b?= =?us-ascii?Q?riRzycvo0lNYU6rM4Cx147LSy3sBvDvVPnUsM1yY/dP9bmLV/wBArd763MMv?= =?us-ascii?Q?6nfCQK50F9gVEjT+Wjpy0ry1EYPwPaa5iCg+/rfNpj8p3Syb7aLKBb9KUOVA?= =?us-ascii?Q?7pDEzKp/D258rAnamvPOExCpWxoALc/ZeYs8AWWJ8i7uQeDIsmLt+Z5bLL50?= =?us-ascii?Q?TzhrES/vFJIolqd/xccxordDUC5hhkueOGGiwncsgejAe4WUjyhoGOHwi8G/?= =?us-ascii?Q?ERiogQq7ESiW22ZtiedYpV5X8pxga3DRet4bFDH2tJuKWW48Bj4pQLxpNDb+?= =?us-ascii?Q?uOuWY4DUhI/VSn1C32FGw426xpMp1fsFc1bWJ/kC8KXy/yLHaGdlLttVI41e?= =?us-ascii?Q?NTkxsiBQ7ey87ag9MpyjVD4ua7DYnwKowjzkVWZW+s11Dl/HUHLvL+hCLy1v?= =?us-ascii?Q?XBBqjjmZ8uC0qOGLhDCjicisLXscbiWGVJlBA3MLpNZGgfWUxAhh2mOHnl0V?= =?us-ascii?Q?nsbGoF+zCHRVbV8KLPUDmhKT8f148nTveTyYMsJGBewzXiDR+W7BS6YiYKKd?= =?us-ascii?Q?f+FSgtf2P9V8fl/wWieePW3Mom92yZOCDLkn6DhNNMUQah3kKPWxsLofS9Zr?= =?us-ascii?Q?NyKAoG3TsQroNjZwHsGnkU7AFQD9GecHKRPr7g7We/utav8TzY7r49mRFWCn?= =?us-ascii?Q?ylU6HRcX+tq+VhRsKFbBaGu+FbqbyTpy4l+T+YOoSu/zRklWqM+9FauSFrzj?= =?us-ascii?Q?5ZnXrppHFHn+eXDSjic7CZJYMim/GJXRrSL3GNI+i49V+feYdTyMFL//2/4H?= =?us-ascii?Q?7KBxbC5WPkrptvYqKmZAsjNED0/x3y/wCGkowl/c7tbUHOpwjMC9T5d0EsKU?= =?us-ascii?Q?gsFZ6QC7Oa1ZD2AFKh3gT+EQpURS8pSWwx1OitgrUrXWcRiTsq4rWip+oDTJ?= =?us-ascii?Q?KnYuhFjt7hBxOuLHOuoRdDRAL6O1hnIthlXuV81o0hYXsbjJVreR/yvrSYEn?= =?us-ascii?Q?7uNxi99I3XCKkcd6Imr+PR3+raCM6aKIj3Udes5Ks6MWWp0j7DYbbQooACyv?= =?us-ascii?Q?cUkCe4eYb7pPg5bJYgJHSP7TM6wJ/pjD8Ox/FNtKANn2+6njba8j7OVC2m7h?= =?us-ascii?Q?erkreqSHYlztfscDf7ZbAmC3syqwZx05fmAWBE6f03xj42+1IRMm8OZx0QB+?= =?us-ascii?Q?YuqEWy5J6H/mcgjgeV9o3Z/bOMO1yjpABxwz9wuuks1U7BRxqtC/eIP9QkMR?= =?us-ascii?Q?8qpZMohpWdYMI1PcZQKRHtnHLDIimXDWUBz58J+ufxt/7YJUiQiptqFS4f1Q?= =?us-ascii?Q?/FxDiJlyVUMRE5DrFVNQA/F6JsLN/QRG?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB1PEPF000509E2.eurprd03.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 590ad3b7-4606-4b36-294f-08de133aeadb X-Microsoft-Antispam: BCL:0;ARA:13230040|14060799003|36860700013|82310400026|376014|35042699022|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?leqagVtirxnqAzqAzDFN2nOI/YgN2Z0ZTS9/IRdEo4wx2r3b2RGkmtKlCuOb?= =?us-ascii?Q?r7F3qcMLsSzataWrQMO1O6psE/Gyb6uIhKSqFiY/XRvthI85gK86Vu0q/pZH?= =?us-ascii?Q?i7UbU9CH99grO6qxbGmfcq2LfTMglSaSh/6wsPAcgwyvCfywPpCEhe0+z5NQ?= =?us-ascii?Q?GM0yCUpASI3ypccvxWmVH0ifoIXgkE7ejUT3W/pUpweTxje8hld6rpz9E80I?= =?us-ascii?Q?XENg+h9M73l82yMPb6eIoSIcW6cMHaWQvvLHO3TFbSh/8RWkA+BsYeITtqqH?= =?us-ascii?Q?BIancIZERR1Zk7lPhujb6ujXw/QAluUS77+Dk75fx+NNDDfW+0FVOZyDLXTp?= =?us-ascii?Q?gdBAlBlxuUKvAest+W56ygxEtSjqZi2u7YnKoQUZ9CnlTZJIjZLK1IRdW8Gv?= =?us-ascii?Q?7wro6ZlXDQi88n8kVRU4SetLvMHkD0piReVHX43KBiEDbfz9B2KVfPhKKLHL?= =?us-ascii?Q?aY1uq1/ecpevKO/U1tyrun88f8FbF3ulcW0Ml5EvdMc/SvsupX/H6kKT4IyE?= =?us-ascii?Q?f47tK2BKAHwm6BCPwN7Y0ddoSuxs9PORQHevCN0WBrcpP1fYpCPFHcNFcZPg?= =?us-ascii?Q?DGNOUbu6lI7+I61YfGTD69QF0hS0AKNurtkukxyobC3CPrE416McOw6Nxl2Y?= =?us-ascii?Q?u0mWZDSe809edCN5mNynhUskBcuJGIjHfFuV46jwI4STkMnzGl39v2z14f9b?= =?us-ascii?Q?oFaYoX81Aa7G1SrM1hQS6HcbzN1wtao9HWgYii/Cwmo8gxsZy0yxzmqI6UPT?= =?us-ascii?Q?yN5WaaaZceTZR7ZM65IfmCjC+Jq+HHzNqU7CgtTJuGCgeiHOxxFiEXZ+JrOf?= =?us-ascii?Q?65JHdDGJOwSwfMtf7peSGD/Z3AVQXxTmY92UB0DA54explNWeqagfeIKN67V?= =?us-ascii?Q?lTkHR9/CDvkjlWl7M9Mj1XK6fbyi2/xeVBBeF7vcIDV2chFRx4uEow3pLEqd?= =?us-ascii?Q?jQSjAt6FJm7LGbUeQARt8KBLCE4svvmGCelZrZCYg0iWng0vTVOpZaEmsbNH?= =?us-ascii?Q?43YMU75joF3kYZiYJFTT2NUM08eli3nlUd15/n9HiAmVgyir6TkWSS9yHZI7?= =?us-ascii?Q?kYV156Ntd4j2//+rsNFTbs+4qZ6vwM1Wj/L/AnH06uWe7q1N7Nyb0Zkg3KdF?= =?us-ascii?Q?J/7NAMsE2U3IQEWQIExrKI3V0beBQTpIydX8uHuBqz2eMkbBH6xuI2ybMfyX?= =?us-ascii?Q?LVmRTBiPyPbpyWGjzXU61a69Kjc1b9JcU7xQEOkmtluWt2sOf6idBDwy96FB?= =?us-ascii?Q?ZgLQZ42xeDBj1k9/pFAI9XEtvxQhS3RnKXwvNgW2l20682MWtN4B/7cDq8BA?= =?us-ascii?Q?u49H4voGgdcVn34NEDsgobS+guBYVrhC2IID3Fuq9aGYqnisZ+/LT2pNRyw7?= =?us-ascii?Q?IoCp+3Aa6uKycyz4xCTsHGlpMcwG37xU/wc7PlQcwOCWQRlbe/+1hP2qzw1C?= =?us-ascii?Q?QAfz6aQG0RFM3ZlDE73wkKQtus22pf8h/j7Tzzgp7evJDYR0w4Pv/SoVjC9n?= =?us-ascii?Q?mFmzaBmHblGzjGkEG3PvZbQqd4Iy5oAbw1dn6CCqUZ69BvZQCvyccbFYmGF+?= =?us-ascii?Q?54hyIatxUiHNHjC6MZM=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(14060799003)(36860700013)(82310400026)(376014)(35042699022)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:03.0069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e388553-0855-4f3e-936a-08de133afe72 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E2.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB8244 Content-Type: text/plain; charset="utf-8" This patch adds common helpers to issue power commands, poll transitions, and validate domain state, then wires them into the L2 on/off paths. The L2 power-on sequence now delegates control of the SHADER and TILER domains to the MCU when allowed, while the L2 itself is never delegated. On power-off, dependent domains beneath the L2 are checked, and if necessary, retracted and powered down to maintain proper domain ordering. Signed-off-by: Karunika Choo --- v2: * Updated GENMASK to GENMASK_U64 to address kernel test robot warnings for 32-bit systems. * Removed panthor_pwr_read_status() in favour of a simple gpu_read64() operation on the PWR_STATUS register. * Renamed panthor_pwr_info_show() to panthor_pwr_debug_info_show() for more clarity. * Added additional WARN_ON for an invalid domain when requesting power domain transition. * Made panthor_pwr_domain_transition()'s expected val logic more readable and clearer. * Wait on domain power transition instead of failing the operation. * Fixed inconsistent error return value vs kerneldoc. * Removed confusing drm_dbg in delegate_domain() in favor of a comment. * Add unwind to panthor_pwr_delegate_domains(). * Moved child domain handling logic from panthor_pwr_l2_power_off() into panthor_pwr_domain_force_off(). * Added additional clarification regarding delegation and retraction of power domains. * Minor formatting and readability changes and remove unnecessary checks. --- drivers/gpu/drm/panthor/panthor_pwr.c | 378 +++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_pwr.h | 4 + drivers/gpu/drm/panthor/panthor_regs.h | 1 + 3 files changed, 383 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/pantho= r/panthor_pwr.c index da64fe006a8b..cd529660a276 100644 --- a/drivers/gpu/drm/panthor/panthor_pwr.c +++ b/drivers/gpu/drm/panthor/panthor_pwr.c @@ -23,6 +23,14 @@ PWR_IRQ_COMMAND_NOT_ALLOWED | \ PWR_IRQ_COMMAND_INVALID) +#define PWR_ALL_CORES_MASK GENMASK_U64(63, 0) + +#define PWR_DOMAIN_MAX_BITS 16 + +#define PWR_TRANSITION_TIMEOUT_US (2ULL * USEC_PER_SEC) + +#define PWR_RETRACT_TIMEOUT_US (2ULL * USEC_PER_MSEC) + /** * struct panthor_pwr - PWR_CONTROL block management data. */ @@ -59,6 +67,323 @@ static void panthor_pwr_irq_handler(struct panthor_devi= ce *ptdev, u32 status) } PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler); +static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 co= mmand, u64 args) +{ + if (args) + gpu_write64(ptdev, PWR_CMDARG, args); + + gpu_write(ptdev, PWR_COMMAND, command); +} + +static const char *get_domain_name(u8 domain) +{ + switch (domain) { + case PWR_COMMAND_DOMAIN_L2: + return "L2"; + case PWR_COMMAND_DOMAIN_TILER: + return "Tiler"; + case PWR_COMMAND_DOMAIN_SHADER: + return "Shader"; + case PWR_COMMAND_DOMAIN_BASE: + return "Base"; + case PWR_COMMAND_DOMAIN_STACK: + return "Stack"; + } + return "Unknown"; +} + +static u32 get_domain_base(u8 domain) +{ + switch (domain) { + case PWR_COMMAND_DOMAIN_L2: + return PWR_L2_PRESENT; + case PWR_COMMAND_DOMAIN_TILER: + return PWR_TILER_PRESENT; + case PWR_COMMAND_DOMAIN_SHADER: + return PWR_SHADER_PRESENT; + case PWR_COMMAND_DOMAIN_BASE: + return PWR_BASE_PRESENT; + case PWR_COMMAND_DOMAIN_STACK: + return PWR_STACK_PRESENT; + } + return 0; +} + +static u32 get_domain_ready_reg(u32 domain) +{ + return get_domain_base(domain) + (PWR_L2_READY - PWR_L2_PRESENT); +} + +static u32 get_domain_pwrtrans_reg(u32 domain) +{ + return get_domain_base(domain) + (PWR_L2_PWRTRANS - PWR_L2_PRESENT); +} + +static bool is_valid_domain(u32 domain) +{ + return get_domain_base(domain) !=3D 0; +} + +static bool has_rtu(struct panthor_device *ptdev) +{ + return ptdev->gpu_info.gpu_features & GPU_FEATURES_RAY_TRAVERSAL; +} + +static u8 get_domain_subdomain(struct panthor_device *ptdev, u32 domain) +{ + if ((domain =3D=3D PWR_COMMAND_DOMAIN_SHADER) && has_rtu(ptdev)) + return PWR_COMMAND_SUBDOMAIN_RTU; + + return 0; +} + +static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev= , u32 domain, + u32 timeout_us) +{ + u32 pwrtrans_reg =3D get_domain_pwrtrans_reg(domain); + u64 val; + int ret =3D 0; + + ret =3D gpu_read64_poll_timeout(ptdev, pwrtrans_reg, val, !(PWR_ALL_CORES= _MASK & val), 100, + timeout_us); + if (ret) { + drm_err(&ptdev->base, "%s domain power in transition, pwrtrans(0x%llx)", + get_domain_name(domain), val); + return ret; + } + + return 0; +} + +static void panthor_pwr_debug_info_show(struct panthor_device *ptdev) +{ + drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev, GP= U_FEATURES)); + drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev, PW= R_STATUS)); + drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev, PW= R_L2_PRESENT)); + drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PW= R_L2_PWRTRANS)); + drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev, PW= R_L2_READY)); + drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev, PW= R_TILER_PRESENT)); + drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PW= R_TILER_PWRTRANS)); + drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev, PW= R_TILER_READY)); + drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev, PW= R_SHADER_PRESENT)); + drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PW= R_SHADER_PWRTRANS)); + drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev, PW= R_SHADER_READY)); +} + +static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32= cmd, u32 domain, + u64 mask, u32 timeout_us) +{ + u32 ready_reg =3D get_domain_ready_reg(domain); + u32 pwr_cmd =3D PWR_COMMAND_DEF(cmd, domain, get_domain_subdomain(ptdev, = domain)); + u64 expected_val =3D 0; + u64 val; + int ret =3D 0; + + if (drm_WARN_ON(&ptdev->base, !is_valid_domain(domain))) + return -EINVAL; + + switch (cmd) { + case PWR_COMMAND_POWER_DOWN: + expected_val =3D 0; + break; + case PWR_COMMAND_POWER_UP: + expected_val =3D mask; + break; + default: + drm_err(&ptdev->base, "Invalid power domain transition command (0x%x)", = cmd); + return -EINVAL; + } + + ret =3D panthor_pwr_domain_wait_transition(ptdev, domain, timeout_us); + if (ret) + return ret; + + /* domain already in target state, return early */ + if ((gpu_read64(ptdev, ready_reg) & mask) =3D=3D expected_val) + return 0; + + panthor_pwr_write_command(ptdev, pwr_cmd, mask); + + ret =3D gpu_read64_poll_timeout(ptdev, ready_reg, val, (mask & val) =3D= =3D expected_val, 100, + timeout_us); + if (ret) { + drm_err(&ptdev->base, + "timeout waiting on %s power domain transition, cmd(0x%x), arg(0x%llx)", + get_domain_name(domain), pwr_cmd, mask); + panthor_pwr_debug_info_show(ptdev); + return ret; + } + + return 0; +} + +#define panthor_pwr_domain_power_off(__ptdev, __domain, __mask, __timeout_= us) \ + panthor_pwr_domain_transition(__ptdev, PWR_COMMAND_POWER_DOWN, __domain, = __mask, \ + __timeout_us) + +#define panthor_pwr_domain_power_on(__ptdev, __domain, __mask, __timeout_u= s) \ + panthor_pwr_domain_transition(__ptdev, PWR_COMMAND_POWER_UP, __domain, __= mask, __timeout_us) + +/** + * retract_domain() - Retract control of a domain from MCU + * @ptdev: Device. + * @domain: Domain to retract the control + * + * Retracting L2 domain is not expected since it won't be delegated. + * + * Return: 0 on success or retracted already. + * -EPERM if domain is L2. + * A negative error code otherwise. + */ +static int retract_domain(struct panthor_device *ptdev, u32 domain) +{ + const u32 pwr_cmd =3D PWR_COMMAND_DEF(PWR_COMMAND_RETRACT, domain, 0); + const u64 pwr_status =3D gpu_read64(ptdev, PWR_STATUS); + const u64 delegated_mask =3D PWR_STATUS_DOMAIN_DELEGATED(domain); + const u64 allow_mask =3D PWR_STATUS_DOMAIN_ALLOWED(domain); + u64 val; + int ret; + + if (drm_WARN_ON(&ptdev->base, domain =3D=3D PWR_COMMAND_DOMAIN_L2)) + return -EPERM; + + ret =3D gpu_read64_poll_timeout(ptdev, PWR_STATUS, val, !(PWR_STATUS_RETR= ACT_PENDING & val), + 0, PWR_RETRACT_TIMEOUT_US); + if (ret) { + drm_err(&ptdev->base, "%s domain retract pending", get_domain_name(domai= n)); + return ret; + } + + if (!(pwr_status & delegated_mask)) { + drm_dbg(&ptdev->base, "%s domain already retracted", get_domain_name(dom= ain)); + return 0; + } + + panthor_pwr_write_command(ptdev, pwr_cmd, 0); + + /* + * On successful retraction + * allow-flag will be set with delegated-flag being cleared. + */ + ret =3D gpu_read64_poll_timeout(ptdev, PWR_STATUS, val, + ((delegated_mask | allow_mask) & val) =3D=3D allow_mask, 10, + PWR_TRANSITION_TIMEOUT_US); + if (ret) { + drm_err(&ptdev->base, "Retracting %s domain timeout, cmd(0x%x)", + get_domain_name(domain), pwr_cmd); + return ret; + } + + return 0; +} + +/** + * delegate_domain() - Delegate control of a domain to MCU + * @ptdev: Device. + * @domain: Domain to delegate the control + * + * Delegating L2 domain is prohibited. + * + * Return: + * * 0 on success or delegated already. + * * -EPERM if domain is L2. + * * A negative error code otherwise. + */ +static int delegate_domain(struct panthor_device *ptdev, u32 domain) +{ + const u32 pwr_cmd =3D PWR_COMMAND_DEF(PWR_COMMAND_DELEGATE, domain, 0); + const u64 pwr_status =3D gpu_read64(ptdev, PWR_STATUS); + const u64 allow_mask =3D PWR_STATUS_DOMAIN_ALLOWED(domain); + const u64 delegated_mask =3D PWR_STATUS_DOMAIN_DELEGATED(domain); + u64 val; + int ret; + + if (drm_WARN_ON(&ptdev->base, domain =3D=3D PWR_COMMAND_DOMAIN_L2)) + return -EPERM; + + /* Already delegated, exit early */ + if (pwr_status & delegated_mask) + return 0; + + /* Check if the command is allowed before delegating. */ + if (!(pwr_status & allow_mask)) { + drm_warn(&ptdev->base, "Delegating %s domain not allowed", get_domain_na= me(domain)); + return -EPERM; + } + + ret =3D panthor_pwr_domain_wait_transition(ptdev, domain, PWR_TRANSITION_= TIMEOUT_US); + if (ret) + return ret; + + panthor_pwr_write_command(ptdev, pwr_cmd, 0); + + /* + * On successful delegation + * allow-flag will be cleared with delegated-flag being set. + */ + ret =3D gpu_read64_poll_timeout(ptdev, PWR_STATUS, val, + ((delegated_mask | allow_mask) & val) =3D=3D delegated_mask, + 10, PWR_TRANSITION_TIMEOUT_US); + if (ret) { + drm_err(&ptdev->base, "Delegating %s domain timeout, cmd(0x%x)", + get_domain_name(domain), pwr_cmd); + return ret; + } + + return 0; +} + +static int panthor_pwr_delegate_domains(struct panthor_device *ptdev) +{ + int ret; + + if (!ptdev->pwr) + return 0; + + ret =3D delegate_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER); + if (ret) + return ret; + + ret =3D delegate_domain(ptdev, PWR_COMMAND_DOMAIN_TILER); + if (ret) + goto err_retract_shader; + + return 0; + +err_retract_shader: + retract_domain(ptdev, PWR_COMMAND_DOMAIN_SHADER); + + return ret; +} + +/** + * panthor_pwr_domain_force_off - Forcefully power down a domain. + * @ptdev: Device. + * @domain: Domain to forcefully power down. + * + * This function will attempt to retract and power off the requested power + * domain. However, if retraction fails, the operation is aborted. If powe= r off + * fails, the domain will remain retracted and under the host control. + * + * Return: 0 on success or a negative error code on failure. + */ +static int panthor_pwr_domain_force_off(struct panthor_device *ptdev, u32 = domain) +{ + const u64 domain_ready =3D gpu_read64(ptdev, get_domain_ready_reg(domain)= ); + int ret; + + /* Domain already powered down, early exit. */ + if (!domain_ready) + return 0; + + /* Domain has to be in host control to issue power off command. */ + ret =3D retract_domain(ptdev, domain); + if (ret) + return ret; + + return panthor_pwr_domain_power_off(ptdev, domain, domain_ready, PWR_TRAN= SITION_TIMEOUT_US); +} + void panthor_pwr_unplug(struct panthor_device *ptdev) { unsigned long flags; @@ -103,6 +428,59 @@ int panthor_pwr_init(struct panthor_device *ptdev) return 0; } +void panthor_pwr_l2_power_off(struct panthor_device *ptdev) +{ + const u64 l2_allow_mask =3D PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_= L2); + const u64 pwr_status =3D gpu_read64(ptdev, PWR_STATUS); + + /* Abort if L2 power off constraints are not satisfied */ + if (!(pwr_status & l2_allow_mask)) { + drm_warn(&ptdev->base, "Power off L2 domain not allowed"); + return; + } + + /* It is expected that when halting the MCU, it would power down its + * delegated domains. However, an unresponsive or hung MCU may not do + * so, which is why we need to check and retract the domains back into + * host control to be powered down in the right order before powering + * down the L2. + */ + if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_TILER)) + return; + + if (panthor_pwr_domain_force_off(ptdev, PWR_COMMAND_DOMAIN_SHADER)) + return; + + panthor_pwr_domain_power_off(ptdev, PWR_COMMAND_DOMAIN_L2, ptdev->gpu_inf= o.l2_present, + PWR_TRANSITION_TIMEOUT_US); +} + +int panthor_pwr_l2_power_on(struct panthor_device *ptdev) +{ + const u32 pwr_status =3D gpu_read64(ptdev, PWR_STATUS); + const u32 l2_allow_mask =3D PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_= L2); + int ret; + + if ((pwr_status & l2_allow_mask) =3D=3D 0) { + drm_warn(&ptdev->base, "Power on L2 domain not allowed"); + return -EPERM; + } + + ret =3D panthor_pwr_domain_power_on(ptdev, PWR_COMMAND_DOMAIN_L2, ptdev->= gpu_info.l2_present, + PWR_TRANSITION_TIMEOUT_US); + if (ret) + return ret; + + /* Delegate control of the shader and tiler power domains to the MCU as + * it can better manage which shader/tiler cores need to be powered up + * or can be powered down based on currently running jobs. + * + * If the shader and tiler domains are already delegated to the MCU, + * this call would just return early. + */ + return panthor_pwr_delegate_domains(ptdev); +} + void panthor_pwr_suspend(struct panthor_device *ptdev) { if (!ptdev->pwr) diff --git a/drivers/gpu/drm/panthor/panthor_pwr.h b/drivers/gpu/drm/pantho= r/panthor_pwr.h index b325e5b7eba3..3c834059a860 100644 --- a/drivers/gpu/drm/panthor/panthor_pwr.h +++ b/drivers/gpu/drm/panthor/panthor_pwr.h @@ -10,6 +10,10 @@ void panthor_pwr_unplug(struct panthor_device *ptdev); int panthor_pwr_init(struct panthor_device *ptdev); +void panthor_pwr_l2_power_off(struct panthor_device *ptdev); + +int panthor_pwr_l2_power_on(struct panthor_device *ptdev); + void panthor_pwr_suspend(struct panthor_device *ptdev); void panthor_pwr_resume(struct panthor_device *ptdev); diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panth= or/panthor_regs.h index 5469eec02178..18702d7001e2 100644 --- a/drivers/gpu/drm/panthor/panthor_regs.h +++ b/drivers/gpu/drm/panthor/panthor_regs.h @@ -72,6 +72,7 @@ #define GPU_FEATURES 0x60 #define GPU_FEATURES_RAY_INTERSECTION BIT(2) +#define GPU_FEATURES_RAY_TRAVERSAL BIT(5) #define GPU_TIMESTAMP_OFFSET 0x88 #define GPU_CYCLE_COUNT 0x90 -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010030.outbound.protection.outlook.com [52.101.69.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10B372F0C74 for ; Fri, 24 Oct 2025 20:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.69.30 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; cv=fail; b=aHPLjZBKtjS5xvGevvpHF8nvccnRjce+5DO54Nqqhs4FbR09JRHmtluwAxA51A12HYSVDeL9s6XN0AixXv9MuufuCcX6if8n6pPTvWJk9IUrEuGhQMSlHdMQMcIsravL3pD33OFBC5Rexs/2BYuIgBe45Ey5l3uYPe4+DHpo1Mw= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; c=relaxed/simple; bh=4oxrKYUSHIdw7zu8UtywLD7V1RpyWCgvW7cNfop+R9M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Ah6ThJPHdLOdUSvd5fhl+ebEDpKN025bR38aPYBGHNre9o5XLrZl7h9F5o72exwShWwSE11vXyxBGv03rUhvKaGCzoGW6lK1E/k7zOTt0arzIRfJ2C78KqDiO9de26Pqqw7sz4n3Ks4Il6iI9jfpDOsE+2xEndAtQNN1wWzHTVU= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=llJMY1F8; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=llJMY1F8; arc=fail smtp.client-ip=52.101.69.30 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="llJMY1F8"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="llJMY1F8" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=QeAa93/MdJiJAfvznC0cJadZt8HtpAhmjjQlf2ksgH5RarlBaiR8SVwvCclkhfhZLoTyjGcHLcTEMyYAPDhwFy6aKxlJZgmUicJM3hwQrJqOYIzl65uCMFUf66CnJ46WcDBJgn4WQ69AkO8zXP8X96cjmssdRmovB+v9H6yhIxxqh0Ka0B4IW2v8gbsuu8TgPC4OwxvgQprAeTCtHBW0UBf7Igj/uMH1zCPkBQINElubFRyUH30mpGN/UpmSPB3P7nvVKva06XjGJP/aOI0+d1gmPnQQy31kRg5hbHk5tiep681mBydnd8nHYM0iCcE5AjMInUCy2cctut/sDAEZXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zn2YdCLgGNEnnzpHiNJ/Epr5k2AZPwdy7K9SGWKkaPc=; b=iNv81+zat0eNj1/gym9e/DFgL3U5BMbYZWUuExGCxWn/w7P9/GNCzp/bCLfj1kCZr2F9Rn5hNdi/Mkzjxgq2/9MOjc4I+/5XKHVEPOZSD12V4rDLjf4UoiRqonGigD/Bk99SkF80ed8De3QaiSdJ6yTPoiTPHuOiQASyMYmrHK58PM71E13fX3tGcs8xElThuvHb6Qn0mjisaAhxAt082N5RazyFZZ2H5HTigVUiim2j5lFeOAb3tjrRPeOVqXSXzha8rUrvxwPBG2kvghRM22gKjKw9Sog4HPujx6ILkUFZjEPlA4qAC5R2RTegfhhWIKAfgWcc5B4CUCc5gi34Aw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zn2YdCLgGNEnnzpHiNJ/Epr5k2AZPwdy7K9SGWKkaPc=; b=llJMY1F8EVLZX0fQvVAZ0tuUY/yNMLFBRWu1Gv/E7yXv2gJmYJwGlZQJiJ82RvJemwiPd6ZOLPrKxbRbpkwtwY83DE9GZbZpzeXmEq1LafmHJOE2ciE8wUbDb7cf/4RF4MbXuUYnluUo+cJu4SXQnwmn+C7wZ8iGDgAzsqMFO+Q= Received: from AM0PR03CA0019.eurprd03.prod.outlook.com (2603:10a6:208:14::32) by DU0PR08MB9438.eurprd08.prod.outlook.com (2603:10a6:10:42e::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:04 +0000 Received: from AMS0EPF000001A7.eurprd05.prod.outlook.com (2603:10a6:208:14:cafe::4d) by AM0PR03CA0019.outlook.office365.com (2603:10a6:208:14::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.13 via Frontend Transport; Fri, 24 Oct 2025 20:22:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AMS0EPF000001A7.mail.protection.outlook.com (10.167.16.234) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:03 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=K2YkXCFqPM9oAP880cxYLjABGLmg63v9C0kmhZEogKt3b/J69b1tPuDJLrLsmZSMNn/BRp/oln6KUzyC/VOCVtWDdSeZOGY+JfipCAC2m0ZnlHFpU9zMFWM9wnmeYbXvwfqx8yEH3iHUTsiinZRQPKt8J/bgULo4+LFNORIOFbAqIX1UdJHCYPebvXlaNNKuYdcFONYWK7ZbH51/JaBBIDmCJsGUU0lieBsjhIsP3zhi0EFjD6M6rSRbRRU7IKwBhBAwSWqP3CntCP9+68p4VB4ltWqXWVfugDehGeE04xQ+e9fXMq0VZUOYWUP4vi3z5KXuNViQ6vq0DKNwvgnZ1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zn2YdCLgGNEnnzpHiNJ/Epr5k2AZPwdy7K9SGWKkaPc=; b=KgAcxzIyzGzZWXuMqoe2nFeLTQbnfe8m+U8LJ95bfc4d5exNGd50JlJ9paap4tGZmKkCWJpiCHHDVOtNHgWRsqH5LPprHKxKoj0LVXeIaufec/Gdeuxf6Mg9+32vxmeekVq3uNkWNbdnV9yXUbRWTa/YQ95ORBQuq+BEgyDFsRwOYq86yUPgg4PnQyc4opjNECvusND1XkjRDGTvVabKK2mVh+UjeXt0Ox44dHSwHPVVCHh1/dEiKDMTcPI2BeH+1lvBzkECZuLto0GDli5oRE9EZxXMhAAZ7252Y2JmB0pRk6oe8OBPec8md2UmD8BNFxpEzl9s7Ue/aE7ruOdAYg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zn2YdCLgGNEnnzpHiNJ/Epr5k2AZPwdy7K9SGWKkaPc=; b=llJMY1F8EVLZX0fQvVAZ0tuUY/yNMLFBRWu1Gv/E7yXv2gJmYJwGlZQJiJ82RvJemwiPd6ZOLPrKxbRbpkwtwY83DE9GZbZpzeXmEq1LafmHJOE2ciE8wUbDb7cf/4RF4MbXuUYnluUo+cJu4SXQnwmn+C7wZ8iGDgAzsqMFO+Q= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:31 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:31 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] drm/panthor: Implement soft reset via PWR_CONTROL Date: Fri, 24 Oct 2025 21:21:14 +0100 Message-ID: <20251024202117.3241292-6-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0516.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:272::9) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|AMS0EPF000001A7:EE_|DU0PR08MB9438:EE_ X-MS-Office365-Filtering-Correlation-Id: 92d1dabc-4e1e-4114-24e0-08de133afef8 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?pk+DCZZ8qrGqRA9Z5iipJ8jsPcjXLKqQEmJPsUpgIn95JlFKTipzUk6HVs7Q?= =?us-ascii?Q?M+y30nKnjpmtY8RJM54zxflX5Y9tb5S/f1HJb7FS1iMfaxdZq5ZGU7eiJxE1?= =?us-ascii?Q?egzdZOKvNjOJfosKQ0C11+5Df6cwBExciY5WXpY8cNz9FGRI0liaq5K2/KjT?= =?us-ascii?Q?jDfPhphaZrGAtbN1sSPooo/yTg9PK6sL6+STNoXoH40RNiApmwZhxyLswylJ?= =?us-ascii?Q?HVcb0LfeJPE6xe5eEs+ZAXQa96nIadxxW/NdxDmOy4PGYEBPqZaCOBcJ85/w?= =?us-ascii?Q?R8NY89Y1Hgwo1eaBdHleWNjU+oZv7tEPb06yuFIYZltYvNnpYroeFxm9vfCg?= =?us-ascii?Q?Uzw/m5iD72+RiQ7qkjoooVOziTGAz00uWmIYBYFpuF5d5oB1my0DE8DeLQGG?= =?us-ascii?Q?NCGCz1VNrpHV6fFmkHNUxL830OHTcrrUvxYZw4nxzFNEn9pTvQmxC9+f00nb?= =?us-ascii?Q?6sd6gC1P7pXbh9Ejj0DiL0OBSeHtXUZgdk9kiD7YTzWZWZptDGgWVrYaXJoj?= =?us-ascii?Q?dy/o7Rv4oEBRevJ26pnjxKP4uuhdcF5aL0BCN0CXyRJveQEcbVgTAbzytY1z?= =?us-ascii?Q?ljB4gn2jBwkABhRjZ6h/CgLowMUVnsKlKqoC2AiVp81dG+sADvCDx7zO0Cpw?= =?us-ascii?Q?xFUygKZP2yOSKNEryekYmv4cuEvm38VHYK3s0PRLf3CG3wv5Oivk7NVHEGM9?= =?us-ascii?Q?irouut1JQm8zzrvLZ3I9WaGBTJtOXadic735CUKFHC36KW+uF/oaZ+OAGfIY?= =?us-ascii?Q?4859V4Y7lg5ra2b2gc6RXBWlcrB72fY0TVO1BTE4tQZ1GeZmKhmXf993/cfq?= =?us-ascii?Q?IgRgZcOpe8rsw8DOJgu+rbUTTuEGMn58JZU9QQRW5BeKaXyMa0xs3whfINst?= =?us-ascii?Q?x1WozbMAADLVqZSmXnx7kKwVH5DCzG3YdkYd1PpfnF3wuo6R2MVPj/nPhzyZ?= =?us-ascii?Q?I/4KYzsz57jCi2bHqeHyHRWc66mEOhz3NDAmiMgrZVGu8I7B4WNtFQA4CxZ0?= =?us-ascii?Q?ngKGkZ4MXTDheYDvywh3+3JSMMkpbetF0TIrN72o4hYC5pwnp80On5b1itoZ?= =?us-ascii?Q?59Zg7Z1nG8cQSaAojWGVhAhhx+T9S8u0S763452wn++F8M+dVKVRbyjJHbhc?= =?us-ascii?Q?U4BbH137AxS0lic5gIV/Lsp1ZzmXYO4t3JlIHj+sNbxKpPJ1jci5urNjfl/D?= =?us-ascii?Q?HmnjfGY7TlMYorQ534gAEgErXv+JWFjPCrflngtopdM4GuItCxNPkvUcFZlW?= =?us-ascii?Q?2cdmUa3TfF+FP1oYG6KgJtAtTfPCF0vWWl6UGPXvilDaIGZbRrBzb8opWDjP?= =?us-ascii?Q?oIQKMcROwhdHTis3UKlUkgA1R6SJWD9eEu4HR7UzSvhNHchEn3IHb/OkNMjb?= =?us-ascii?Q?HBzfAMHlLoXaqvc07EjBv6UGnq+I2DomD6RH2PjET0aRjXys5tspKZPiGheI?= =?us-ascii?Q?AcKJJ0i1zb7x7RqRtre18Pty0XlNivZt?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS0EPF000001A7.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: c13561ce-a261-4ac1-0c98-08de133aebaf X-Microsoft-Antispam: BCL:0;ARA:13230040|14060799003|35042699022|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?S6Hb7pdo0izGuAKrnZqlbzevF+aE9qw6S9dDChePrmx8aSXL+xrXg3mSZEvw?= =?us-ascii?Q?IVX2fH4nu7pzLpwD4acBXchGE0umHDtmP1xI3Ory7FD4RIi3Ez/rKXtkT/II?= =?us-ascii?Q?UsS4gZfjGyVOkBU6V3pbli9PQ7b+Ckg3UHfOTuDDQkImsBNu2qrJhLGBGsAF?= =?us-ascii?Q?kLBO+o/wFFuiuMGp89UQw5V5BH/SQoEHCTTQPBF84NPEoFlB/aJhrE/DlOzt?= =?us-ascii?Q?OpL/73/sLmYZzjIWVIXqElaiaZ90dlGtdHscEZSoNFszPosq+nY3N9iXHvTt?= =?us-ascii?Q?OX5ld25/XyGYaCiQ32/+CLgYYa7z/sXp0NDqz5gRXStc3/VpO6Bes/MOvTAF?= =?us-ascii?Q?Wb5Q0MvNDfiJ3hGqX1x9E35IYncq5zrZe2/N874BmOaXTnzcBKW1r/fet3p6?= =?us-ascii?Q?G4tzrwfstejgmIoIdKoCz7wouoZy2MIWyAgpsnRb9uOod7OVBxNEfNeZmlzg?= =?us-ascii?Q?tsSe4FOgMRWXV2/nq+0hVZEfGngBO46ZEBN/GK+PswmWz31S8LwU6eWUePGs?= =?us-ascii?Q?2zsh4m3j90AEqiBm5I79dTHpHsc1PES4jsjEFbgs1VfeXOdxFtVp7tT59vuS?= =?us-ascii?Q?ink8tjhznhPIEfwG2RVT328ijfGVbnAIDEPI/8wj8KYzgF10/z0fUidDf9nz?= =?us-ascii?Q?MWLR4GKoxBkJPOt//VpyJCkmGAGi4EFKZjPLG9SUSF5ySb0eOKzHM+oVxey3?= =?us-ascii?Q?+muLnk8XrxLX5cAPHZNOKuBG/PUizWhEYQ0vfBfZV1w3OzB1z8DqSz9xN/KH?= =?us-ascii?Q?1D0HgWEATDg2hRakwxvde54EofL6KVvGAih/ATlVfdQLBX4TGDw5BzjVexod?= =?us-ascii?Q?ZDD8vcKoGhmMgrJXoY/b4ELHBUeC49YlvvoC9nEEoO33YuLxPvzEqexOl5cD?= =?us-ascii?Q?Q/Jtf+zTspRJqqtTNTCYTpUIYuVXpLa2OsLRugDqDeqLcURPYsimHsiMgOHq?= =?us-ascii?Q?yJVooKh2ljHmD2TrwhLT4I7POg812ClFFy3do+bPvcFl2y+ST3G6ohJOTQx4?= =?us-ascii?Q?RPlOOuvz0pqf4+RCOuCZ5xLhH1/eHZobv3t5b+rXY2tFXVhRUhxy5V6x4CQo?= =?us-ascii?Q?vOYVr4PNhmcmSdwOiUj40IYZEjZJma4F3W/OBUQhWQKYIrK95+oPd3KMHuFG?= =?us-ascii?Q?D71XdAUVjwgnWn7yYnMzY3vxw/6FarP24zS4mXH4PhJ2fNyNINMPi6DpIaj3?= =?us-ascii?Q?e53tbbsVP6VHS650oggbrD6I7yVrRXUPAnOnFejwvrpZi1JUUexgIRJfuPpa?= =?us-ascii?Q?1v1ITV7gl+3ISiG821NRe7oTcCj+PJlq4fMOgJ18z1ANKaDNgy/n93QP2eD5?= =?us-ascii?Q?J8fwoIjmhnBYI60vtm/pRJZxbnWKi6sKxYBaMFxgRrrpuW98+ktFgLfgwGlq?= =?us-ascii?Q?l95XOAGl+73XrRaCgi8jGiZ1GJTDCB29Rfb81orboBsNoect6r496pYrtI4Z?= =?us-ascii?Q?YQkd1fjBVQfXE+ihciXKxWfg7hkrM+tt4+wQgHqsQaeyZoTwI1ERKWmP2icG?= =?us-ascii?Q?fiNrI9UH9gmhnrWksNWM3IEQwcj3fQutAPwrEFVkxMuwfc5jxVYRrBxsOcqe?= =?us-ascii?Q?qnr2NOLTfYp55ecOgV4=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(14060799003)(35042699022)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:03.8939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92d1dabc-4e1e-4114-24e0-08de133afef8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A7.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9438 Content-Type: text/plain; charset="utf-8" Add helpers to issue reset commands through the PWR_CONTROL interface and wait for reset completion using IRQ signaling. This enables support for RESET_SOFT operations with timeout handling and status verification. Signed-off-by: Karunika Choo --- v2: * Dropped RESET_FAST implementation as it is not currently being used. * Renamed reset_completed to reset_pending to align with underlying logic and fixed the logic of its callers accordingly. * Improved readability of panthor_pwr_reset() and removed inline ternary expressions. --- drivers/gpu/drm/panthor/panthor_pwr.c | 50 +++++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_pwr.h | 2 ++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/pantho= r/panthor_pwr.c index cd529660a276..4edb818c7ac4 100644 --- a/drivers/gpu/drm/panthor/panthor_pwr.c +++ b/drivers/gpu/drm/panthor/panthor_pwr.c @@ -3,6 +3,7 @@ #include #include +#include #include #include @@ -31,6 +32,8 @@ #define PWR_RETRACT_TIMEOUT_US (2ULL * USEC_PER_MSEC) +#define PWR_RESET_TIMEOUT_MS 500 + /** * struct panthor_pwr - PWR_CONTROL block management data. */ @@ -75,6 +78,43 @@ static void panthor_pwr_write_command(struct panthor_dev= ice *ptdev, u32 command, gpu_write(ptdev, PWR_COMMAND, command); } +static bool reset_irq_raised(struct panthor_device *ptdev) +{ + return gpu_read(ptdev, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED; +} + +static bool reset_pending(struct panthor_device *ptdev) +{ + return (ptdev->pwr->pending_reqs & PWR_IRQ_RESET_COMPLETED); +} + +static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd) +{ + scoped_guard(spinlock_irqsave, &ptdev->pwr->reqs_lock) { + if (reset_pending(ptdev)) { + drm_WARN(&ptdev->base, 1, "Reset already pending"); + } else { + ptdev->pwr->pending_reqs |=3D PWR_IRQ_RESET_COMPLETED; + gpu_write(ptdev, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED); + panthor_pwr_write_command(ptdev, reset_cmd, 0); + } + } + + if (!wait_event_timeout(ptdev->pwr->reqs_acked, !reset_pending(ptdev), + msecs_to_jiffies(PWR_RESET_TIMEOUT_MS))) { + guard(spinlock_irqsave)(&ptdev->pwr->reqs_lock); + + if (reset_pending(ptdev) && !reset_irq_raised(ptdev)) { + drm_err(&ptdev->base, "RESET timed out (0x%x)", reset_cmd); + return -ETIMEDOUT; + } + + ptdev->pwr->pending_reqs &=3D ~PWR_IRQ_RESET_COMPLETED; + } + + return 0; +} + static const char *get_domain_name(u8 domain) { switch (domain) { @@ -428,6 +468,16 @@ int panthor_pwr_init(struct panthor_device *ptdev) return 0; } +int panthor_pwr_reset_soft(struct panthor_device *ptdev) +{ + if (!(gpu_read64(ptdev, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) { + drm_err(&ptdev->base, "RESET_SOFT not allowed"); + return -EOPNOTSUPP; + } + + return panthor_pwr_reset(ptdev, PWR_COMMAND_RESET_SOFT); +} + void panthor_pwr_l2_power_off(struct panthor_device *ptdev) { const u64 l2_allow_mask =3D PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_= L2); diff --git a/drivers/gpu/drm/panthor/panthor_pwr.h b/drivers/gpu/drm/pantho= r/panthor_pwr.h index 3c834059a860..adf1f6136abc 100644 --- a/drivers/gpu/drm/panthor/panthor_pwr.h +++ b/drivers/gpu/drm/panthor/panthor_pwr.h @@ -10,6 +10,8 @@ void panthor_pwr_unplug(struct panthor_device *ptdev); int panthor_pwr_init(struct panthor_device *ptdev); +int panthor_pwr_reset_soft(struct panthor_device *ptdev); + void panthor_pwr_l2_power_off(struct panthor_device *ptdev); int panthor_pwr_l2_power_on(struct panthor_device *ptdev); -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010045.outbound.protection.outlook.com [52.101.84.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97DB72F1FC8 for ; Fri, 24 Oct 2025 20:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.84.45 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337337; cv=fail; b=HEf1lhmrUjNk8Xwu3HkG5IHZnabJxnzNsY1Rei2t8a2vO3XM0N3K8jWRRLA802+7UtiUSLg2YKwLtVe/K83e7SMjTR1qjEYplrd+ApKq8qASeVUPCL1Swdm80w2nTXXkas/qzUt94z33c5b/TaUlgTqe9SIGflgc5iHxei8wlBc= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337337; c=relaxed/simple; bh=GfdnodDQiZ8FRhSRqoKQXlVJtHLzxCrOb4PjLmuPMIw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=e2zg/SazIomzwZjTHVKNeBkYILJ29RmYRKzUqxCYlCePdAHH3IUmXlGo2FVksYuxaDcaisoS/+nDdcBA+rJ8aaAjRHEgfbxDAvu+AZJb+q73i7PK1lFZ73IZlMA/YfQKKq5e2mUwtKjNxgDnnanWI+/kXbtKz/6tVmXeF5aHQAk= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Qhdf9Qet; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Qhdf9Qet; arc=fail smtp.client-ip=52.101.84.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Qhdf9Qet"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Qhdf9Qet" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=EfMXI++B9IYxi3I5qtdkqPdYXREH5KMZ/n364Rn5CkeEu/XBUoP7n2GGo9sT5VeW6VVncohKYEt5AmoXEOKWjKDmeOtMP5BP3gtZbsv7+0CvOkN6y7iOR7NLOW8N9n4Ble+ouI9RQzY0AEuBvMXXUcA9qNic8pKXDqtgfWh0LhQPnyElPyQXYr4b0lCfF+3CesnQCim+Fff0RAME1TDo8kWJH70C2/IZaf6YHgSa8mQ/ByWOgsGU8+Hlpq6lrgo6hPiVYhoK+YlCe/P1lBT2bYvpZbfDLuJ7Q7NkY8o1HVYX3V6a/8yEsXH7Gj1VgLQxATGkIpNEI0Oml9kDY5llGA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JuAWy1IcIPEshsV8czPgvuRqxPi0HJBkk2JmOdC2ByY=; b=eztntLUeBCwuUl5YUFNQpp+jr7Z9OBfSQjIhr35NXJwiLV7lCGuQc1TugjCnJTHwq8hsFt6OTsBjsRdqTpGSntsuzv2GZiJ9X74800DkQk6SiYm1Uk6NUCuVMNCL8SeDED2epvJ4Ex/n8lAPOZxW6f+tfn/58mbJ6gO7Vsj2mxb1wNtQbQBI742Af67Hj8vTOeO/HVIfR/gbVvt4XmT5ghx8GxDM9RkpiJ/mr1e6jxwdTN2nn6Wd6DWKwGv4RIghM3Ii+jlfHGEKv0vfviBSog+l66E1IzAZhS+uB0TbAT/9johBSSJsJU9uT2u82IEYWypexZAdPxusxVZQHgnxsQ== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JuAWy1IcIPEshsV8czPgvuRqxPi0HJBkk2JmOdC2ByY=; b=Qhdf9QetJJBL2NCuig77IyX1niUsioTVLw4+5oTSzIvG+uzhMtzaxP+Dso3uR52Y+uwOVKf0cF9Nt2o5odYMCSKkT4iw7FUCjkk5ZkdxcE8iP2Hbuo5bc+TokYNHAgsHCdXrkmnIa3IJzXIlCiXaWeMSu5U/V+k3RH1X6Kmu5eQ= Received: from DUZPR01CA0084.eurprd01.prod.exchangelabs.com (2603:10a6:10:46a::11) by AS2PR08MB9788.eurprd08.prod.outlook.com (2603:10a6:20b:603::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.15; Fri, 24 Oct 2025 20:22:07 +0000 Received: from DB5PEPF00014B9E.eurprd02.prod.outlook.com (2603:10a6:10:46a:cafe::78) by DUZPR01CA0084.outlook.office365.com (2603:10a6:10:46a::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.15 via Frontend Transport; Fri, 24 Oct 2025 20:22:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DB5PEPF00014B9E.mail.protection.outlook.com (10.167.8.171) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:05 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fjpZUYMhSqWPo4JToxn9KaM/1QdxN2G3/idJPtDzbAqFFWSTWuav1p5vtn2yaxa6s7xXGyQr7CbHPmZiHY9EEkp7okQ8hlp5FuXhd4cAMAw6hYp4QuS0dBsdBXUiX2pBFC/JoHBO61pEzXrMjy480/dXSk2o2/s4q82MAx8jjL0RXjMngVRDp2k5HGY2sg79gOn8HC5XZVk5h6NL2+PUZXs0xK1ZMB9jAkodhOh3dNFMcnqdSNoYT/JXR3/5pEwI2oPxGVNWWp/EBqryshcAWnyo090fk8glngXc9Hy84CLiOpClwSqptPvpLpBHdZ13nqHYzZgy4OLSEMWElbiOYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JuAWy1IcIPEshsV8czPgvuRqxPi0HJBkk2JmOdC2ByY=; b=VBujM0WjbCYZGw+F7+MYUH0CjdQZV1rESVxxb20UZUFqLsSaR7sNRafHxUAHfPjyO+Q894YY49G8m1wtc64Whrij01nRH4ZvhuESIGghY2GylH2EOMiYmnAt658P4b9jKPBerQyPqg44uD9UEnIAL+TvjV07uo3ojfYLM+fnvXxY8NRUYa+7v6v9TeKUNzkWueZs5hcOjvJIVDrXZj/0476lt/TLWp3N4zQt/ra9livmxLnXtFo3qJ8ywplz3gr+UW07jDQYJI6TmZ52CanFxVCCJjVQSuDcU9v5Rhqa85IKGRUvI/f1aAM2bbinGYoLYqWDrv/4Vj99R6f4B6FKIw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JuAWy1IcIPEshsV8czPgvuRqxPi0HJBkk2JmOdC2ByY=; b=Qhdf9QetJJBL2NCuig77IyX1niUsioTVLw4+5oTSzIvG+uzhMtzaxP+Dso3uR52Y+uwOVKf0cF9Nt2o5odYMCSKkT4iw7FUCjkk5ZkdxcE8iP2Hbuo5bc+TokYNHAgsHCdXrkmnIa3IJzXIlCiXaWeMSu5U/V+k3RH1X6Kmu5eQ= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:33 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:33 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] drm/panthor: Support GLB_REQ.STATE field for Mali-G1 GPUs Date: Fri, 24 Oct 2025 21:21:15 +0100 Message-ID: <20251024202117.3241292-7-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO3P265CA0026.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:387::9) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|DB5PEPF00014B9E:EE_|AS2PR08MB9788:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fa8b2eb-6227-4b34-8cb5-08de133affcb X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?i8kC9iPGhQa1etMtLL7ZDpJ39sC+/eDuYHCJrPiFRQARw56vuuErBNOXTuf8?= =?us-ascii?Q?bqeL6EVsofuVn6oNfagAWoEcanJM4V4uD6r9RjsxMezgGrJNzUqKxt2zlUiM?= =?us-ascii?Q?s3EH44+eIdw8hq2qrJd84GzwWHye3ePbbhN3dupUb0J6XmjfQHI2gFAwhZ6H?= =?us-ascii?Q?MlAXpGcisqwDFVsKh0RFBpoT0YSMtSNftuQm/qeLkiAdMpJ65LIVAynZyE9t?= =?us-ascii?Q?xR6ywJuTtWx/A19koQLz0EXap6Hx9+nQDugJI2SbkPjVDAWH8zrvb7n/E0Jj?= =?us-ascii?Q?TfFeKb9/RFqqpIqdGy/Eb1D7ZLe1Ed4SRNZ6FZW9lXkdDLoxvAAwdp6puOuJ?= =?us-ascii?Q?HOCS6KLiKNhVsOS4P8fiRH6j2c2vInKjX69tm+5PloDu4ZGIntSiuSzNurip?= =?us-ascii?Q?S6lh7pTvHATwebV2SVPkMIBbfVMaEpMJCkMProntmS4/AUiikH4ygt5c/oEg?= =?us-ascii?Q?mcchicbxUAU0E3xY22B5noU6g2K0zISFSTioBN76PEpEKTbmtwbHtGyvOOEw?= =?us-ascii?Q?+ZRueuNVnR3tmvypTFq1Dzz28MFRbaQlnOZBKQxHV40Qb298pt6O8NAdeF7N?= =?us-ascii?Q?b6FThoWtlx5VgBXhsNqN0A5WvozCOASIhp6bp+Wi2WxOo5XnmSKnBm7sV6/7?= =?us-ascii?Q?TAnI1sh1RcCP490UNvMpeENoFb+uxE3Jpzis24UQVDqD9UuWhdtzqXTmK4HD?= =?us-ascii?Q?nt43OPaeMZCMaSZxEjEUIjWcOyv4FLpQH01Y6bI0js8Kb9fqqstIxVaHdc0x?= =?us-ascii?Q?feUirzwv4gLra8xpVBF89Wd2IZBumC0sakROkk8CmB6FEc80Jp62LhZ4wV0A?= =?us-ascii?Q?zx+/nhNzMLK868qx4PofZB1rGMM/Utoc/NaHSa5nDUKkeAfqeR3yWuk2Dije?= =?us-ascii?Q?VtyCrbMW9BXT6F9HwcEwWbT2EIdDv6SryVF17JC57QIP1CIwkHx8KRW0DURX?= =?us-ascii?Q?gUyO6ongHriwg2JcjZjEw+XsisQRGPhgMfRUA/QogqfKCViwx+rHGaB7u8vV?= =?us-ascii?Q?UuIrIAuHe0H5J2ptCYK2kFZPtoLVOflU2RGSXp2UVaJIC6U3ENTmyDplmlnC?= =?us-ascii?Q?iksXU7t3ySt5rUFXKICohZ2o92aNBCBciRABvm+2u7BAoXRmUI5+ANz9oCNP?= =?us-ascii?Q?zo2+0wTAXaacF6xr9G2aNZJtJ9VYpVzW6Bzkr638RG+TZKWiwwVFZFDWHcQw?= =?us-ascii?Q?crS4Xr0q1k9TxPDfk2R/ie84y4Rd7OSM+na6K5VRDmbR9TGMbcQxWDI/hW2/?= =?us-ascii?Q?ANtg9Uih7Wgg8xV8ex8SxykTnmdbormEoCPC57QfV+7eOlyQJ7ocvNlCU3cW?= =?us-ascii?Q?1KnI+oYPgpSqpQ6CAMteMj1fJPJSXXiz0QEUcN8u4SHF990D7ef1vrZB90Fa?= =?us-ascii?Q?7Ji1kwiCdvIBobjW+/xR8mks1tVHUinNJHD4lLOcnlmwnwVzsgIFvT2zZ6Dv?= =?us-ascii?Q?YeWPP1Xak0KmEjL5hWSlUiAsHCQ2aLOK?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B9E.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 63281ab6-5202-4a8c-59f1-08de133aec78 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|35042699022|1800799024|14060799003|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?w+Eq6E710UQJ/dynnMi8ezqjYf+tQOixMfQgxzvP/AMeF0JBCHtk6FIhjJrn?= =?us-ascii?Q?BV3Bvg/3ELUVqEfFLSq65lFr3cvmrPcJ/iLiak/hzQZooHHS1lWx7TK2w5xp?= =?us-ascii?Q?kyKa/dCf0y2bybeo4GX4yXq2rnNG3gUgq41lepBfMwcdky1iTeDonOAgtvLl?= =?us-ascii?Q?ydniae1ER2aKpvNoTQt+hRmZnufKIluZvr+0FYTf65O8NP5Lw21kGC7mgdCe?= =?us-ascii?Q?YQWSsdBZyvVGs8rB3DzcB5RJePaHGZk9R23NReElr53Dy54oUsvyqk2f8Kf0?= =?us-ascii?Q?1O6HWw1np605WAXEIlGb1H7AczXtAoKGK5LMHmDvyd/szOZPvHrFmEzeB2VA?= =?us-ascii?Q?PidbfHoh/e1PLBbKIlga45kwxLz9j3l9AdNbNeRPBpQ5WwBbHaMzOIOoG5DU?= =?us-ascii?Q?j9DB0PTyVx4LUTO9dBs8P3JjojJy0tv0wRlMQP8LqIRifb3dDbsQsZpuXH9L?= =?us-ascii?Q?g2lH+L4Kxo4fvZ/7no8BEAVeOs6JEwi71sUN1a1Zaz2yc3ONEyi5UbzQBbyt?= =?us-ascii?Q?X0SdF8ZCiQXoZdliF16W7l7hZ9wgmNsq4ZhFLne3NFjil061jwJJBCIPeoAl?= =?us-ascii?Q?jc6k2pm5EowodhDO2n93V70YryzBPnTxQKasAxaRuXO+X4BXOYO6J4pjbrDd?= =?us-ascii?Q?mNCsIchm+UeoWUMFRWQxwNKwJpKKgmoNwkmZX0aKz8XQuCyIAVfuYAOjXEQm?= =?us-ascii?Q?H0vccSyQjnPOWZMSlFd4pe2BnzdxMUT9gNWzcm2Xa+jBorvsr5bOkkEfRkYf?= =?us-ascii?Q?lubZLnCZHTIJZ+0lTX5e/WFFFu5rgMPYWpzLfP0vODeYHaJeiMSvgacnyeyW?= =?us-ascii?Q?KpdD6hXL+YWgNd12gVaogkANs7GO2JsVHhlIHNrnCvgfUXLHullbUIw5Dixx?= =?us-ascii?Q?AaMaM4jgHCmlZnzBA1zW/R1JASI+mfnHvj5nWgbzSze3Z1rw6BtIJoUz40y3?= =?us-ascii?Q?wHDezb8J3qHq2Kc8SLm2Tiz8KRzaaFi2VIS3R3rnUYmcn0n4QgXaIHTmdkL1?= =?us-ascii?Q?HuD3e/zOeY5nV/7eS48CV39SvtW5BCnVaV13GQMGDLXmry1+YCBAsghEVmaj?= =?us-ascii?Q?93g0j52An88XQ4wFEGiKosDJOTHAcdmpkD4wpA+U140ubL7Kp3M1Z763KSTB?= =?us-ascii?Q?sDHqIm4mZCd4zTs6SxZYGNhYt5dmixmsU7a1raBnDml3BoKZF7S1BpXL9HGL?= =?us-ascii?Q?ErFC12lTzLHPOSWVyd4iXFQKx5IcBeUKvIttoWMppZJjJl9hfhuRyG3GH0vm?= =?us-ascii?Q?rP4AW19KUG1F6XjWGB/VmCfcAGlwGXqy/E0bj4InYZ2/j3NdK5JpfrY/qvmu?= =?us-ascii?Q?hHUxNXYzE7v3bkh6rQDpTjMXwk89M977N0PzZyE7gGLA0TDVHR7wjP7wBy+K?= =?us-ascii?Q?0IaBRiVRIl23NU+ACpzpMSinGqBqCJIqMsl+crA7R9+FgrF0L6vwoAc9hOkZ?= =?us-ascii?Q?K6m7axom2+KZkB6qcjqnMckal5aohuZGWE9Ez4b83dLgI8WAAZIpUo84WzGh?= =?us-ascii?Q?n3dRIgpiR8vHXFM7aPoxAsuDt2KNq7N4RyCBylUa09N1Ewg24sj++bhSTcVF?= =?us-ascii?Q?dBcGOIRtuRer/24vLW8=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(35042699022)(1800799024)(14060799003)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:05.2627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fa8b2eb-6227-4b34-8cb5-08de133affcb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9E.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9788 Content-Type: text/plain; charset="utf-8" Add support for the GLB_REQ.STATE field introduced in CSF v4.1+, which replaces the HALT bit to provide finer control over the MCU state. This change implements basic handling for transitioning the MCU between ACTIVE and HALT states on Mali-G1 GPUs. The update introduces new helpers to issue the state change requests, poll for MCU halt completion, and restore the MCU to an active state after halting. Signed-off-by: Karunika Choo --- v2: * Reduced MCU_HALT_TIMEOUT_US to 1 second. * Wrap the CSG_IFACE_VERSION checks for v4.1.0 with panthor_fw_has_glb_state(). * Removed use of undefined panthor_fw_csf_version() MACRO. --- drivers/gpu/drm/panthor/panthor_fw.c | 89 +++++++++++++++++++++++----- drivers/gpu/drm/panthor/panthor_fw.h | 7 +++ 2 files changed, 80 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 6b91c3cb6678..78f884ccb8b0 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -32,6 +32,7 @@ #define PROGRESS_TIMEOUT_SCALE_SHIFT 10 #define IDLE_HYSTERESIS_US 800 #define PWROFF_HYSTERESIS_US 10000 +#define MCU_HALT_TIMEOUT_US (1ULL * USEC_PER_SEC) /** * struct panthor_fw_binary_hdr - Firmware binary header. @@ -316,6 +317,13 @@ panthor_fw_get_cs_iface(struct panthor_device *ptdev, = u32 csg_slot, u32 cs_slot) return &ptdev->fw->iface.streams[csg_slot][cs_slot]; } +static bool panthor_fw_has_glb_state(struct panthor_device *ptdev) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + + return glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0); +} + /** * panthor_fw_conv_timeout() - Convert a timeout into a cycle-count * @ptdev: Device. @@ -995,6 +1003,9 @@ static void panthor_fw_init_global_iface(struct pantho= r_device *ptdev) GLB_IDLE_EN | GLB_IDLE; + if (glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0)) + glb_iface->input->ack_irq_mask |=3D GLB_STATE_MASK; + panthor_fw_update_reqs(glb_iface, req, GLB_IDLE_EN, GLB_IDLE_EN); panthor_fw_toggle_reqs(glb_iface, req, ack, GLB_CFG_ALLOC_EN | @@ -1068,6 +1079,54 @@ static void panthor_fw_stop(struct panthor_device *p= tdev) drm_err(&ptdev->base, "Failed to stop MCU"); } +static bool panthor_fw_mcu_halted(struct panthor_device *ptdev) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + bool halted; + + halted =3D gpu_read(ptdev, MCU_STATUS) =3D=3D MCU_STATUS_HALT; + + if (panthor_fw_has_glb_state(ptdev)) + halted &=3D (GLB_STATE_GET(glb_iface->output->ack) =3D=3D GLB_STATE_HALT= ); + + return halted; +} + +static void panthor_fw_halt_mcu(struct panthor_device *ptdev) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + + if (panthor_fw_has_glb_state(ptdev)) + panthor_fw_update_reqs(glb_iface, req, GLB_STATE(GLB_STATE_HALT), GLB_ST= ATE_MASK); + else + panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); + + gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); +} + +static bool panthor_fw_wait_mcu_halted(struct panthor_device *ptdev) +{ + bool halted =3D false; + + if (read_poll_timeout_atomic(panthor_fw_mcu_halted, halted, halted, 10, + MCU_HALT_TIMEOUT_US, 0, ptdev)) { + drm_warn(&ptdev->base, "Timed out waiting for MCU to halt"); + return false; + } + + return true; +} + +static void panthor_fw_mcu_set_active(struct panthor_device *ptdev) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + + if (panthor_fw_has_glb_state(ptdev)) + panthor_fw_update_reqs(glb_iface, req, GLB_STATE(GLB_STATE_ACTIVE), GLB_= STATE_MASK); + else + panthor_fw_update_reqs(glb_iface, req, 0, GLB_HALT); +} + /** * panthor_fw_pre_reset() - Call before a reset. * @ptdev: Device. @@ -1084,19 +1143,13 @@ void panthor_fw_pre_reset(struct panthor_device *pt= dev, bool on_hang) ptdev->reset.fast =3D false; if (!on_hang) { - struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(p= tdev); - u32 status; - - panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); - gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); - if (!gpu_read_poll_timeout(ptdev, MCU_STATUS, status, - status =3D=3D MCU_STATUS_HALT, 10, - 100000)) { - ptdev->reset.fast =3D true; - } else { + panthor_fw_halt_mcu(ptdev); + if (!panthor_fw_wait_mcu_halted(ptdev)) drm_warn(&ptdev->base, "Failed to cleanly suspend MCU"); - } + else + ptdev->reset.fast =3D true; } + panthor_fw_stop(ptdev); panthor_job_irq_suspend(&ptdev->fw->irq); } @@ -1124,14 +1177,14 @@ int panthor_fw_post_reset(struct panthor_device *pt= dev) */ panthor_reload_fw_sections(ptdev, true); } else { - /* The FW detects 0 -> 1 transitions. Make sure we reset - * the HALT bit before the FW is rebooted. + /* + * If the FW was previously successfully halted in the pre-reset + * operation, we need to transition it to active again before + * the FW is rebooted. * This is not needed on a slow reset because FW sections are * re-initialized. */ - struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(p= tdev); - - panthor_fw_update_reqs(glb_iface, req, 0, GLB_HALT); + panthor_fw_mcu_set_active(ptdev); } ret =3D panthor_fw_start(ptdev); @@ -1169,6 +1222,10 @@ void panthor_fw_unplug(struct panthor_device *ptdev) if (ptdev->fw->irq.irq) panthor_job_irq_suspend(&ptdev->fw->irq); + panthor_fw_halt_mcu(ptdev); + if (!panthor_fw_wait_mcu_halted(ptdev)) + drm_warn(&ptdev->base, "Failed to halt MCU on unplug"); + panthor_fw_stop(ptdev); } diff --git a/drivers/gpu/drm/panthor/panthor_fw.h b/drivers/gpu/drm/panthor= /panthor_fw.h index 6598d96c6d2a..a19ed48b2d0b 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.h +++ b/drivers/gpu/drm/panthor/panthor_fw.h @@ -214,6 +214,13 @@ struct panthor_fw_global_input_iface { #define GLB_FWCFG_UPDATE BIT(9) #define GLB_IDLE_EN BIT(10) #define GLB_SLEEP BIT(12) +#define GLB_STATE_MASK GENMASK(14, 12) +#define GLB_STATE_ACTIVE 0 +#define GLB_STATE_HALT 1 +#define GLB_STATE_SLEEP 2 +#define GLB_STATE_SUSPEND 3 +#define GLB_STATE(x) (((x) << 12) & GLB_STATE_MASK) +#define GLB_STATE_GET(x) (((x) & GLB_STATE_MASK) >> 12) #define GLB_INACTIVE_COMPUTE BIT(20) #define GLB_INACTIVE_FRAGMENT BIT(21) #define GLB_INACTIVE_TILER BIT(22) -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011063.outbound.protection.outlook.com [52.101.70.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D0922F0C79 for ; Fri, 24 Oct 2025 20:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.70.63 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; cv=fail; b=NgJd6iWHpW5kkth3m/Z7WDXS/IIaaDvenJSImPn5JYl1TZ9rDVBzALCiTm1QGrDuardQfuyN5AGoRhpI+ppcz7KV2lgPl5wuTfpvjDeXwP96NSQDTscK1TtMfPQb3ojQn0LaLCuF//sYEJD+vd69seMfTP7gdZndVQS2ctuKb8A= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337333; c=relaxed/simple; bh=sDcFqb2S0R1ny0eI8xCmGBPSG+rNFeJPdlsW3NxOoDI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=NfIlLxdrburTtedAv6ySw5mFGLcNNEssBAwKNjTG/fb+j+xSLUfsU7GcbnhntPshdt9Jq23b38sqo8vFfFrYX8U4e7NacDyWhL6YPA61mOzrQoCVCL1xDCfnsPhizQ+S8iOBNKU0Pwb94knNNp3+GVJseqh1OnLSc/UA33DZ+CQ= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GVmWY2HF; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GVmWY2HF; arc=fail smtp.client-ip=52.101.70.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GVmWY2HF"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GVmWY2HF" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=VrCjXNEnpazBd7ZBpmthhm7I+Pf2Gu2pJd6TSIOgaqwzkCcgYd7BncuhD1hS0obrs/D3eOXKE0cApppXjmlLv2C28gEOfieRey+75lgGStt4BzmZXgrMsaTEc9JtgP6q2vpPVv5r19Xs3neMDe6nbiIANTolXRTdbCb8a/ve6cmgJpo9fvLscRHr2LFp4ULc4rMqlfex1nX4CX5rrvSqdVEB/JWgMFKC8OOL2hheDtSpsu/y4MJpGkeJv+w5YcP4PQTnzJQyfx9CYJdglCtGNHl2+l5TN9jiBBigr+C+WrD1yCYi8iLTAEkCuUYSTJf7v9rWEd270KBwZyy2h+fHEA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k5NL/EgfbXs/bIdZ4tz5xHjeebkGV17pN2TlGBMmcgw=; b=K2EXGfOKEALKQBlnyeJ/aWIDqnPfIDFL5iwDJO2pU30uOmDpG8xpZrBJBFNQX8GUG9rQmAU3uXb5c5OQsVe+rySCplO3Okx/YOwPeGCOZO4rVkjePO1rPIjereS+6WQhZdtrIlDEbmXJL8dRjTEiBnDIXtbN3PBq8X23juolkB+NEH+nCEHDa9XDjPvuCLkwz0eFmWpQLvxmZ304ISgloqGLY7wnL5P9r428gNQlM0nYwY3dUCPwwQ+6yqXk2j2BGfgjK/DJS1pmB5kpAsLSWiKNIeN9L019W/6fiyZayIcYPDEBlDXgcVNM8pBRkoUqo+B3VoCa1tRRe5ngmyPjdw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k5NL/EgfbXs/bIdZ4tz5xHjeebkGV17pN2TlGBMmcgw=; b=GVmWY2HFgVjPA+0tSbH+o3u/Mr12DvrlTNI5R5QWnPlvAmIJMUyZKqzfaG3vyfJkMGHIYR/W7dUN+8qhM0Wdyk9itfCQgZ3ogvSlUq3nolX9eTv9mpW0UCtQje1NsOJQY5kRXPrOtIf63j8OC1EaL4KTWoSgJ4axswcj00tSNzE= Received: from AM9P195CA0018.EURP195.PROD.OUTLOOK.COM (2603:10a6:20b:21f::23) by PR3PR08MB5691.eurprd08.prod.outlook.com (2603:10a6:102:82::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.12; Fri, 24 Oct 2025 20:22:07 +0000 Received: from AM3PEPF0000A798.eurprd04.prod.outlook.com (2603:10a6:20b:21f:cafe::b) by AM9P195CA0018.outlook.office365.com (2603:10a6:20b:21f::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9228.17 via Frontend Transport; Fri, 24 Oct 2025 20:22:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AM3PEPF0000A798.mail.protection.outlook.com (10.167.16.103) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:06 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=M0SgYI+86ZcZM1KqHKLB9+a70xmjARkR1XXKdqaelPaR/oIN16fmLL/yIpuoJ/r18AI76jMQFNpdPhWr8J946BVFmZaSPxEuwFi5D3OLDd6qSYb7jYqOb5OQQ29qlXEsDGXAvmUbflnJgttLOxT8AmiycWfqjQgOSNcOxwDDcu8cJY+56uXZmlyJ9aS8/Vh0U/NSE9OjDK1mr1sM2TFga0F2GRiBFtWb3qLVPIEaQGnHiiWth+n2VqKdOrgwvDvB2+ffa4yqB/ETDL+7Wg0T6CXyMmwrV4z1b+tM8I/lJA3yiXxaBn2SS2orM2W/tAbAiiruqALWzQ++g0NqcF4lWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k5NL/EgfbXs/bIdZ4tz5xHjeebkGV17pN2TlGBMmcgw=; b=Ov62a8HQPmplbJg2PRQQF+OCKslzizdGdxEf4Vg1waWjXa3vvKZAR/Cyi96ldNr++ADw/KpBtesML43Jc3vCDohJnGVgIBuaijZQ32b8egdjdtyyLB8uKDVFRiy7bHyzi2UiYBTDz3fgr1bflEwtlBcsINcKRWFildpTC1D6sFuHBvmPxYJuM/dTVwaK3QgAPrrxqmZVDyVApp0wbc8cqMLry7hDSewTiXLnDDGNnGYGX390HRCZIvExI/AdLjx/2x6qqGO2/gryXGTu6Ib9Ohc2m7W/TQGwktbAgelpcBl42vkuv1WvEiV7ZH4fSi4A2sEevCPPK7otNq4q0fksiw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k5NL/EgfbXs/bIdZ4tz5xHjeebkGV17pN2TlGBMmcgw=; b=GVmWY2HFgVjPA+0tSbH+o3u/Mr12DvrlTNI5R5QWnPlvAmIJMUyZKqzfaG3vyfJkMGHIYR/W7dUN+8qhM0Wdyk9itfCQgZ3ogvSlUq3nolX9eTv9mpW0UCtQje1NsOJQY5kRXPrOtIf63j8OC1EaL4KTWoSgJ4axswcj00tSNzE= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:34 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:34 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] drm/panthor: Support 64-bit endpoint_req register for Mali-G1 Date: Fri, 24 Oct 2025 21:21:16 +0100 Message-ID: <20251024202117.3241292-8-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0389.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18f::16) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|AM3PEPF0000A798:EE_|PR3PR08MB5691:EE_ X-MS-Office365-Filtering-Correlation-Id: 42babff1-91da-46e8-126a-08de133b0098 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?EpQzFQfwQEVryZv3ODLdLwu0Zo7L3//VOyugyZCuhqY9qsq4WBj/bf6Slf5Y?= =?us-ascii?Q?YG4uaF6y/miVLFWYWiitVr0R/a4h7cmh0OWsuxOazMXXRfLCFFM+oIZqJ1bv?= =?us-ascii?Q?6jtMg0cnRNcbR+ywGj4TB9zwroOSgZmSYZvIm/DTvvNMQJQGH/BTPlCnoiBt?= =?us-ascii?Q?+649qyNCeIeMKUMuPFqbpCoyKmGWowtZK9oB7IKH/maOCoDhiQsai8ygt7Na?= =?us-ascii?Q?ByGYoK9B2cMMAnWRK4993G9nXqSb8UaTxutUl9VGi/5dcGF4aS9zNi5xcNhv?= =?us-ascii?Q?ZcMW2iAh97DarammMGEJqk5Ypep3B9CcNoip6xYx08W1ik0sXAHwoR+OhirJ?= =?us-ascii?Q?60skI/gWWhF0k051dH6v8PCyd6+Lt2uTpEFhMBrvhKVi4Wpw28E2yf/Flfby?= =?us-ascii?Q?ewTl/d7EyUJtfXLXFUN2j0zdUyTciUricha/KsHRK7YmZcTN1Ze8s6EXdPYi?= =?us-ascii?Q?jx/baBRW2OyaY212xpxr1U4DzSvGeEVEmHfguG/wtCRoKeVg+hwI6/JsScwj?= =?us-ascii?Q?aQCaxllejhWr7XkPLrW+g7uX5FqHdd+ZRBqr0Fhpx4UPqJvSjFjkrpzLhnkq?= =?us-ascii?Q?gi2VTdCgym4d6/AgYyNw3RbvQM1TZqPMI6ckRNDe8IZ+G5TBD3rYbVaWOcNF?= =?us-ascii?Q?23fb01f/h/zBzOt8q/uftTDhIT11TdTFi1i9Rwrhk8il2NaZQ/uik1+v+Klg?= =?us-ascii?Q?UuUnwy6eOzbhZXquLO1AvMoDvcFTlFPV5XT1cNKzIHTut/YlURL+/3P7yQpx?= =?us-ascii?Q?m8+HxhejoT0zq/V9CUW3Uz1bEfvbvQ9VJaUzmCsW0hnaYBdkdXivHfM3nsLj?= =?us-ascii?Q?eR0uDzp2PxLJJTJZDjDVaJ7WWiPDjyYoNvNDJTMsaHEB0WWLhw8xjL1GOxWV?= =?us-ascii?Q?ZStRTyb3GXYMb4ayfl3ocNO9eWMU61l3F4/23wY7o+333wxno8K8wzBbxjId?= =?us-ascii?Q?NbS/1afRiSF6MqNUuVxdGyJYLp8o2aOaFGTcYMdugiTUgKtdh1UF8IPAHsx8?= =?us-ascii?Q?Y7JcVV9LqM/a7Nj9+u8thDvbywARJqEyqsm3lsksIPfgEXk1Lp9yxeV1eH0p?= =?us-ascii?Q?vSRlr5SmgiDOnB8ovQ72frT6ER8nuXh1ruXmFrUB28aPlX++MPS0hRdRBctv?= =?us-ascii?Q?Xfp0aT0DNAVaM7DoV6u/rvUqzeYEZ+M4DjURZWrpIrCY8rHM2H48F5PwLuIX?= =?us-ascii?Q?AiFKRBIzvFYrx1K+sBXy6jmZmQqGrnpg4i5ybrh0A2QZC+qp2S2EM+E8zaae?= =?us-ascii?Q?R6aUcFrmCy1OPlEmyi73XGyxbuFw+6Fxd5hgNHeAHqowCHU32ocWp708DgJi?= =?us-ascii?Q?PrjFEpxGQ6zXqEFIIBiou+tIUVhcN6il/BehztAjxEa9JrkAlue8TBrFEpO7?= =?us-ascii?Q?85fMM025rqMmLPBfTQitsVRN49X20Iwq/IRqGkgGFIeF0nsTHnaSAedxQGPj?= =?us-ascii?Q?2Ff0KUxSdUDCUFI83dMwoB+oiSMOarEX?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM3PEPF0000A798.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: cc4a3649-e31b-4227-71fc-08de133aed47 X-Microsoft-Antispam: BCL:0;ARA:13230040|35042699022|1800799024|376014|14060799003|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?dzFPi0kz61D2c3BSiMrmlNjsoH+LIZ1UNIOrg4+e56UQTi0HpGLCGcisC0hL?= =?us-ascii?Q?elPujb32zI6luFe02XD3gyHB9hVOfDjBkYYKyJkrWX3RJ565UG7wSCzrG/XF?= =?us-ascii?Q?C1SNQwYBvTkEyOJTAlxGJ4G/aBQgTmdgf8LWH2T87V3oXpa8IQgtR+9P5d2R?= =?us-ascii?Q?GnxuLUG1M24bc/8ZxTxOfy6DKtciwh29p6fuPIKU3lxgTvrZ6SEY0HOFaH1K?= =?us-ascii?Q?qL1JZAEAO8SUt5o6ZGcH+4FsKwsbGmnrNs7bUf/nPXxLQ7LW8kO1uWBwGTGe?= =?us-ascii?Q?3mZOzsvxPqRB/NIRW5M+D5LqGxTcrBbRrv6JpHTOHHjdstEBD5uX23wTBam0?= =?us-ascii?Q?/RbxkogziVTyNa/ryOD/LLPJ3VhQo7YJ1Te56ng/eJumzg1WHBsoCdLgqASI?= =?us-ascii?Q?MovQ9vIjPS9royC2siJMixpCRPVjs/5v8ub6qQt2QwNvilLnys0u8++BCcww?= =?us-ascii?Q?QpYUbrRNYKQbQg6gL3k4FOBGEQRkhv7fz6F/Vy2ySdRl0QVzWRCXFmeG0zu6?= =?us-ascii?Q?E+0AOyPCSC2nxJ8ZYkmrhoRiGL7jclTwdRgMv+sYRJ8v93SUmXpbB3EQ6yz8?= =?us-ascii?Q?lqhoPMqJtViEMIunUM4TUyTX/OZpWLlMcMaybriNGY4X6U5DD6SF5hBkMUGa?= =?us-ascii?Q?GcMxWFTcxF+R5NttevR95XFCQDPhw7qB8TUp1qcIeiG1LOKCpcDbJrSApRaM?= =?us-ascii?Q?WkPfNN8M0hfFZdwQEKwaqSuC+NEgbUaJqO8C1XTXrodNBTMBQnHyWTQq7z/8?= =?us-ascii?Q?xlkCX5cxHrkS91fN5/oSpjjUGBOMKnDMWYh9HUWKuFF5AJ3TAs54C94xZ41Y?= =?us-ascii?Q?O61ePX2XNayi4O0dCMuV71lu6ACKQxXaD23DwtMU7aRIveZ5JHAER+C2jaOS?= =?us-ascii?Q?SkLZsUOZ6iedvxPc+HOZcqb5/l4Ej/Rc01NUGgQyDOVfdSmNs5gvc8vRc3G2?= =?us-ascii?Q?a989CVnoai9izfHh/OnVGJjXcjbu9aJ0LL6Poi8vSPsiIAgKl3iO8M1caFT7?= =?us-ascii?Q?RYD2Pm0DacJvbcScvKZ9E/wgegqDuJX7Jce1P4WKlfzoKNGtoTC9WK6pKfbU?= =?us-ascii?Q?dUvVPaM2GDhBLUBaFVZGqt+hQvAx9U4+yEIChEXa4b5LXYigtNBXBQZX4KXN?= =?us-ascii?Q?lXR6uJqUI9ddTNqKWD25aUi9StvHy9BFjp+k8P+zOTfNaGfAVgSJXnVgvcLe?= =?us-ascii?Q?aqmmkVS2lJm6TotSMci8IIQSqrTg4HtTBdD2YXOLPJJzp6QLZss+c3ycU2cr?= =?us-ascii?Q?c2HXTVy/BEZed2wpr3YD0qUx1XKigN3hKLhds5kyqkkCG2rszdhDSaqZexNy?= =?us-ascii?Q?Bl97Ax9zX1K3YDJ3W9JiDAvj2yldFdfw4eMYZxNOq1Aa4lZ2Ku52WgllgsLZ?= =?us-ascii?Q?2YAVtXrumA3nop8KFdzgIuW7AWdeBdVzBm3JztxHsJ6TQwScGjt2RXSSLXde?= =?us-ascii?Q?zb48JzXfnbVUNQIl+g/nwhC3f7MxjZ6bsoYp2AmLAlBFJNfhVbtZNh/LqZHG?= =?us-ascii?Q?0J29wVtZEqdfSSumBPGHNG9I3vWVaI8W/AaIds+CznFBDTBAY+tx2nWPpJmI?= =?us-ascii?Q?GGVeG6FwGCAjlUn9IIw=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(35042699022)(1800799024)(376014)(14060799003)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:06.6103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42babff1-91da-46e8-126a-08de133b0098 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A798.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR08MB5691 Content-Type: text/plain; charset="utf-8" Add support for the 64-bit endpoint_req register introduced in CSF v4.0+ GPUs. Unlike a simple register widening, the 64-bit variant occupies the next 64 bits after the original 32-bit field, requiring version-dependent access. This change introduces helper functions to read, write, and update the endpoint_req register, ensuring correct handling on both pre-v4.0 and v4.0+ firmwares. Signed-off-by: Karunika Choo --- v2: * Wrap the CSG_IFACE_VERSION checks for v4.0.0 with panthor_fw_has_64bit_ep_req(). * Removed wrongly included code from previous patch. * Reordered CSG_EP_REQ_PRIORITY_GET() and CSG_EP_REQ_PRIORITY() to reuse CSG_EP_REQ_PRIORITY_MASK definition. * Updated panthor_fw_csg_endpoint_req_*() functions to accept CSG iface structure instead of a CSG id. * Update endpoint_req variables to u64. * Minor readability and code quality fixes. --- drivers/gpu/drm/panthor/panthor_fw.c | 36 +++++++++++++++++++++++++ drivers/gpu/drm/panthor/panthor_fw.h | 25 +++++++++++++++-- drivers/gpu/drm/panthor/panthor_sched.c | 21 +++++++++------ 3 files changed, 72 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 78f884ccb8b0..9ba10ab1d7c0 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -324,6 +324,42 @@ static bool panthor_fw_has_glb_state(struct panthor_de= vice *ptdev) return glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 1, 0); } +static bool panthor_fw_has_64bit_ep_req(struct panthor_device *ptdev) +{ + struct panthor_fw_global_iface *glb_iface =3D panthor_fw_get_glb_iface(pt= dev); + + return glb_iface->control->version >=3D CSF_IFACE_VERSION(4, 0, 0); +} + +u64 panthor_fw_csg_endpoint_req_get(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface) +{ + if (panthor_fw_has_64bit_ep_req(ptdev)) + return csg_iface->input->endpoint_req2; + else + return csg_iface->input->endpoint_req; +} + +void panthor_fw_csg_endpoint_req_set(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface, u64 value) +{ + if (panthor_fw_has_64bit_ep_req(ptdev)) + csg_iface->input->endpoint_req2 =3D value; + else + csg_iface->input->endpoint_req =3D lower_32_bits(value); +} + +void panthor_fw_csg_endpoint_req_update(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface, u64 value, + u64 mask) +{ + if (panthor_fw_has_64bit_ep_req(ptdev)) + panthor_fw_update_reqs64(csg_iface, endpoint_req2, value, mask); + else + panthor_fw_update_reqs(csg_iface, endpoint_req, lower_32_bits(value), + lower_32_bits(mask)); +} + /** * panthor_fw_conv_timeout() - Convert a timeout into a cycle-count * @ptdev: Device. diff --git a/drivers/gpu/drm/panthor/panthor_fw.h b/drivers/gpu/drm/panthor= /panthor_fw.h index a19ed48b2d0b..fbdc21469ba3 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.h +++ b/drivers/gpu/drm/panthor/panthor_fw.h @@ -167,10 +167,11 @@ struct panthor_fw_csg_input_iface { #define CSG_EP_REQ_TILER(x) (((x) << 16) & GENMASK(19, 16)) #define CSG_EP_REQ_EXCL_COMPUTE BIT(20) #define CSG_EP_REQ_EXCL_FRAGMENT BIT(21) -#define CSG_EP_REQ_PRIORITY(x) (((x) << 28) & GENMASK(31, 28)) #define CSG_EP_REQ_PRIORITY_MASK GENMASK(31, 28) +#define CSG_EP_REQ_PRIORITY(x) (((x) << 28) & CSG_EP_REQ_PRIORITY_MASK) +#define CSG_EP_REQ_PRIORITY_GET(x) (((x) & CSG_EP_REQ_PRIORITY_MASK) >> 2= 8) u32 endpoint_req; - u32 reserved2[2]; + u64 endpoint_req2; u64 suspend_buf; u64 protm_suspend_buf; u32 config; @@ -464,6 +465,16 @@ struct panthor_fw_global_iface { spin_unlock(&(__iface)->lock); \ } while (0) +#define panthor_fw_update_reqs64(__iface, __in_reg, __val, __mask) \ + do { \ + u64 __cur_val, __new_val; \ + spin_lock(&(__iface)->lock); \ + __cur_val =3D READ_ONCE((__iface)->input->__in_reg); \ + __new_val =3D (__cur_val & ~(__mask)) | ((__val) & (__mask)); \ + WRITE_ONCE((__iface)->input->__in_reg, __new_val); \ + spin_unlock(&(__iface)->lock); \ + } while (0) + struct panthor_fw_global_iface * panthor_fw_get_glb_iface(struct panthor_device *ptdev); @@ -473,6 +484,16 @@ panthor_fw_get_csg_iface(struct panthor_device *ptdev,= u32 csg_slot); struct panthor_fw_cs_iface * panthor_fw_get_cs_iface(struct panthor_device *ptdev, u32 csg_slot, u32 cs= _slot); +u64 panthor_fw_csg_endpoint_req_get(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface); + +void panthor_fw_csg_endpoint_req_set(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface, u64 value); + +void panthor_fw_csg_endpoint_req_update(struct panthor_device *ptdev, + struct panthor_fw_csg_iface *csg_iface, u64 value, + u64 mask); + int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_id, u32= req_mask, u32 *acked, u32 timeout_ms); diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/pant= hor/panthor_sched.c index 0cc9055f4ee5..d6f5efc10312 100644 --- a/drivers/gpu/drm/panthor/panthor_sched.c +++ b/drivers/gpu/drm/panthor/panthor_sched.c @@ -1139,11 +1139,13 @@ csg_slot_sync_priority_locked(struct panthor_device= *ptdev, u32 csg_id) { struct panthor_csg_slot *csg_slot =3D &ptdev->scheduler->csg_slots[csg_id= ]; struct panthor_fw_csg_iface *csg_iface; + u64 endpoint_req; lockdep_assert_held(&ptdev->scheduler->lock); csg_iface =3D panthor_fw_get_csg_iface(ptdev, csg_id); - csg_slot->priority =3D (csg_iface->input->endpoint_req & CSG_EP_REQ_PRIOR= ITY_MASK) >> 28; + endpoint_req =3D panthor_fw_csg_endpoint_req_get(ptdev, csg_iface); + csg_slot->priority =3D CSG_EP_REQ_PRIORITY_GET(endpoint_req); } /** @@ -1303,6 +1305,7 @@ csg_slot_prog_locked(struct panthor_device *ptdev, u3= 2 csg_id, u32 priority) struct panthor_csg_slot *csg_slot; struct panthor_group *group; u32 queue_mask =3D 0, i; + u64 endpoint_req; lockdep_assert_held(&ptdev->scheduler->lock); @@ -1329,10 +1332,12 @@ csg_slot_prog_locked(struct panthor_device *ptdev, = u32 csg_id, u32 priority) csg_iface->input->allow_compute =3D group->compute_core_mask; csg_iface->input->allow_fragment =3D group->fragment_core_mask; csg_iface->input->allow_other =3D group->tiler_core_mask; - csg_iface->input->endpoint_req =3D CSG_EP_REQ_COMPUTE(group->max_compute_= cores) | - CSG_EP_REQ_FRAGMENT(group->max_fragment_cores) | - CSG_EP_REQ_TILER(group->max_tiler_cores) | - CSG_EP_REQ_PRIORITY(priority); + endpoint_req =3D CSG_EP_REQ_COMPUTE(group->max_compute_cores) | + CSG_EP_REQ_FRAGMENT(group->max_fragment_cores) | + CSG_EP_REQ_TILER(group->max_tiler_cores) | + CSG_EP_REQ_PRIORITY(priority); + panthor_fw_csg_endpoint_req_set(ptdev, csg_iface, endpoint_req); + csg_iface->input->config =3D panthor_vm_as(group->vm); if (group->suspend_buf) @@ -2230,9 +2235,9 @@ tick_ctx_apply(struct panthor_scheduler *sched, struc= t panthor_sched_tick_ctx *c continue; } - panthor_fw_update_reqs(csg_iface, endpoint_req, - CSG_EP_REQ_PRIORITY(new_csg_prio), - CSG_EP_REQ_PRIORITY_MASK); + panthor_fw_csg_endpoint_req_update(ptdev, csg_iface, + CSG_EP_REQ_PRIORITY(new_csg_prio), + CSG_EP_REQ_PRIORITY_MASK); csgs_upd_ctx_queue_reqs(ptdev, &upd_ctx, csg_id, csg_iface->output->ack ^ CSG_ENDPOINT_CONFIG, CSG_ENDPOINT_CONFIG); -- 2.49.0 From nobody Sun Feb 8 12:43:03 2026 Received: from AM0PR02CU008.outbound.protection.outlook.com (mail-westeuropeazon11013054.outbound.protection.outlook.com [52.101.72.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 297712F362F for ; Fri, 24 Oct 2025 20:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.72.54 ARC-Seal: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337336; cv=fail; b=mQUGiISnb8M0LAlEY6t6f/qnkYZfrIGhidzb+s0sdKEkeKmjHajclnXqs/+wgh4KTg9vNY3yh5wbbKBnFwLGoNCmZ3Twt7OztjQoECsz7VqdqbVBjObrfvihHcjVWXPoloAcSmazO25SsOExuh00XghzGIeMCTnOq5f91EqIG9w= ARC-Message-Signature: i=3; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761337336; c=relaxed/simple; bh=k6dyhztKv9fTa3I6SerC6Ado+vgeflcqLK70HRkF3Fk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=VvhkjIZuMop0X/uDZECZqMhKtRQspp1GLImT5++HfmJtvF/A4O2nyrcxGxY0xDtno2CCTjlPy3xjxrZhVjW2FA8XueNJpl3Qt+Vaz5erbJrVi66IBhyjGe8noj914BwRln5Va7OP/vAbRYTuBFDafgqu5PBiT52qr1gsefI11T4= ARC-Authentication-Results: i=3; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Re9SC8Z/; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Re9SC8Z/; arc=fail smtp.client-ip=52.101.72.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Re9SC8Z/"; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Re9SC8Z/" ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=deM+9k7/C2bWhwPq3mCleNJtJ4DShZmZJYVdkKuZiGyox40G3S+WDUUDnOXYxQmjJK8NqRuLKs/Itvf1PKyQJf+Ts+YikaY41uV0rPwYoKlc5a6uvSaDeyCpo/zfJXZnixhri0/DaUeRFy0ci3eToJYKrg3gUhx66KAbdt7SwHA4afYiL8aPNC4Xbrz5td6EBK67iXgFVVqzRhS3LkLK3GZjSn2b1056SszXs+xmSoug++DyrSTSFNWy0we5ZwWe88QdzfRcG8SLcD2R/0r8bD0JQ17HC3OeDoP2sXhYek1QEYQ0ekJdodvyqvz+CVdAwPey4re+iYvYLvAo+qvveA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uCDRmdbdCbdECXFPwUHuHAZk/hnTwJlbnZbnB2pkvtY=; b=LMNKZ1ws1eOWldA9/iXOpb7k5OoVtMBObQ2wU/Pp0zqc4FgIRTd1yEhPg61J8aucPyhwCBgKz3gs+2sAdM8sauu1E2xpmf6yMAbSw9EdZivSx2/jUpWGaF2pVuPCgCyrWyHWqjFzYo+F6rSo0Q43Bu2QYd1/ixqu8jHksw+lnz1BxokWz+YFAjYEIJI27v2vsrzdeFjcnX4JODyscf6Bbq4r0+NXLPwgVGXqlqCSCdAfcXnDTDQYcq8gO6i3008/97Suh+Z38LMBE/FniG7RwKd+t50I4tcc0vJbIhZwAEvBsTKetKZzyKYo71/lavtZjOwKA/yHvcFFyMGvgzKRjg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uCDRmdbdCbdECXFPwUHuHAZk/hnTwJlbnZbnB2pkvtY=; b=Re9SC8Z/thdF77xWTGIiw1BDtJRuMdA1Um9vyVTaaRfNsTX24grf4RM9mJNwFQTdvjbe0JQ5nby72P8IaCWmD71kKOsItTdrQe4VrRJHhdGyLJjcWtkZuv2a+WGeJvcD34kNe7zcG5di980eLHFXLUGz+5JlEVrwwPHkbn4M2/A= Received: from AM5PR0601CA0074.eurprd06.prod.outlook.com (2603:10a6:206::39) by AM0PR08MB5411.eurprd08.prod.outlook.com (2603:10a6:208:181::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:22:09 +0000 Received: from AMS0EPF0000019D.eurprd05.prod.outlook.com (2603:10a6:206:0:cafe::a2) by AM5PR0601CA0074.outlook.office365.com (2603:10a6:206::39) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.15 via Frontend Transport; Fri, 24 Oct 2025 20:22:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AMS0EPF0000019D.mail.protection.outlook.com (10.167.16.249) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9253.7 via Frontend Transport; Fri, 24 Oct 2025 20:22:08 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tSSx9W6RhqY/6xjFGT+fD7GBIy8i15xvLk3xgyNU/vdfNvwU3m9SzCF9w5NangPZGw/H8rB+A7XQA/xMHKE++bOc3EuZ8Wojk523p10Dl9tnWRgGMtC3iylEgiZx/e5YzpvKDrG5/Qod7z+mIzKYTFI0iJCKtj7wAXAVHXnU2Ly5LsCFSL/V42ZkRnicB0iMxLlEQztsBSjHAZCz3acdXtTOGPWTMajCPMjkgQxaW3ak7fG7Tp5MPVhXDTN/2/h2l51EoAl0pTc01DlyARE2LnyvCteh9ByBm1BWr589/Y0sxFLkXUNHH8V0X/h5g+LwSWqn4+vQhfVVpzRkyvalxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uCDRmdbdCbdECXFPwUHuHAZk/hnTwJlbnZbnB2pkvtY=; b=qVEueNB3rOpHveMWXZ6HeoYWIOJj5OcVreCsF500n0TaFO0H/RALgFAKBtwFKENdDmFQauJFOupuL8ykEmxyAJyXICVRzQzgXY5DsaW0TFL9U/lcei7uH5QIqG/5+5cSRVA+fIh1861Ve3pTHSF3ZTWcNZwD/gfaBWE4yRvchKqZ1WtREhRXsqhX23jwEbLTQxrZGoY6mdUpe6xbR0RwaFRuRI1Q8DsF2tjmZRbQGT/UCbF+0X1Nt+ysjFytr34t3VgDohQaa+gPSdViwKPHRdJDKEgqGgVcOpkOBSQVC0Lv8rxr/+OG5FUOp64xgDxMAjeN71DQBL0mi2A+DeI0fg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uCDRmdbdCbdECXFPwUHuHAZk/hnTwJlbnZbnB2pkvtY=; b=Re9SC8Z/thdF77xWTGIiw1BDtJRuMdA1Um9vyVTaaRfNsTX24grf4RM9mJNwFQTdvjbe0JQ5nby72P8IaCWmD71kKOsItTdrQe4VrRJHhdGyLJjcWtkZuv2a+WGeJvcD34kNe7zcG5di980eLHFXLUGz+5JlEVrwwPHkbn4M2/A= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) by DU0PR08MB8929.eurprd08.prod.outlook.com (2603:10a6:10:464::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Fri, 24 Oct 2025 20:21:36 +0000 Received: from VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74]) by VI0PR08MB11200.eurprd08.prod.outlook.com ([fe80::d594:64a:dfc:db74%7]) with mapi id 15.20.9253.011; Fri, 24 Oct 2025 20:21:35 +0000 From: Karunika Choo To: dri-devel@lists.freedesktop.org Cc: nd@arm.com, Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] drm/panthor: Add support for Mali-G1 GPUs Date: Fri, 24 Oct 2025 21:21:17 +0100 Message-ID: <20251024202117.3241292-9-karunika.choo@arm.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20251024202117.3241292-1-karunika.choo@arm.com> References: <20251024202117.3241292-1-karunika.choo@arm.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0516.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:272::9) To VI0PR08MB11200.eurprd08.prod.outlook.com (2603:10a6:800:257::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VI0PR08MB11200:EE_|DU0PR08MB8929:EE_|AMS0EPF0000019D:EE_|AM0PR08MB5411:EE_ X-MS-Office365-Filtering-Correlation-Id: b0fc139d-1b90-42c5-9257-08de133b01a7 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?KAOA6C/2jx0e0XpjgNcpVYlbLxpW7PBdK2hJqSbedMp0KsHKwsEyEnmvoBIM?= =?us-ascii?Q?ViTlXu07S0ASSmbxtpQxoquFsBziHnSPjlp6QfylYBWlbMda1oHWTVhT2xdA?= =?us-ascii?Q?aF1I8rrGj6iJO/T1A6hpx0PbGR4Krf1AbFi/iE1/QT+3Xyo9zhQBgaYgE0/r?= =?us-ascii?Q?g0J26D+j7fhvtcbUbaYuQY6PELAyd5SYmqGTAigXSL3vKIFFux1KoE9UmuoE?= =?us-ascii?Q?zAR/ac8bVKutwv680nj+2FJCdi21+HMBcOVGfC6LCqLzNaU+IKVQIeEUR7ah?= =?us-ascii?Q?O+UT6zh+rOs0tWBtf5YPo1vVjumJfQpT+U+63sDRvCyyqMOEJ/GEsdajvxw9?= =?us-ascii?Q?id7qqXg44gfFkRAz5S3SLUc2gkeE+0VfDqqDX2vn6LoR4o6aACcGPLhQs9If?= =?us-ascii?Q?MnCkQdEIY9FOIHxLqRYu0W9+2KKZWKfJWxseDg0QQ7hAv3PuwXUA9GMy3xiK?= =?us-ascii?Q?hGUTgSty3lWT2LjZ2HtR7q/aOVbx/TytJNrtSx9TRABrYpp0HiZE/tkQjODH?= =?us-ascii?Q?B6hpBquY7TdOhNfhmmU77Ff48/8+BlWEQ30/R5k9QlLYconLvCtP2/Afb2B+?= =?us-ascii?Q?oG/89myMvOH+31VsQ4h4/RC1/AH7CuPnVLhBTRvuOkAGRrh3IF89kkTs8Na3?= =?us-ascii?Q?/mS2EtLPsvDSZc7YmLn+nounKEiBeaO+02MAgZzFBMcwbWN4VSr590MLaSYN?= =?us-ascii?Q?DX+7t/F1w06qSS89Qdi+Y1lVGPmDbczx1+alPRCXRMMugbBFdkwH2Q9DTbZB?= =?us-ascii?Q?4QBcmiDhY2EY2rrgfU7zi82qD9xJui5i143X9F7GdWKTQu9+vqoCzRSODmx1?= =?us-ascii?Q?KW3zktVp+pxW6I2to2uU8LOgVesZywwBir41zQi5cAZC7hKUveiJ9lCKM+HZ?= =?us-ascii?Q?L2aDMh61lVWnN7CwIa25dQ+B7PsCrzRts6Cfm2bZqLML7/zjulkpGQtqcgfZ?= =?us-ascii?Q?rYX/Rr6q2OVVp5D9Z5M7UmH5+fmZX/U3HQoR2Lm8x/Rbt0wcSNN/5K0KyCKD?= =?us-ascii?Q?wrBFebUjl8htBI2+O6Y9kYoEBDwGof4hwpJFWZ9oXNx9+FOhitfcULWPRgrP?= =?us-ascii?Q?HYIOK16MV5jqav8B44ks15aj1MLZavid8KCm+NljkBktJURAxdE8uREATQJS?= =?us-ascii?Q?BawhAXOi3mm7GERSsSeNHkpBG/om1dM4PY4LEN5njeQbFq7QNleLuoOw2nrg?= =?us-ascii?Q?O+HMXyn2CjUZddOUs9YDqLjc2lsRzVI7mXGZ54pfiqyiOhUkcQ+XfSgRTi28?= =?us-ascii?Q?/UA5/1vBkmpUVAN1/n/WZUB4PZ4FY9iU+dzAS94ZPNNt4lnVPa1IwUSkaCts?= =?us-ascii?Q?EaWKInOX6Nvu4XFcoN1QJ4cXtprSbKPo6m/8zSnf0UKDI5ReZce8x7RNK1Bj?= =?us-ascii?Q?eEPZ5AsE6D26vBtyQjojeV6INuxHbiLjxAJX4vGz/RuDHdHsGwqQzFTrYQkX?= =?us-ascii?Q?iPXViVendjzXFYt+qZKHxflyfZ8ZRZuY?= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI0PR08MB11200.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8929 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS0EPF0000019D.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 68866de7-213b-4442-9809-08de133aee13 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|35042699022|82310400026|14060799003|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DdlDKI7S2rvVp/Y76DluFLQ/Aab2JLvCXJlrRD45alk0cUg/uUM3EXilR09X?= =?us-ascii?Q?5366iUdghtKY9xc9bl9ag6a7c1QU3yjW6dF7/5pkXR+++Z04eNceudvskZ4c?= =?us-ascii?Q?I0puHlXDG5OS1DI3gBW7pm1pQjcBv39bA9iKiUynboo2iLyQaOQcB3mkaBa9?= =?us-ascii?Q?fK+X2PSnkIo78CiYJrFrwsJKJUGWHi8cIxIEqR9TR2+ccY6EOrJegAVT667g?= =?us-ascii?Q?azOGlwAQ6VohnozVxfZsLdAcV6UGDrWpsYJ1SL4eh1C/Q+Ew4zLnlM+tVJbK?= =?us-ascii?Q?PQmZho5xFo3J35d3VxYnz5vBb0rMYvlvy61+RKNQuM5CN0cK9525m1l/LNLe?= =?us-ascii?Q?cBafKflFqdCBkHneWuWuLUr5e2Rx2oO2pxQ9C1XuV9D8gTGdg5GUwrT9w1XJ?= =?us-ascii?Q?Im0v+Hxrj458lzH+mTi99+QRYcvfKH+/B3qX90RMwT7Mn2K8T1TgVv6M6EY9?= =?us-ascii?Q?SsKQ+4chXa0USa61jg5d/Pb1KLyuaU/Z8fGIrrNa5FAKOig1/SkK3Bc9Mxd7?= =?us-ascii?Q?aoU6zIODHPKADcHAeqCCLXGQEqgh0C8gZEYk8j2NXL1nO9SHKCbJ2+v0HFgb?= =?us-ascii?Q?tglAX+tPcpQPur2eykgDiiM73fy30AxfWimBPY4ADYoPtYTQiqzzhww0kzBH?= =?us-ascii?Q?CLkQCtxQO8FLdAutqUNa+GFoOwufcbZa4PBVOveXvaVIk4rB0aPxgV+SxSKy?= =?us-ascii?Q?8Pp0eLZCc7UIme4j+ObqgN8jchxPkh9GaWhzDEiEgneqdv9O8zPG5zf1K829?= =?us-ascii?Q?S1qWnUYDXTKaRRpiMWaXATLCSiZrHHba++EsbGgMK1CRM6Im0+UFAdOB1vqZ?= =?us-ascii?Q?VwaltrTO5iU6JEiKrupZP8XRsTTGEBKwCgL5P3On+hnu+oEb1T/93jpZ+9vl?= =?us-ascii?Q?2fqM/H5JMimGcZEr7mKlhoBmFVLezdqVjFXcPJTGndWIIjKIgrxuYGt7DcNK?= =?us-ascii?Q?tEdY0KWaViKldInrj6yliU5s8FtUYNqLKuZuPsOqzhnRAqf50u3mtIeloiMd?= =?us-ascii?Q?oc4qU6/1ADn9RRV532pNYCUv/DS/niRYVFAYaPqVP3Aa7G48HkqnYOtL52HJ?= =?us-ascii?Q?+WmRVczCfbvZQFYG+kWYYBu6nrzpzDAxu7UH8yVT2uWXJGD8srF5S1cnu8K5?= =?us-ascii?Q?6vITJuafSJZ/NsIfrZFr/Yfo5RWVnwv5rZr51vNIYUdMpIPgnJktyksX6p30?= =?us-ascii?Q?82ZY0Xtu4YNIFjO0cB9LMAC/FcyVZypNHC6INMizjcOs074ne6deJCl+1RZC?= =?us-ascii?Q?MJsqKUEar41QL/MRFfXSYHgfaOkt+qqoxPwOOy2st+JiXsm5AG/MrikulUTT?= =?us-ascii?Q?wB9j8rmqBc4yF33iKSIcVRBpmzIA8C3s0pUwJPAo74XV1Jj4mRFnsp0QFDIO?= =?us-ascii?Q?8EcvthDOacjQn564ny/om7wtV/HkIFDiKwV37BC9MyEB3yh3GK++FkdczEa3?= =?us-ascii?Q?lYfY/x4Xmgoc1xgQeCD9EEpPBpjmoUfkVbtat8Yy86wbjrKIDfKbPLQZy4NX?= =?us-ascii?Q?MsC737XpeiV/11UiZo0Xn5y6yBAJp2NJwBAJxdzeVWUfEG6ONt0W1/wm9Bge?= =?us-ascii?Q?H84IUbwBoNi41A6lmzw=3D?= X-Forefront-Antispam-Report: CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(35042699022)(82310400026)(14060799003)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2025 20:22:08.4072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0fc139d-1b90-42c5-9257-08de133b01a7 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF0000019D.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5411 Content-Type: text/plain; charset="utf-8" Add support for Mali-G1 GPUs (CSF architecture v14), introducing a new panthor_hw_arch_v14 entry with reset and L2 power management operations via the PWR_CONTROL block. Mali-G1 introduces a dedicated PWR_CONTROL block for managing resets and power domains. panthor_gpu_info_init() is updated to use this block for L2, tiler, and shader domain present register reads. Signed-off-by: Karunika Choo --- v2: * Removed feature bits usage. * Check panthor_hw_has_pwr_ctrl() to read the correct *_PRESENT registers instead of reading reserved registers on newer GPUs. --- drivers/gpu/drm/panthor/panthor_fw.c | 1 + drivers/gpu/drm/panthor/panthor_hw.c | 35 ++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 9ba10ab1d7c0..031d23166c18 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -1500,3 +1500,4 @@ MODULE_FIRMWARE("arm/mali/arch10.12/mali_csffw.bin"); MODULE_FIRMWARE("arm/mali/arch11.8/mali_csffw.bin"); MODULE_FIRMWARE("arm/mali/arch12.8/mali_csffw.bin"); MODULE_FIRMWARE("arm/mali/arch13.8/mali_csffw.bin"); +MODULE_FIRMWARE("arm/mali/arch14.8/mali_csffw.bin"); diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 09aef34a6ce7..29c7a6e60300 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -3,6 +3,7 @@ #include "panthor_device.h" #include "panthor_gpu.h" +#include "panthor_pwr.h" #include "panthor_regs.h" #define GPU_PROD_ID_MAKE(arch_major, prod_major) \ @@ -28,12 +29,25 @@ static struct panthor_hw panthor_hw_arch_v10 =3D { }, }; +static struct panthor_hw panthor_hw_arch_v14 =3D { + .ops =3D { + .soft_reset =3D panthor_pwr_reset_soft, + .l2_power_off =3D panthor_pwr_l2_power_off, + .l2_power_on =3D panthor_pwr_l2_power_on, + }, +}; + static struct panthor_hw_entry panthor_hw_match[] =3D { { .arch_min =3D 10, .arch_max =3D 13, .hwdev =3D &panthor_hw_arch_v10, }, + { + .arch_min =3D 14, + .arch_max =3D 14, + .hwdev =3D &panthor_hw_arch_v14, + }, }; static char *get_gpu_model_name(struct panthor_device *ptdev) @@ -81,6 +95,12 @@ static char *get_gpu_model_name(struct panthor_device *p= tdev) fallthrough; case GPU_PROD_ID_MAKE(13, 1): return "Mali-G625"; + case GPU_PROD_ID_MAKE(14, 0): + return "Mali-G1-Ultra"; + case GPU_PROD_ID_MAKE(14, 1): + return "Mali-G1-Premium"; + case GPU_PROD_ID_MAKE(14, 3): + return "Mali-G1-Pro"; } return "(Unknown Mali GPU)"; @@ -107,12 +127,19 @@ static void panthor_gpu_info_init(struct panthor_devi= ce *ptdev) ptdev->gpu_info.as_present =3D gpu_read(ptdev, GPU_AS_PRESENT); - ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT); - ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT); - ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT); - /* Introduced in arch 11.x */ ptdev->gpu_info.gpu_features =3D gpu_read64(ptdev, GPU_FEATURES); + + if (panthor_hw_has_pwr_ctrl(ptdev)) { + /* Introduced in arch 14.x */ + ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, PWR_L2_PRESENT); + ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, PWR_TILER_PRESENT); + ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, PWR_SHADER_PRESENT); + } else { + ptdev->gpu_info.shader_present =3D gpu_read64(ptdev, GPU_SHADER_PRESENT); + ptdev->gpu_info.tiler_present =3D gpu_read64(ptdev, GPU_TILER_PRESENT); + ptdev->gpu_info.l2_present =3D gpu_read64(ptdev, GPU_L2_PRESENT); + } } static void panthor_hw_info_init(struct panthor_device *ptdev) -- 2.49.0