From nobody Sun Feb 8 21:27:12 2026 Received: from out-174.mta1.migadu.com (out-174.mta1.migadu.com [95.215.58.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1E2E29B793 for ; Fri, 24 Oct 2025 19:29:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761334196; cv=none; b=G/XJtlGnoY8Llkkmb6hDfJd4vZ9txsRyLGSMacuWd1XcSTIEmNyZ3ADyjhP4OGm0IYlP8Gm98Ep5QtjyzZ0ZFT3FUi3FWc791RnvQ+0egPdXA0wVZ6LKRYqa7ybsGuK6O8uTbeuYReNKJi1KlT4V7+1uudFb9LFSnu0oPfCt5Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761334196; c=relaxed/simple; bh=SB5q6+0hwZ04VXp6V9khXsmBZaeHcCObNItM11WBnhQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K/SLAvXcau0v1BjcKOgpSFE+5rraYW5J4GPP2/NoMYIxtDBwrlfkxVNYnUP1WGZINUaMHDtyuPKbYLvYPGdhipYjnXrQ5rxy5l427/hB48n+XocHmLRDKZbWALZFJXPfDPecrr1sZlfUAFeJXhENxLaV4Hf8TgQhrzfElofQ8d0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=GlLPWgMK; arc=none smtp.client-ip=95.215.58.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="GlLPWgMK" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1761334193; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DnV9hP8q4zoQm9zSknFS2vlFz4b3nNad1qMbHV1P/c8=; b=GlLPWgMKF6ORhryWoBp3kaBoDjowU94NZ+ATwkedc8YjWVcofwmR5HSCGq5tioSfnrdKnG /zWn3YaQVZ+5VhAHWa7YLLR5TV7L8f1QRJarfclbLTLuHv+MX+Df0HbgTO/HpRD87esgwM jD2ig7Jy+mHk5mwYcq4sR+iSNyrRaqM= From: Yosry Ahmed To: Sean Christopherson Cc: Paolo Bonzini , Jim Mattson , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Yosry Ahmed , stable@vger.kernel, Matteo Rizzo Subject: [PATCH 2/3] KVM: nSVM: Propagate SVM_EXIT_CR0_SEL_WRITE correctly for LMSW emulation Date: Fri, 24 Oct 2025 19:29:17 +0000 Message-ID: <20251024192918.3191141-3-yosry.ahmed@linux.dev> In-Reply-To: <20251024192918.3191141-1-yosry.ahmed@linux.dev> References: <20251024192918.3191141-1-yosry.ahmed@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT When emulating L2 instructions, svm_check_intercept() checks whether a write to CR0 should trigger a synthesized #VMEXIT with SVM_EXIT_CR0_SEL_WRITE. For MOV-to-CR0, SVM_EXIT_CR0_SEL_WRITE is only triggered if any bit other than CR0.MP and CR0.TS is updated. However, according to the APM (24593=E2=80=94Rev. 3.42=E2=80=94March 2024, Table 15= -7): The LMSW instruction treats the selective CR0-write intercept as a non-selective intercept (i.e., it intercepts regardless of the value being written). Skip checking the changed bits for x86_intercept_lmsw and always inject SVM_EXIT_CR0_SEL_WRITE. Fixes: cfec82cb7d31 ("KVM: SVM: Add intercept check for emulated cr accesse= s") Cc: stable@vger.kernel Reported-by: Matteo Rizzo Signed-off-by: Yosry Ahmed --- arch/x86/kvm/svm/svm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 153c12dbf3eb1..9ea0ff136e299 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4541,20 +4541,20 @@ static int svm_check_intercept(struct kvm_vcpu *vcp= u, INTERCEPT_SELECTIVE_CR0))) break; =20 - cr0 =3D vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; - val =3D info->src_val & ~SVM_CR0_SELECTIVE_MASK; - + /* LMSW always triggers INTERCEPT_SELECTIVE_CR0 */ if (info->intercept =3D=3D x86_intercept_lmsw) { - cr0 &=3D 0xfUL; - val &=3D 0xfUL; - /* lmsw can't clear PE - catch this here */ - if (cr0 & X86_CR0_PE) - val |=3D X86_CR0_PE; + icpt_info.exit_code =3D SVM_EXIT_CR0_SEL_WRITE; + break; } =20 + /* + * MOV-to-CR0 only triggers INTERCEPT_SELECTIVE_CR0 if any bit + * other than SVM_CR0_SELECTIVE_MASK is changed. + */ + cr0 =3D vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; + val =3D info->src_val & ~SVM_CR0_SELECTIVE_MASK; if (cr0 ^ val) icpt_info.exit_code =3D SVM_EXIT_CR0_SEL_WRITE; - break; } case SVM_EXIT_READ_DR0: --=20 2.51.1.821.gb6fe4d2222-goog