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charset="utf-8" Enable OTG support for primary USB controller on EVK Platform. Add HD3SS3220 Type-C port controller present between Type-C port and SoC that provides role switch notifications to controller. Signed-off-by: Krishna Kurapati --- Changes in v3: - Moved "usb-role-switch" to lemans dtsi file - Moved vbus supply to connector node Link to v3 bindings and driver support: https://lore.kernel.org/all/20251024181832.2744502-1-krishna.kurapati@oss.q= ualcomm.com/ Link to v2: https://lore.kernel.org/all/20251008180036.1770735-1-krishna.kurapati@oss.q= ualcomm.com/ arch/arm64/boot/dts/qcom/lemans-evk.dts | 122 +++++++++++++++++++++++- arch/arm64/boot/dts/qcom/lemans.dtsi | 1 + 2 files changed, 121 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/= qcom/lemans-evk.dts index c7dc9b8f4457..2baad2612b16 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -37,6 +37,35 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + connector0 { + compatible =3D "usb-c-connector"; + label =3D "USB0-Type-C"; + data-role =3D "dual"; + power-role =3D "dual"; + + vbus-supply =3D <&vbus_supply_regulator_0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb0_con_hs_ep: endpoint { + remote-endpoint =3D <&usb3_hs_ep>; + }; + }; + port@1 { + reg =3D <1>; + + usb0_con_ss_ep: endpoint { + remote-endpoint =3D <&hd3ss3220_in_ep>; + }; + }; + }; + }; + edp0-connector { compatible =3D "dp-connector"; label =3D "EDP0"; @@ -101,6 +130,15 @@ platform { }; }; =20 + vbus_supply_regulator_0: vbus-supply-regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus_supply_0"; + gpio =3D <&expander1 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + }; + vmmc_sdc: regulator-vmmc-sdc { compatible =3D "regulator-fixed"; =20 @@ -453,6 +491,53 @@ &gpi_dma2 { status =3D "okay"; }; =20 +&pmm8654au_2_gpios { + usb0_intr_state: usb0-intr-state { + pins =3D "gpio5"; + function =3D "normal"; + input-enable; + bias-pull-up; + power-source =3D <0>; + }; +}; + +&i2c11 { + status =3D "okay"; + + hd3ss3220@67 { + compatible =3D "ti,hd3ss3220"; + reg =3D <0x67>; + + interrupts-extended =3D <&pmm8654au_2_gpios 5 IRQ_TYPE_EDGE_FALLING>; + + id-gpios =3D <&tlmm 50 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&usb_id>, <&usb0_intr_state>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint =3D <&usb0_con_ss_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint =3D <&usb3_ss_ep>; + }; + }; + }; + }; +}; + &i2c18 { status =3D "okay"; =20 @@ -718,11 +803,24 @@ wake-pins { }; }; =20 + qup_i2c11_default: qup-i2c11-state { + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + sd_cd: sd-cd-state { pins =3D "gpio36"; function =3D "gpio"; bias-pull-up; }; + + usb_id: usb-id-state { + pins =3D "gpio50"; + function =3D "gpio"; + bias-pull-up; + }; }; =20 &uart10 { @@ -751,9 +849,29 @@ &ufs_mem_phy { }; =20 &usb_0 { - dr_mode =3D "peripheral"; - status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb3_hs_ep: endpoint { + remote-endpoint =3D <&usb0_con_hs_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + usb3_ss_ep: endpoint { + remote-endpoint =3D <&hd3ss3220_out_ep>; + }; + }; + + }; }; =20 &usb_0_hsphy { diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index cf685cb186ed..f624d8d4aa9d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3970,6 +3970,7 @@ usb_0: usb@a600000 { snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; =20 + usb-role-switch; status =3D "disabled"; }; =20 --=20 2.34.1