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charset="utf-8" Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 131 +++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index a55b9eb02898..0bf9ca1e0dc3 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -904,7 +904,7 @@ gcc: clock-controller@100000 { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <0>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -2432,6 +2432,135 @@ pcie0_phy: phy@1c04000 { status =3D "disabled"; }; =20 + pcie1: pci@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <1>; + num-lanes =3D <4>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcieport1: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c14000 { + compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg =3D <0x0 0x01c14000 0x0 0x4000>; + + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible =3D "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; --=20 2.34.1