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charset="utf-8" Add vendor prefix for UltraRISC Technology Co., Ltd. Acked-by: Rob Herring (Arm) Signed-off-by: Lucas Zampieri --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 9ec8947dfcad..887bcb792284 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1642,6 +1642,8 @@ patternProperties: description: Universal Scientific Industrial Co., Ltd. "^usr,.*": description: U.S. Robotics Corporation + "^ultrarisc,.*": + description: UltraRISC Technology Co., Ltd. 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charset="utf-8" From: Charles Mirabile Add compatible strings for the PLIC found in UltraRISC DP1000 SoC. The PLIC is part of the UR-CP100 core and has a hardware bug requiring a workaround. Signed-off-by: Charles Mirabile Acked-by: Conor Dooley Signed-off-by: Lucas Zampieri --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 5b827bc24301..34591d64cca3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -74,6 +74,9 @@ properties: - sophgo,sg2044-plic - thead,th1520-plic - const: thead,c900-plic + - items: + - const: ultrarisc,dp1000-plic + - const: ultrarisc,cp100-plic - items: - const: sifive,plic-1.0.0 - const: riscv,plic0 --=20 2.51.0 From nobody Fri Dec 19 08:54:58 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F94306B25 for ; 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charset="utf-8" From: Charles Mirabile Optimize the PLIC driver by maintaining the interrupt enable state in the handler's enable_save array during normal operation rather than only during suspend/resume. This eliminates the need to read enable registers during suspend and makes the enable state immediately available for other optimizations. Modify __plic_toggle() to take a handler pointer instead of enable_base, allowing it to update both the hardware registers and the cached enable_save state atomically within the existing enable_lock protection. Remove the suspend-time enable register reading since enable_save now always reflects the current state. Signed-off-by: Charles Mirabile Signed-off-by: Lucas Zampieri --- drivers/irqchip/irq-sifive-plic.c | 36 +++++++++++-------------------- 1 file changed, 13 insertions(+), 23 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index cbd7697bc1481..d518a8b468742 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -94,15 +94,22 @@ static DEFINE_PER_CPU(struct plic_handler, plic_handler= s); =20 static int plic_irq_set_type(struct irq_data *d, unsigned int type); =20 -static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) +static void __plic_toggle(struct plic_handler *handler, int hwirq, int ena= ble) { - u32 __iomem *reg =3D enable_base + (hwirq / 32) * sizeof(u32); + u32 __iomem *base =3D handler->enable_base; u32 hwirq_mask =3D 1 << (hwirq % 32); + int group =3D hwirq / 32; + u32 value; + + value =3D readl(base + group); =20 if (enable) - writel(readl(reg) | hwirq_mask, reg); + value |=3D hwirq_mask; else - writel(readl(reg) & ~hwirq_mask, reg); + value &=3D ~hwirq_mask; + + handler->enable_save[group] =3D value; + writel(value, base + group); } =20 static void plic_toggle(struct plic_handler *handler, int hwirq, int enabl= e) @@ -110,7 +117,7 @@ static void plic_toggle(struct plic_handler *handler, i= nt hwirq, int enable) unsigned long flags; =20 raw_spin_lock_irqsave(&handler->enable_lock, flags); - __plic_toggle(handler->enable_base, hwirq, enable); + __plic_toggle(handler, hwirq, enable); raw_spin_unlock_irqrestore(&handler->enable_lock, flags); } =20 @@ -247,33 +254,16 @@ static int plic_irq_set_type(struct irq_data *d, unsi= gned int type) =20 static int plic_irq_suspend(void) { - unsigned int i, cpu; - unsigned long flags; - u32 __iomem *reg; struct plic_priv *priv; =20 priv =3D per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; =20 /* irq ID 0 is reserved */ - for (i =3D 1; i < priv->nr_irqs; i++) { + for (unsigned int i =3D 1; i < priv->nr_irqs; i++) { __assign_bit(i, priv->prio_save, readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); 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charset="utf-8" From: Charles Mirabile Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to work around a known hardware bug with IRQ claiming in the UR-CP100 cores. When claiming an interrupt on UR-CP100 cores, all other interrupts must be disabled before the claim register is accessed to prevent incorrect handling of the interrupt. This is a hardware bug in the CP100 core implementation, not specific to the DP1000 SoC. When the PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM flag is present, a specialized handler (plic_handle_irq_cp100) saves the enable state of all interrupts, disables all interrupts except for the first pending one before reading the claim register, and then restores the interrupts before further processing of the claimed interrupt continues. This implementation leverages the enable_save optimization from the previous patch, which maintains the current interrupt enable state in memory, avoiding additional register reads during the workaround. The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all SoCs using UR-CP100 cores, regardless of the specific SoC implementation. This has no impact on other platforms. Co-developed-by: Zhang Xincheng Signed-off-by: Zhang Xincheng Signed-off-by: Charles Mirabile Acked-by: Samuel Holland Signed-off-by: Lucas Zampieri --- drivers/irqchip/irq-sifive-plic.c | 116 +++++++++++++++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index d518a8b468742..786be200248f9 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -49,6 +49,8 @@ #define CONTEXT_ENABLE_BASE 0x2000 #define CONTEXT_ENABLE_SIZE 0x80 +#define PENDING_BASE 0x1000 + /* * Each hart context has a set of control registers associated with it. R= ight * now there's only two: a source priority threshold over which the hart w= ill @@ -63,6 +65,7 @@ #define PLIC_ENABLE_THRESHOLD 0 #define PLIC_QUIRK_EDGE_INTERRUPT 0 +#define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1 struct plic_priv { struct fwnode_handle *fwnode; @@ -388,6 +391,110 @@ static void plic_handle_irq(struct irq_desc *desc) chained_irq_exit(chip, desc); } =20 +static u32 cp100_isolate_pending_irq(int nr_irq_groups, u32 ie[], + u32 __iomem *pending, + u32 __iomem *enable) +{ + u32 pending_irqs =3D 0; + int i, j; + + /* Look for first pending interrupt */ + for (i =3D 0; i < nr_irq_groups; i++) { + /* Any pending interrupts would be annihilated, so skip checking them */ + if (!ie[i]) + continue; + + pending_irqs =3D ie[i] & readl_relaxed(pending + i); + + if (pending_irqs) + break; + } + + if (!pending_irqs) + return 0; + + /* Isolate lowest set bit*/ + pending_irqs &=3D -pending_irqs; + + /* Disable all interrupts but the first pending one */ + for (j =3D 0; j < nr_irq_groups; j++) { + u32 new_mask =3D j =3D=3D i ? pending_irqs : 0; + + /* If the new mask does not differ, skip writing it */ + if (new_mask =3D=3D ie[j]) + continue; + + writel_relaxed(new_mask, enable + j); + } + + return pending_irqs; +} + +static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, + void __iomem *claim) +{ + int nr_irq_groups =3D DIV_ROUND_UP(handler->priv->nr_irqs, 32); + u32 __iomem *pending =3D handler->priv->regs + PENDING_BASE; + u32 __iomem *enable =3D handler->enable_base; + irq_hw_number_t hwirq =3D 0; + u32 iso_mask; + int i; + + guard(raw_spinlock)(&handler->enable_lock); + + /* Existing enable state is already cached in enable_save */ + iso_mask =3D cp100_isolate_pending_irq(nr_irq_groups, handler->enable_sav= e, pending, enable); + + if (!iso_mask) + return 0; + + /* + * Interrupts delievered to hardware still become pending, but only + * interrupts that are both pending and enabled can be claimed. + * Clearing enable bit for all interrupts but the first pending one + * avoids hardware bug that occurs during read from claim register + * with more than one eligible interrupt. + */ + hwirq =3D readl(claim); + + /* Restore previous state */ + for (i =3D 0; i < nr_irq_groups; i++) { + u32 stored =3D handler->enable_save[i]; + u32 written =3D i =3D=3D hwirq / 32 ? iso_mask : 0; + + /* If we did not need to change the mask, no need to change it back */ + if (stored =3D=3D written) + continue; + + writel_relaxed(stored, enable + i); + } + + return hwirq; +} + +static void plic_handle_irq_cp100(struct irq_desc *desc) +{ + struct plic_handler *handler =3D this_cpu_ptr(&plic_handlers); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + void __iomem *claim =3D handler->hart_base + CONTEXT_CLAIM; + irq_hw_number_t hwirq; + + WARN_ON_ONCE(!handler->present); + + chained_irq_enter(chip, desc); + + while ((hwirq =3D cp100_get_hwirq(handler, claim))) { + int err =3D generic_handle_domain_irq(handler->priv->irqdomain, hwirq); + + if (unlikely(err)) { + pr_warn_ratelimited("%pfwP: can't find mapping for hwirq %lu\n", + handler->priv->fwnode, hwirq); + } + } + + chained_irq_exit(chip, desc); +} + static void plic_set_threshold(struct plic_handler *handler, u32 threshold) { /* priority must be > threshold to trigger an interrupt */ @@ -424,6 +531,8 @@ static const struct of_device_id plic_match[] =3D { .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, { .compatible =3D "thead,c900-plic", .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + { .compatible =3D "ultrarisc,cp100-plic", + .data =3D (const void *)BIT(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM) }, {} }; =20 @@ -658,12 +767,17 @@ static int plic_probe(struct fwnode_handle *fwnode) } if (global_setup) { + void (*handler_fn)(struct irq_desc *) =3D plic_handle_irq; + + if (test_bit(PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM, &handler->priv->p= lic_quirks)) + handler_fn =3D plic_handle_irq_cp100; + /* Find parent domain and register chained handler */ domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS= _ANY); if (domain) plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); if (plic_parent_irq) - irq_set_chained_handler(plic_parent_irq, plic_handle_irq); + irq_set_chained_handler(plic_parent_irq, handler_fn); cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", --=20 2.51.0