From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FE0E3064B1; Fri, 24 Oct 2025 08:33:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294794; cv=none; b=TNYvgLgpzdg982A/Q/f8/CVd/Aete/v5N1uFranR3eqCgxg27qUf06YldM6aubI1u95U+Pyp/5LA1a85FGEkD2B9aOSxZSq5V2mMlFoF0JJjIMK+lBov/YbwRX3GqsCJIfJqMCs3Ur4AFGZZ85GZ689UYiUmchunfH7Mx1Nl7vU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294794; c=relaxed/simple; bh=GnXom17LPeRNQIG22zsGuukZcFHtFvIHWJ7Waw4tsSg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VIG6XlLHqdGn2UdzxvgwsMpr05MYyPPKK6snyzrSMrdIyRfsvzT6utx3FTlQ1dJV9nJgxge0lxzv6GhDyyYQZ+8Olgap1Yn8Z34FMtC+5KuwCWZ6lne5jsvY3wjPVzypflycyplf0PQ3wWOiBte6dVj+Zu3SyniJa/1OFFEPXJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=pYMeoMlu; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="pYMeoMlu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1761294790; bh=GnXom17LPeRNQIG22zsGuukZcFHtFvIHWJ7Waw4tsSg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pYMeoMlufLsWIxH3fO9lyb2yv5FCpKI3l9gBfEd5dCyjhWvUu3d/rwiGyTeWLpga1 CCWKdrO3DdGobDBcGlcyrrtfE2MWJw3jd5n1ByqvduSmlP+MKB+5J55Oa/5NEkP/pE qVwQ8Z+5B2XMYbHQJOIPw1ggu52W91dT83WGunEE7V+XwHiXgtF4/iqSMV4lUVazBe Xx1EXf9dZt6rlodhtQGjRVh29y55AJs86oNy1zKs28bowOdLmEFtqVoxzHRs6mADV9 gyLthaUdv0lRzhANwwSnTNkJAa4w6TuQoTwLpsSOSU1F0BzoHF5MiO1zoXUFT8g6Np ESj9XGS3KkziA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 45F1D17E00AC; Fri, 24 Oct 2025 10:33:10 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, laura.nao@collabora.com, nfraprado@collabora.com, wenst@chromium.org, y.oudjana@protonmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 1/7] clk: mediatek: Split out registration from mtk_clk_register_gates() Date: Fri, 24 Oct 2025 10:32:55 +0200 Message-ID: <20251024083301.25845-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> References: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for clock controllers over SPMI bus, split out the actual registration iterator out of the function mtk_clk_register_gates() to a new mtk_clk_register_all_gates() private function, taking a handle to regmap and hwv_regmap as parameters. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-gate.c | 43 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index f6b1429ff757..fd8cec95cd8d 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -252,30 +252,17 @@ static void mtk_clk_unregister_gate(struct clk_hw *hw) kfree(cg); } =20 -int mtk_clk_register_gates(struct device *dev, struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data) +static int mtk_clk_register_all_gates(struct device *dev, struct device_no= de *node, + struct regmap *regmap, struct regmap *hwv_regmap, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data) { int i; struct clk_hw *hw; - struct regmap *regmap; - struct regmap *regmap_hwv; =20 if (!clk_data) return -ENOMEM; =20 - regmap =3D device_node_to_regmap(node); - if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); - return PTR_ERR(regmap); - } - - regmap_hwv =3D mtk_clk_get_hwv_regmap(node); - if (IS_ERR(regmap_hwv)) - return dev_err_probe( - dev, PTR_ERR(regmap_hwv), - "Cannot find hardware voter regmap for %pOF\n", node); - for (i =3D 0; i < num; i++) { const struct mtk_gate *gate =3D &clks[i]; =20 @@ -311,6 +298,28 @@ int mtk_clk_register_gates(struct device *dev, struct = device_node *node, =20 return PTR_ERR(hw); } + +int mtk_clk_register_gates(struct device *dev, struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data) +{ + struct regmap *regmap, *regmap_hwv; + + regmap =3D device_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); + return PTR_ERR(regmap); + } + + regmap_hwv =3D mtk_clk_get_hwv_regmap(node); + if (IS_ERR(regmap_hwv)) + return dev_err_probe( + dev, PTR_ERR(regmap_hwv), + "Cannot find hardware voter regmap for %pOF\n", node); + + return mtk_clk_register_all_gates(dev, node, regmap, regmap_hwv, + clks, num, clk_data); +} EXPORT_SYMBOL_GPL(mtk_clk_register_gates); =20 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282753064AE; Fri, 24 Oct 2025 08:33:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294795; cv=none; b=OlsftVe+Q60QnJQruSGPKN9RKe5n30wHxRVH+tS1YdV26/sh7zbmSBFG4FLImA1uFyYXuSkSh+xD81teX833pxhwQF0fEfkhuQ2h4MagSoEAdSOLChiaMIKYWZBdQ3y1C49wAGInGlK8j0oVpopNpCtWU3zP285CpwybLXXvtpU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294795; c=relaxed/simple; bh=uMNDlVMiY8eMGT5nLR/6G4iE8k9njF/IX52KNy0kIlQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Fri, 24 Oct 2025 10:33:11 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, laura.nao@collabora.com, nfraprado@collabora.com, wenst@chromium.org, y.oudjana@protonmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 2/7] clk: mediatek: clk-gate: Simplify and optimize registration iter Date: Fri, 24 Oct 2025 10:32:56 +0200 Message-ID: <20251024083301.25845-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> References: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify and optimize mtk_clk_register_all_gates() by removing and replacing the function-local clk_hw pointer assignment and check and as last step the consequent assignment to the array containing handles to the registered clocks with... just the last step. This removes a bunch of useless assignments, and in case any error happens, the tear down iterator will still do its job without any change required, effectively bringing no functional change, and a a small optimization. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-gate.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index fd8cec95cd8d..8d1cc6a98a5f 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -257,8 +257,7 @@ static int mtk_clk_register_all_gates(struct device *de= v, struct device_node *no const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data) { - int i; - struct clk_hw *hw; + int i, ret; =20 if (!clk_data) return -ENOMEM; @@ -272,21 +271,19 @@ static int mtk_clk_register_all_gates(struct device *= dev, struct device_node *no continue; } =20 - hw =3D mtk_clk_register_gate(dev, gate, regmap, regmap_hwv); - - if (IS_ERR(hw)) { + clk_data->hws[gate->id] =3D mtk_clk_register_gate(dev, gate, regmap, hwv= _regmap); + if (IS_ERR(clk_data->hws[gate->id])) { pr_err("Failed to register clk %s: %pe\n", gate->name, - hw); + clk_data->hws[gate->id]); + ret =3D PTR_ERR(clk_data->hws[gate->id]); goto err; } - - clk_data->hws[gate->id] =3D hw; } =20 return 0; =20 err: - while (--i >=3D 0) { + while (i-- >=3D 0) { const struct mtk_gate *gate =3D &clks[i]; =20 if (IS_ERR_OR_NULL(clk_data->hws[gate->id])) @@ -296,7 +293,7 @@ static int mtk_clk_register_all_gates(struct device *de= v, struct device_node *no clk_data->hws[gate->id] =3D ERR_PTR(-ENOENT); } =20 - return PTR_ERR(hw); + return ret; } =20 int mtk_clk_register_gates(struct device *dev, struct device_node *node, --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 108A73064B8; Fri, 24 Oct 2025 08:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 24 Oct 2025 10:33:11 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, laura.nao@collabora.com, nfraprado@collabora.com, wenst@chromium.org, y.oudjana@protonmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 3/7] clk: mediatek: clk-mtk: Split and rename __mtk_clk_simple_probe() Date: Fri, 24 Oct 2025 10:32:57 +0200 Message-ID: <20251024083301.25845-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> References: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support to register clock controllers that are not reachable over MMIO but rather over a different bus, especially SPMI (for PMIC clocks!), split out the current private __mtk_clk_simple_probe() function in two, make it accept a handle to regmap in and call it mtk_clk_simple_probe_internal(). The new function is not static, but its symbol is *not* exported: this is done on purpose, because this is supposed to be usable only by clock registration helpers inside of clk/mediatek, and only ones built inside of the same module as clk-mtk, as will be done in a later change. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 58 ++++++++++++++++++++++++---------- drivers/clk/mediatek/clk-mtk.h | 5 +++ 2 files changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 19cd27941747..93c7e28ffb5f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -2,6 +2,8 @@ /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno */ =20 #include @@ -14,6 +16,7 @@ #include #include #include +#include #include =20 #include "clk-mtk.h" @@ -464,26 +467,15 @@ void mtk_clk_unregister_dividers(const struct mtk_clk= _divider *mcds, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_dividers); =20 -static int __mtk_clk_simple_probe(struct platform_device *pdev, - struct device_node *node) +int mtk_clk_simple_probe_internal(struct platform_device *pdev, + struct device_node *node, + const struct mtk_clk_desc *mcd, + struct regmap *regmap) { - const struct platform_device_id *id; - const struct mtk_clk_desc *mcd; struct clk_hw_onecell_data *clk_data; void __iomem *base =3D NULL; int num_clks, r; =20 - mcd =3D device_get_match_data(&pdev->dev); - if (!mcd) { - /* Clock driver wasn't registered from devicetree */ - id =3D platform_get_device_id(pdev); - if (id) - mcd =3D (const struct mtk_clk_desc *)id->driver_data; - - if (!mcd) - return -EINVAL; - } - /* Composite and divider clocks needs us to pass iomem pointer */ if (mcd->composite_clks || mcd->divider_clks) { if (!mcd->shared_io) @@ -653,20 +645,52 @@ static void __mtk_clk_simple_remove(struct platform_d= evice *pdev, mtk_free_clk_data(clk_data); } =20 +static int mtk_clk_get_desc(struct platform_device *pdev, const struct mtk= _clk_desc **d) +{ + const struct platform_device_id *id; + const struct mtk_clk_desc *mcd; + + mcd =3D device_get_match_data(&pdev->dev); + if (!mcd) { + /* Clock driver wasn't registered from devicetree */ + id =3D platform_get_device_id(pdev); + if (id) + mcd =3D (const struct mtk_clk_desc *)id->driver_data; + + if (!mcd) + return -EINVAL; + } + *d =3D mcd; + + return 0; +} + int mtk_clk_pdev_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct device_node *node =3D dev->parent->of_node; + const struct mtk_clk_desc *mcd; + int ret; =20 - return __mtk_clk_simple_probe(pdev, node); + ret =3D mtk_clk_get_desc(pdev, &mcd); + if (ret) + return ret; + + return mtk_clk_simple_probe_internal(pdev, node, mcd, NULL); } EXPORT_SYMBOL_GPL(mtk_clk_pdev_probe); =20 int mtk_clk_simple_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; + const struct mtk_clk_desc *mcd; + int ret; + + ret =3D mtk_clk_get_desc(pdev, &mcd); + if (ret) + return ret; =20 - return __mtk_clk_simple_probe(pdev, node); + return mtk_clk_simple_probe_internal(pdev, node, mcd, NULL); } EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); =20 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 5417b9264e6d..945fd3ee79ca 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -262,6 +262,11 @@ struct mtk_clk_desc { bool need_runtime_pm; }; =20 +int mtk_clk_simple_probe_internal(struct platform_device *pdev, + struct device_node *node, + const struct mtk_clk_desc *mcd, + struct regmap *regmap); + int mtk_clk_pdev_probe(struct platform_device *pdev); void mtk_clk_pdev_remove(struct platform_device *pdev); int mtk_clk_simple_probe(struct platform_device *pdev); --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00B2930BF5D; Fri, 24 Oct 2025 08:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294799; cv=none; b=nXkbRnHni7hdI7WddXlre5XiMLgGTR6c59TpSJLbRgFezHfm6NGVBJOXOXoWbySsonn2DvkDunBXerzp50ibslwL0PeJJchcnUY1lJdH+kUbIZUdHHZBEtFvWLHadwBof7de0SrGbTQPP8BZ0Ea9XtuOEmnFc4USQ63kCmyP4BQ= ARC-Message-Signature: i=1; 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charset="utf-8" In preparation for adding means to register SPMI clock controllers add a new mtk_spmi_clk_register_gates() function and wire it up to mtk_clk_simple_probe_internal(). Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-gate.c | 10 ++++++++++ drivers/clk/mediatek/clk-gate.h | 6 ++++++ drivers/clk/mediatek/clk-mtk.c | 8 ++++++-- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index 8d1cc6a98a5f..1bc09c5ca897 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -319,6 +319,16 @@ int mtk_clk_register_gates(struct device *dev, struct = device_node *node, } EXPORT_SYMBOL_GPL(mtk_clk_register_gates); =20 +int mtk_spmi_clk_register_gates(struct device *dev, struct device_node *no= de, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data, + struct regmap *regmap) +{ + return mtk_clk_register_all_gates(dev, node, regmap, NULL, + clks, num, clk_data); +} +EXPORT_SYMBOL_GPL(mtk_spmi_clk_register_gates); + void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data) { diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gat= e.h index 4f05b9855dae..924219344021 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -14,6 +14,7 @@ struct clk_hw_onecell_data; struct clk_ops; struct device; struct device_node; +struct regmap; =20 extern const struct clk_ops mtk_clk_gate_ops_setclr; extern const struct clk_ops mtk_clk_gate_ops_setclr_inv; @@ -57,6 +58,11 @@ int mtk_clk_register_gates(struct device *dev, struct de= vice_node *node, const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data); =20 +int mtk_spmi_clk_register_gates(struct device *dev, struct device_node *no= de, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data, + struct regmap *regmap); + void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 93c7e28ffb5f..b5b329f6fde7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -552,8 +552,12 @@ int mtk_clk_simple_probe_internal(struct platform_devi= ce *pdev, } =20 if (mcd->clks) { - r =3D mtk_clk_register_gates(&pdev->dev, node, mcd->clks, - mcd->num_clks, clk_data); + if (regmap) + r =3D mtk_spmi_clk_register_gates(&pdev->dev, node, mcd->clks, + mcd->num_clks, clk_data, regmap); + else + r =3D mtk_clk_register_gates(&pdev->dev, node, mcd->clks, + mcd->num_clks, clk_data); if (r) goto unregister_dividers; } --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9F1F30BF55; Fri, 24 Oct 2025 08:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761294797; cv=none; b=ZtSv8MYz3QgBiiGxsp1q5eB9QbKlqb+lTSceVrn1/ZhTZ1gKhZPEMrbmW0EWJJl2WYmMokSe9SEOReSeQxoxGtpP3B6r2lAMZN6QcSc8+zwceGOabhAwJRmwHN5BLlSzo9zNon5zhqB1TC/N5VVBbRxpmXMQXajrzVikOeMunLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Add a new mtk_spmi_clk_simple_probe() helper in a new file to add support for registering SPMI Clock Controllers, and change the Makefile to conditionally embed the new clk-mtk-spmi inside of a clk-mediatek object. This was all done like that because clk-mtk-spmi wants to import the "SPMI" namespace as it uses functions to register a new SPMI subdevice (the clock controller), but doing so is not necessary if SPMI Clock Controllers support is not desired. This means that COMMON_CLK_MEDIATEK_SPMI may be either y or n, as this conditionally includes or excludes it from the object which will require said namespace only if support is desired. As a last note, when COMMON_CLK_MEDIATEK_SPMI=3Dn, the generated object will be "the same as before" (bar the name), because the object generated by COMMON_CLK_MEDIATEK was already containing all of the ones that are included right now (again, if built without support for SPMI Clock Controllers). Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 8 ++++ drivers/clk/mediatek/Makefile | 5 ++- drivers/clk/mediatek/clk-mtk-spmi.c | 62 +++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk-spmi.h | 31 +++++++++++++++ 4 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.c create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0d52771d06b3..3452dcbc9e45 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -18,6 +18,14 @@ config COMMON_CLK_MEDIATEK_FHCTL This driver supports MediaTek frequency hopping and spread spectrum clocking features. =20 +config COMMON_CLK_MEDIATEK_SPMI + bool + depends on COMMON_CLK_MEDIATEK + select REGMAP_SPMI + select SPMI + help + MediaTek PMICs clock support. + config COMMON_CLK_MT2701 bool "Clock driver for MediaTek MT2701" depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 4daba371342f..1471d8affa44 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o +clk-mediatek-y :=3D clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumu= x.o reset.o clk-mux.o +clk-mediatek-$(CONFIG_COMMON_CLK_MEDIATEK_SPMI) +=3D clk-mtk-spmi.o +obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mediatek.o + obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) +=3D clk-fhctl.o clk-pllfh.o =20 obj-$(CONFIG_COMMON_CLK_MT6735) +=3D clk-mt6735-apmixedsys.o clk-mt6735-in= fracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o diff --git a/drivers/clk/mediatek/clk-mtk-spmi.c b/drivers/clk/mediatek/clk= -mtk-spmi.c new file mode 100644 index 000000000000..0206e1f8ec27 --- /dev/null +++ b/drivers/clk/mediatek/clk-mtk-spmi.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-mtk-spmi.h" + +int mtk_spmi_clk_simple_probe(struct platform_device *pdev) +{ + struct regmap_config mtk_spmi_clk_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .fast_io =3D true + }; + struct device_node *node =3D pdev->dev.of_node; + const struct mtk_spmi_clk_desc *mscd; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; + struct regmap *regmap; + int ret; + + ret =3D of_property_read_u32(node, "reg", &mtk_spmi_clk_regmap_config.reg= _base); + if (ret) + return ret; + + /* If the max_register was not declared the pdata is not valid */ + mscd =3D device_get_match_data(&pdev->dev); + if (mscd->max_register =3D=3D 0) + return -EINVAL; + + mtk_spmi_clk_regmap_config.max_register =3D mscd->max_register; + + sparent =3D to_spmi_device(pdev->dev.parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(&pdev->dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); + + regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, &mtk_spmi_clk_regma= p_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return mtk_clk_simple_probe_internal(pdev, node, mscd->desc, regmap); +} +EXPORT_SYMBOL_GPL(mtk_spmi_clk_simple_probe); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("SPMI"); diff --git a/drivers/clk/mediatek/clk-mtk-spmi.h b/drivers/clk/mediatek/clk= -mtk-spmi.h new file mode 100644 index 000000000000..39499d1db10a --- /dev/null +++ b/drivers/clk/mediatek/clk-mtk-spmi.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno + */ + +#ifndef __DRV_CLK_MTK_SPMI_H +#define __DRV_CLK_MTK_SPMI_H + +struct mtk_clk_desc; +struct platform_device; + +struct mtk_spmi_clk_desc { + const struct mtk_clk_desc *desc; + u16 max_register; +}; + +#ifdef CONFIG_COMMON_CLK_MEDIATEK_SPMI + +int mtk_spmi_clk_simple_probe(struct platform_device *pdev); + +#else + +inline int mtk_spmi_clk_simple_probe(struct platform_device *pdev) +{ + return -ENXIO; +} + +#endif /* CONFIG_COMMON_CLK_MEDIATEK_SPMI */ + +#endif /* __DRV_CLK_MTK_SPMI_H */ --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27C6930BF6D; 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Fri, 24 Oct 2025 10:33:14 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, laura.nao@collabora.com, nfraprado@collabora.com, wenst@chromium.org, y.oudjana@protonmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 6/7] dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller Date: Fri, 24 Oct 2025 10:33:00 +0200 Message-ID: <20251024083301.25845-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> References: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings to describe the SCK_TOP clock controller embedded in the MT6685 IC, reachable over the SPMI bus. Signed-off-by: AngeloGioacchino Del Regno --- NOTE: This does not contain any example because the MT6685 RTC will be added to the mfd binding for MediaTek SPMI PMICs and examples will be there. ** For reviewing purposes, this is how the example will look like: ** - | #include #include spmi { #address-cells =3D <2>; #size-cells =3D <0>; pmic@9 { compatible =3D "mediatek,mt6363"; reg =3D <0x9 SPMI_USID>; interrupts =3D <9 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #address-cells =3D <1>; #interrupt-cells =3D <3>; #size-cells =3D <0>; clock-controller@514 { compatible =3D "mediatek,mt6685-sck-top"; reg =3D <0x514>; #clock-cells =3D <1>; }; rtc@580 { compatible =3D "mediatek,mt6685-rtc"; reg =3D <0x580>; interrupts =3D <9 0 IRQ_TYPE_LEVEL_HIGH>; }; }; }; .../bindings/clock/mediatek,mt6685-clock.yaml | 37 +++++++++++++++++++ .../dt-bindings/clock/mediatek,mt6685-clock.h | 17 +++++++++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6685= -clock.yaml create mode 100644 include/dt-bindings/clock/mediatek,mt6685-clock.h diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml new file mode 100644 index 000000000000..5407ebf2f3b5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6685-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Clock Controller for MT6685 SPMI PM/Clock IC + +maintainers: + - AngeloGioacchino Del Regno + +description: | + The clock architecture in MediaTek PMICs+Clock ICs is structured like be= low: + Crystal(XO) or Internal ClockGen --> + dividers --> + muxes + --> + clock gate + + The device nodes provide clock gate control in different IP blocks. + +properties: + compatible: + const: mediatek,mt6685-sck-top + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false diff --git a/include/dt-bindings/clock/mediatek,mt6685-clock.h b/include/dt= -bindings/clock/mediatek,mt6685-clock.h new file mode 100644 index 000000000000..acc5e2e15ce1 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6685-clock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2025 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#ifndef _DT_BINDINGS_CLK_MT6685_H +#define _DT_BINDINGS_CLK_MT6685_H + +/* SCK_TOP_CKPDN */ +#define CLK_RTC_SEC_MCLK 0 +#define CLK_RTC_EOSC32 1 +#define CLK_RTC_SEC_32K 2 +#define CLK_RTC_MCLK 3 +#define CLK_RTC_32K 4 + +#endif /* _DT_BINDINGS_CLK_MT6685_H */ --=20 2.51.1 From nobody Mon Feb 9 03:25:19 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26D2D30C35E; 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Fri, 24 Oct 2025 10:33:14 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, laura.nao@collabora.com, nfraprado@collabora.com, wenst@chromium.org, y.oudjana@protonmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller Date: Fri, 24 Oct 2025 10:33:01 +0200 Message-ID: <20251024083301.25845-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> References: <20251024083301.25845-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the SCK_TOP Clock Controller IP found in the MediaTek MT6685 PM/Clock IC as a SPMI Sub-Device. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/Kconfig | 7 ++++ drivers/clk/mediatek/Makefile | 2 + drivers/clk/mediatek/clk-mt6685.c | 70 +++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6685.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 3452dcbc9e45..eb1764418b1e 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -132,6 +132,13 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. =20 +config COMMON_CLK_MT6685 + tristate "Clock driver for MediaTek MT6685 Clock IC" + depends on ARCH_MEDIATEK + select COMMON_CLK_MEDIATEK_SPMI + help + This driver supports clocks provided by the MT6685 Clock IC. + config COMMON_CLK_MT6735 tristate "Main clock drivers for MediaTek MT6735" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 1471d8affa44..d68837f1aa06 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -5,6 +5,8 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mediatek.o =20 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) +=3D clk-fhctl.o clk-pllfh.o =20 +obj-$(CONFIG_COMMON_CLK_MT6685) +=3D clk-mt6685.o + obj-$(CONFIG_COMMON_CLK_MT6735) +=3D clk-mt6735-apmixedsys.o clk-mt6735-in= fracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) +=3D clk-mt6735-imgsys.o obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) +=3D clk-mt6735-mfgcfg.o diff --git a/drivers/clk/mediatek/clk-mt6685.c b/drivers/clk/mediatek/clk-m= t6685.c new file mode 100644 index 000000000000..1d524aef61a5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6685.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Collabora Ltd. + * AngeloGioacchino Del Regno + */ +#include +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-mtk-spmi.h" +#include "reset.h" + +static const struct mtk_gate_regs spmi_mt6685_sck_top_cg_regs =3D { + .set_ofs =3D 0x1, + .clr_ofs =3D 0x2, + .sta_ofs =3D 0x0 +}; + +#define GATE_SCKTOP(_id, _name, _parent, _shift) \ +{ \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &spmi_mt6685_sck_top_cg_regs, \ + .shift =3D _shift, \ + .flags =3D CLK_IGNORE_UNUSED, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ +} + +static const struct mtk_gate sck_top_clks[] =3D { + GATE_SCKTOP(CLK_RTC_SEC_MCLK, "rtc_sec_mclk", "rtc_sec_32k", 0), + GATE_SCKTOP(CLK_RTC_EOSC32, "rtc_eosc32", "clk26m", 2), + GATE_SCKTOP(CLK_RTC_SEC_32K, "rtc_sec_32k", "clk26m", 3), + GATE_SCKTOP(CLK_RTC_MCLK, "rtc_mclk", "rtc_32k", 4), + GATE_SCKTOP(CLK_RTC_32K, "rtc_32k", "clk26m", 5), +}; + +static const struct mtk_clk_desc mt6685_sck_top_mcd =3D { + .clks =3D sck_top_clks, + .num_clks =3D ARRAY_SIZE(sck_top_clks), +}; + +static const struct mtk_spmi_clk_desc mt6685_sck_top_mscd =3D { + .desc =3D &mt6685_sck_top_mcd, + .max_register =3D 0x10, +}; + +static const struct of_device_id of_match_clk_mt6685[] =3D { + { .compatible =3D "mediatek,mt6685-sck-top", .data =3D &mt6685_sck_top_ms= cd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6685); + +static struct platform_driver clk_mt6685_spmi_drv =3D { + .probe =3D mtk_spmi_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-spmi-mt6685", + .of_match_table =3D of_match_clk_mt6685, + }, +}; +module_platform_driver(clk_mt6685_spmi_drv); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("MediaTek MT6685 SPMI Clock IC clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.51.1