From nobody Sat Feb 7 17:41:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8807026ED29; Thu, 23 Oct 2025 22:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259461; cv=none; b=RteHT0QX2J7BSPZJkCGxHbf/EVlSGrMlS3AFNV/f4UrVFOHchUvdOkEtttbWEuTRWi/6E0KBSlTv8wMx+fkdEQSltiyuIcmznKJekfZz/c8A587DECZyJgwVhmezCnkhj7f+32QNRmOPnD0uBXg4V8b0AgwBpxjeCcNvTTxfsxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259461; c=relaxed/simple; bh=vTZI1I1+aVm4OJCS6IGIdXNJd01XGd3A7+EqPa7aWYA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uKaBrMbCY6X/GgKF00zy8loPH7a6VJLNDS0D1QKjASTdKSaJDR+dLkwmiiKeOSj8cp0yP7Gp+uO8oLI6df3FqEEs12D2xGCv2Lo/LmEWQi1ZLhn+PcVtkHHpJ41ywftN3DHmQgRU1iW6im3SdO2YOa3rfIWryZpfVWC36XEKpfk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fqQesAot; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fqQesAot" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761259460; x=1792795460; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vTZI1I1+aVm4OJCS6IGIdXNJd01XGd3A7+EqPa7aWYA=; b=fqQesAot83eFGgr9E9UlSsEIqHeT+5+taZXrshSnmd16tp5Meb4DbDSf S6ir212mbAMJlK1iDo+y/siFesruuUsWHJE96pchQuxaglbAAyjc5hCIk 2CKd+bJQvpmhc6hqYa5leYzpKQYytYGpoK+rDenNGMj6GYxSEemZtrgX8 C56Peo8mAXS3L4C5X5McNGSjTFAzjwz+6ssCG9dw5UmLFdEqa/u0Eyd4l yHkR/Q/s9D2UBjxfCap/ad+0B/p8CB4pQTvg1VjvBnqsN9Ip/rKqON3qv jgu/aYTSYbfWvB4Urvq0kyOTAeLByidoaZJKGaCR+lI4gqy3e+xP1Wur9 A==; X-CSE-ConnectionGUID: AOr7cy4AQwiS1lYH0xxh4w== X-CSE-MsgGUID: zxHvDXXYSPKAwIzNqtQ+1A== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63333507" X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="63333507" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:19 -0700 X-CSE-ConnectionGUID: GYPkEpWFSjKkd1azwesSJg== X-CSE-MsgGUID: rvXpa0ApSb2oC7KvTXc0nA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="183885477" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:18 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas , Artem Bityutskiy , Kan Liang , Zhenyu Wang Subject: [PATCH RESEND 1/3] perf/x86/intel/cstate: Add Clearwater Forest support Date: Thu, 23 Oct 2025 15:37:51 -0700 Message-ID: <20251023223754.1743928-2-zide.chen@intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251023223754.1743928-1-zide.chen@intel.com> References: <20251023223754.1743928-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Clearwater Forest is based on the Darkmont Atom microarchitecture. From the perspective of C-state residency profiling, it supports the same residency counters as Sierra Forest: CC1/CC6, PC2/PC6, and MC6. Please note that the C1E residency counter can only be read via PMT, not MSR. Therefore, tools relying on the perf_event framework cannot access the C1E residency. Cc: Artem Bityutskiy Reviewed-by: Kan Liang Signed-off-by: Zhenyu Wang Signed-off-by: Zide Chen Reviewed-by:=C2=A0 Dapeng Mi --- arch/x86/events/intel/cstate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index ec753e39b007..a5f2e0be2337 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -628,6 +628,7 @@ static const struct x86_cpu_id intel_cstates_match[] __= initconst =3D { X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &adl_cstates), X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &srf_cstates), X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &grr_cstates), + X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &srf_cstates), =20 X86_MATCH_VFM(INTEL_ICELAKE_L, &icl_cstates), X86_MATCH_VFM(INTEL_ICELAKE, &icl_cstates), --=20 2.51.1 From nobody Sat Feb 7 17:41:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61C9B28643A; Thu, 23 Oct 2025 22:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259462; cv=none; b=imenkivzOaxw4dGrEGb05I2NbOWaUgea7Ds/Pe6dJFQwYznth1eCpwcW9K3slMypY7/NVb3SY/S8Gwj9ZbA0ucDOkavDPegbFVXAUIV9QF5VqzAxQ7TNmZB/sC8lrF40xZGuLZ5XF7tpGcCu0D7eyJB47zwX6QYL4HHXEWBcPrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259462; c=relaxed/simple; bh=HC/nzp1Ek6Q8BDJXNR8G5iC+Mmgh09qewklI7Y2Hj3I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aw6DghtYJA34iaYvqyQefP8xztM3JHnlipkwI1j2/90sixv2FZbeiViy3f2KsWaFcMQKyxhjOyenKAdYSEZE/HkAIrIf6UB8pxIFQ31zm2nJzQlm/C9zwkxokCvOdLdvad7sJxK/JG8nUE/D/yC3AZ9lo3RzKMlGmuVR5QTWYTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HRCgsUGq; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HRCgsUGq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761259461; x=1792795461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HC/nzp1Ek6Q8BDJXNR8G5iC+Mmgh09qewklI7Y2Hj3I=; b=HRCgsUGq418IthgeuKnT/giEDu9Ov9xqZPey3D27byM2bFmfjA7o8e/A 6jY7uX2CjEz7zcBAZ06wHh1BQuCxvQFWHGJiXzeuhatv3lmWnsQd7cqg8 PYma2w5IfAZTPQoK1DOAM6w7LcxO8uPSfjx9g0j7sUMM38GYrNK3EG+Da Rhidw0KRgITBkcHOp+GB5FowXR3/3HIFKiCSJ5/BlWnPnJQqkrmyRNz8V /PB1JOkDDIvpyiYYIKc2cOh6c4/Q4CCBy/hgzZa63zU9BBuO31ZRo5Y2r FZg21dFzB3TyfpwVF5pOKKpmRar3ssjfZ+TaQv5PXPxJUreWJB8f5Ajdv A==; X-CSE-ConnectionGUID: Z6MIhl7+RlqYYamZ0UFPDg== X-CSE-MsgGUID: QaeUGEqkSKitWPBOxwM4ww== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63333509" X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="63333509" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:19 -0700 X-CSE-ConnectionGUID: vkDiDS3oQvacRAlhoVZ5Jw== X-CSE-MsgGUID: kfXYMNguQMKAaLxtWdVWlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="183885484" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:19 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas , Zhang Rui , Kan Liang Subject: [PATCH RESEND 2/3] perf/x86/intel/cstate: Remove PC3 support from LunarLake Date: Thu, 23 Oct 2025 15:37:52 -0700 Message-ID: <20251023223754.1743928-3-zide.chen@intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251023223754.1743928-1-zide.chen@intel.com> References: <20251023223754.1743928-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhang Rui LunarLake doesn't support Package C3. Remove the PC3 residency counter support from LunarLake. Fixes: 26579860fbd5 ("perf/x86/intel/cstate: Add Lunarlake support") Reviewed-by: Kan Liang Signed-off-by: Zhang Rui Reviewed-by:=C2=A0 Dapeng Mi --- arch/x86/events/intel/cstate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index a5f2e0be2337..2bfd011f99da 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -70,7 +70,7 @@ * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, - * ADL,RPL,MTL,ARL,LNL + * ADL,RPL,MTL,ARL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 @@ -522,7 +522,6 @@ static const struct cstate_model lnl_cstates __initcons= t =3D { BIT(PERF_CSTATE_CORE_C7_RES), =20 .pkg_events =3D BIT(PERF_CSTATE_PKG_C2_RES) | - BIT(PERF_CSTATE_PKG_C3_RES) | BIT(PERF_CSTATE_PKG_C6_RES) | BIT(PERF_CSTATE_PKG_C10_RES), }; --=20 2.51.1 From nobody Sat Feb 7 17:41:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1EF2288C24; Thu, 23 Oct 2025 22:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259462; cv=none; b=Zdiu09zVqPCPhezZ+8Fp3jILTSSqsAHjxg4OMIM85FMqvChmGJXrIVpKYebyoXuTUpYB+RndbWebE1ZuVsUOvj3g6X2QUli4dKcBcvl5Y0Z5MIwP7AsZyxmW9ZJ/UTMn2dgz0Ho48uVpDg/BAwIBvQzhNV4X3G/eTa1Muc/UZI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761259462; c=relaxed/simple; bh=ltxwjcO6fbW7VFGHu2ab0NFMy4SRYIsPlADiG3WOl94=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M/fdLWm+QInSYUW3fORM+rIL6483SgFuFVQ+ZryV+4RKoczUkdBAvrJe21S01lgt+OxPBW9TwC8+XJElcJgmEuFHkp0ht4lnV6gvf7KVaTQSKDc2qmQU9KZkQdDnv9XidkgRdbzSXJq6sd2Ncwf6nZl/UraZ8fqJc+ykmY3gqxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IU9VFnCn; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IU9VFnCn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761259461; x=1792795461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ltxwjcO6fbW7VFGHu2ab0NFMy4SRYIsPlADiG3WOl94=; b=IU9VFnCn6DzYkDwis6CskInn2tUVGy0+UvNsvBZnl9bOLdsM3QLGP2k3 DArfIvLXIKpVQhkXf7KaWiJmI0ep0f3w2gdI+NVHdaxZJ4j6MrROzHTAo xTrFTQolC4J+gLbJUsu8mXDJzu4IiqKYyDrAhhQMnmws7jdfXIq7So4cq oWxPHt419gyzWaTehIvUrNze1h+pPitoKN/sAEgS3OOQWdZgiASQP7qnu 0xlZk8q8XCksp/JlMHGSLvstqrcVIDnhfTIjHZudbSVk42WHOQT03OMV4 +lo8gt4Dppliezvij9RYLUxvB+7Nof5ya4Iz9n7+gR1lWnFy7Q2bisoSK Q==; X-CSE-ConnectionGUID: oJilxQzuRsmkGX9JGJbCkg== X-CSE-MsgGUID: 7UPJSQH6Tr6qs2FyWISt5A== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63333510" X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="63333510" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:20 -0700 X-CSE-ConnectionGUID: TbDhDJyvTRyaJTSWgC9p2w== X-CSE-MsgGUID: TkdAOh+4RZaSy/U+ucfTag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,250,1754982000"; d="scan'208";a="183885487" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 15:44:20 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas , Zhang Rui , Kan Liang Subject: [PATCH RESEND 3/3] perf/x86/intel/cstate: Add Pantherlake support Date: Thu, 23 Oct 2025 15:37:53 -0700 Message-ID: <20251023223754.1743928-4-zide.chen@intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251023223754.1743928-1-zide.chen@intel.com> References: <20251023223754.1743928-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhang Rui Like Lunarlake, Pantherlake supports CC1/CC6/CC7 and PC2/PC6/PC10. Reviewed-by: Kan Liang Signed-off-by: Zhang Rui Reviewed-by:=C2=A0 Dapeng Mi --- arch/x86/events/intel/cstate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 2bfd011f99da..fa67fda6e45b 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -41,7 +41,7 @@ * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL - * MTL,SRF,GRR,ARL,LNL + * MTL,SRF,GRR,ARL,LNL,PTL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -53,18 +53,19 @@ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, - * GRR,ARL,LNL + * GRR,ARL,LNL,PTL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, - * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL + * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL, + * PTL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, - * RPL,SPR,MTL,ARL,LNL,SRF + * RPL,SPR,MTL,ARL,LNL,SRF,PTL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 @@ -77,7 +78,7 @@ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF, - * ARL,LNL + * ARL,LNL,PTL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 @@ -96,7 +97,7 @@ * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, - * TNT,RKL,ADL,RPL,MTL,ARL,LNL + * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL * Scope: Package (physical package) * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter. * perf code: 0x00 @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __= initconst =3D { X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates), X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates), X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates), + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); --=20 2.51.1