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Thu, 23 Oct 2025 13:21:48 -0700 (PDT) From: Artem Shimko To: Vinod Koul , Eugeniy Paltsev Cc: p.zabel@pengutronix.de, dan.carpenter@linaro.org, a.shimko.dev@gmail.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v5 1/3] dmaengine: dw-axi-dmac: simplify PM functions and use modern macros Date: Thu, 23 Oct 2025 23:21:31 +0300 Message-ID: <20251023202134.1291034-2-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023202134.1291034-1-a.shimko.dev@gmail.com> References: <20251023202134.1291034-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify the power management code by removing redundant wrapper functions and using modern kernel PM macros. This reduces code duplication and improves maintainability. The changes convert the suspend/resume functions to take device pointer directly instead of the chip structure, allowing removal of the runtime PM wrapper functions. The manual PM ops definition is replaced with DEFINE_RUNTIME_DEV_PM_OPS() macro and pm_ptr() is used for the platform driver. Probe and remove functions are updated to call PM functions with device pointer. Signed-off-by: Artem Shimko --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 31 ++++++------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/d= w-axi-dmac/dw-axi-dmac-platform.c index b23536645ff7..8b7cf3baf5d3 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1314,8 +1314,10 @@ static int dma_chan_resume(struct dma_chan *dchan) return 0; } =20 -static int axi_dma_suspend(struct axi_dma_chip *chip) +static int axi_dma_suspend(struct device *dev) { + struct axi_dma_chip *chip =3D dev_get_drvdata(dev); + axi_dma_irq_disable(chip); axi_dma_disable(chip); =20 @@ -1325,9 +1327,10 @@ static int axi_dma_suspend(struct axi_dma_chip *chip) return 0; } =20 -static int axi_dma_resume(struct axi_dma_chip *chip) +static int axi_dma_resume(struct device *dev) { int ret; + struct axi_dma_chip *chip =3D dev_get_drvdata(dev); =20 ret =3D clk_prepare_enable(chip->cfgr_clk); if (ret < 0) @@ -1343,20 +1346,6 @@ static int axi_dma_resume(struct axi_dma_chip *chip) return 0; } =20 -static int __maybe_unused axi_dma_runtime_suspend(struct device *dev) -{ - struct axi_dma_chip *chip =3D dev_get_drvdata(dev); - - return axi_dma_suspend(chip); -} - -static int __maybe_unused axi_dma_runtime_resume(struct device *dev) -{ - struct axi_dma_chip *chip =3D dev_get_drvdata(dev); - - return axi_dma_resume(chip); -} - static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_sp= ec, struct of_dma *ofdma) { @@ -1590,7 +1579,7 @@ static int dw_probe(struct platform_device *pdev) * driver to work also without Runtime PM. */ pm_runtime_get_noresume(chip->dev); - ret =3D axi_dma_resume(chip); + ret =3D axi_dma_resume(chip->dev); if (ret < 0) goto err_pm_disable; =20 @@ -1638,7 +1627,7 @@ static void dw_remove(struct platform_device *pdev) axi_dma_disable(chip); =20 pm_runtime_disable(chip->dev); - axi_dma_suspend(chip); + axi_dma_suspend(chip->dev); =20 for (i =3D 0; i < DMAC_MAX_CHANNELS; i++) if (chip->irq[i] > 0) @@ -1653,9 +1642,7 @@ static void dw_remove(struct platform_device *pdev) } } =20 -static const struct dev_pm_ops dw_axi_dma_pm_ops =3D { - SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) -}; +static DEFINE_RUNTIME_DEV_PM_OPS(dw_axi_dma_pm_ops, axi_dma_suspend, axi_d= ma_resume, NULL); =20 static const struct of_device_id dw_dma_of_id_table[] =3D { { @@ -1680,7 +1667,7 @@ static struct platform_driver dw_driver =3D { .driver =3D { .name =3D KBUILD_MODNAME, .of_match_table =3D dw_dma_of_id_table, - .pm =3D &dw_axi_dma_pm_ops, + .pm =3D pm_ptr(&dw_axi_dma_pm_ops), }, }; module_platform_driver(dw_driver); --=20 2.43.0 From nobody Fri Dec 19 15:38:36 2025 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 652E32C2345 for ; Thu, 23 Oct 2025 20:21:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 23 Oct 2025 13:21:51 -0700 (PDT) Received: from NB-6746.corp.yadro.com ([188.243.183.84]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-592f4d2cf30sm977522e87.97.2025.10.23.13.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Oct 2025 13:21:50 -0700 (PDT) From: Artem Shimko To: Vinod Koul , Eugeniy Paltsev , Philipp Zabel Cc: dan.carpenter@linaro.org, a.shimko.dev@gmail.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v5 2/3] dmaengine: dw-axi-dmac: add reset control support Date: Thu, 23 Oct 2025 23:21:32 +0300 Message-ID: <20251023202134.1291034-3-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023202134.1291034-1-a.shimko.dev@gmail.com> References: <20251023202134.1291034-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add proper reset control handling to the AXI DMA driver to ensure reliable initialization and power management. The driver now manages resets during probe, remove, and system suspend/resume operations. The implementation stores reset control in the chip structure and adds reset assert/deassert calls at the appropriate points: resets are deasserted during probe after clock acquisition, asserted during remove and error cleanup, and properly managed during suspend/resume cycles. Additionally, proper error handling is implemented for reset control operations to ensure robust behavior. This ensures the controller is properly reset during power transitions and prevents potential issues with incomplete initialization. Signed-off-by: Artem Shimko --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 59 +++++++++++++------ drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + 2 files changed, 43 insertions(+), 17 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/d= w-axi-dmac/dw-axi-dmac-platform.c index 8b7cf3baf5d3..1496c52f47a6 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1316,11 +1316,16 @@ static int dma_chan_resume(struct dma_chan *dchan) =20 static int axi_dma_suspend(struct device *dev) { + int ret; struct axi_dma_chip *chip =3D dev_get_drvdata(dev); =20 axi_dma_irq_disable(chip); axi_dma_disable(chip); =20 + ret =3D reset_control_assert(chip->resets); + if (ret) + dev_warn(dev, "Failed to assert resets, but continuing suspend\n"); + clk_disable_unprepare(chip->core_clk); clk_disable_unprepare(chip->cfgr_clk); =20 @@ -1338,12 +1343,23 @@ static int axi_dma_resume(struct device *dev) =20 ret =3D clk_prepare_enable(chip->core_clk); if (ret < 0) - return ret; + goto cfgr_clk_disable; + + ret =3D reset_control_deassert(chip->resets); + if (ret) + goto core_clk_disable; =20 axi_dma_enable(chip); axi_dma_irq_enable(chip); =20 return 0; + +core_clk_disable: + clk_disable_unprepare(chip->core_clk); +cfgr_clk_disable: + clk_disable_unprepare(chip->cfgr_clk); + + return ret; } =20 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_sp= ec, @@ -1455,7 +1471,6 @@ static int dw_probe(struct platform_device *pdev) struct axi_dma_chip *chip; struct dw_axi_dma *dw; struct dw_axi_dma_hcfg *hdata; - struct reset_control *resets; unsigned int flags; u32 i; int ret; @@ -1487,16 +1502,6 @@ static int dw_probe(struct platform_device *pdev) return PTR_ERR(chip->apb_regs); } =20 - if (flags & AXI_DMA_FLAG_HAS_RESETS) { - resets =3D devm_reset_control_array_get_exclusive(&pdev->dev); - if (IS_ERR(resets)) - return PTR_ERR(resets); - - ret =3D reset_control_deassert(resets); - if (ret) - return ret; - } - chip->dw->hdata->use_cfg2 =3D !!(flags & AXI_DMA_FLAG_USE_CFG2); =20 chip->core_clk =3D devm_clk_get(chip->dev, "core-clk"); @@ -1507,18 +1512,28 @@ static int dw_probe(struct platform_device *pdev) if (IS_ERR(chip->cfgr_clk)) return PTR_ERR(chip->cfgr_clk); =20 + chip->resets =3D devm_reset_control_array_get_optional_exclusive(&pdev->d= ev); + if (IS_ERR(chip->resets)) + return PTR_ERR(chip->resets); + + ret =3D reset_control_deassert(chip->resets); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n"); + ret =3D parse_device_properties(chip); if (ret) - return ret; + goto err_exit; =20 dw->chan =3D devm_kcalloc(chip->dev, hdata->nr_channels, sizeof(*dw->chan), GFP_KERNEL); - if (!dw->chan) - return -ENOMEM; + if (!dw->chan) { + ret =3D -ENOMEM; + goto err_exit; + } =20 ret =3D axi_req_irqs(pdev, chip); if (ret) - return ret; + goto err_exit; =20 INIT_LIST_HEAD(&dw->dma.channels); for (i =3D 0; i < hdata->nr_channels; i++) { @@ -1605,20 +1620,30 @@ static int dw_probe(struct platform_device *pdev) =20 err_pm_disable: pm_runtime_disable(chip->dev); +err_exit: + reset_control_assert(chip->resets); =20 return ret; } =20 static void dw_remove(struct platform_device *pdev) { + int ret; struct axi_dma_chip *chip =3D platform_get_drvdata(pdev); struct dw_axi_dma *dw =3D chip->dw; struct axi_dma_chan *chan, *_chan; u32 i; =20 - /* Enable clk before accessing to registers */ + /* + * The peripheral must be clocked and out of reset + * before its registers can be accessed. + */ clk_prepare_enable(chip->cfgr_clk); clk_prepare_enable(chip->core_clk); + ret =3D reset_control_deassert(chip->resets); + if (ret) + dev_err(&pdev->dev, "Failed to deassert resets\n"); + axi_dma_irq_disable(chip); for (i =3D 0; i < dw->hdata->nr_channels; i++) { axi_chan_disable(&chip->dw->chan[i]); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dma= c/dw-axi-dmac.h index b842e6a8d90d..c74affb9f344 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -71,6 +71,7 @@ struct axi_dma_chip { struct clk *core_clk; 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Thu, 23 Oct 2025 13:21:57 -0700 (PDT) From: Artem Shimko To: Vinod Koul , Eugeniy Paltsev Cc: p.zabel@pengutronix.de, dan.carpenter@linaro.org, a.shimko.dev@gmail.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v5 3/3] dmaengine: dw-axi-dmac: fix inconsistent indentation in pause/resume functions Date: Thu, 23 Oct 2025 23:21:33 +0300 Message-ID: <20251023202134.1291034-4-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023202134.1291034-1-a.shimko.dev@gmail.com> References: <20251023202134.1291034-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix smatch warnings about inconsistent indentation in dma_chan_pause() and axi_chan_resume() functions. The issue was with misaligned closing braces and incorrect indentation of axi_dma_iowrite64() calls following if-else blocks. The changes address code style violations by correcting misaligned indentation in conditional blocks. Specifically, the closing braces in if-else statements were improperly aligned, and subsequent calls to axi_dma_iowrite64() had incorrect indentation levels. These fixes ensure consistent code formatting according to kernel coding standards while preserving the original functionality and improving overall code readability. Signed-off-by: Artem Shimko --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/d= w-axi-dmac/dw-axi-dmac-platform.c index 1496c52f47a6..7b07bf5ac72b 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1234,7 +1234,7 @@ static int dma_chan_pause(struct dma_chan *dchan) val |=3D BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); @@ -1281,7 +1281,7 @@ static inline void axi_chan_resume(struct axi_dma_cha= n *chan) val &=3D ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); val |=3D (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val =3D axi_dma_ioread32(chan->chip, DMAC_CHEN); --=20 2.43.0