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([2401:4900:1c06:ef2:36b5:9454:6fa:e888]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2946dded613sm20226885ad.37.2025.10.23.04.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Oct 2025 04:21:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Paul Barker , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , =?UTF-8?q?Niklas=20S=C3=B6derlund?= Subject: [PATCH net-next v3 1/2] net: ravb: Make DBAT entry count configurable per-SoC Date: Thu, 23 Oct 2025 12:21:10 +0100 Message-ID: <20251023112111.215198-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023112111.215198-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20251023112111.215198-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar Avoid wasting coherent DMA memory by allocating the descriptor base address table sized for the actual number of DBAT/CDARq entries supported by the SoC. Some platforms (for example GBETH) only provide two CDARq entries; previously the driver always allocated space for 22 entries which needlessly consumed memory on those systems. Pass the per-SoC dbat_entry_num via struct ravb_hw_info and use it for allocation and initialization in probe. This sizes the table correctly and removes the unnecessary memory overhead on SoCs with fewer DBAT entries. Signed-off-by: Lad Prabhakar Reviewed-by: Niklas S=C3=B6derlund --- v2->v3: - Reworded commit message for clarity. v1->v2: - Added Reviewed-by tag from Niklas. --- drivers/net/ethernet/renesas/ravb.h | 2 +- drivers/net/ethernet/renesas/ravb_main.c | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/ren= esas/ravb.h index 7b48060c250b..d65cd83ddd16 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1017,7 +1017,6 @@ enum CSR2_BIT { #define CSR2_CSUM_ENABLE (CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4 | \ CSR2_RTCP6 | CSR2_RUDP6 | CSR2_RICMP6) =20 -#define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 #define NUM_TX_QUEUE 2 @@ -1062,6 +1061,7 @@ struct ravb_hw_info { u32 rx_max_frame_size; u32 rx_buffer_size; u32 rx_desc_size; + u32 dbat_entry_num; unsigned aligned_tx: 1; unsigned coalesce_irqs:1; /* Needs software IRQ coalescing */ =20 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/etherne= t/renesas/ravb_main.c index 9d3bd65b85ff..69d382e8757d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2694,6 +2694,7 @@ static const struct ravb_hw_info ravb_gen2_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .aligned_tx =3D 1, .gptp =3D 1, .nc_queues =3D 1, @@ -2717,6 +2718,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .internal_delay =3D 1, .tx_counters =3D 1, .multi_irqs =3D 1, @@ -2743,6 +2745,7 @@ static const struct ravb_hw_info ravb_gen4_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .internal_delay =3D 1, .tx_counters =3D 1, .multi_irqs =3D 1, @@ -2769,6 +2772,7 @@ static const struct ravb_hw_info ravb_rzv2m_hw_info = =3D { .rx_buffer_size =3D SZ_2K + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), .rx_desc_size =3D sizeof(struct ravb_ex_rx_desc), + .dbat_entry_num =3D 22, .multi_irqs =3D 1, .err_mgmt_irqs =3D 1, .gptp =3D 1, @@ -2794,6 +2798,7 @@ static const struct ravb_hw_info gbeth_hw_info =3D { .rx_max_frame_size =3D SZ_8K, .rx_buffer_size =3D SZ_2K, .rx_desc_size =3D sizeof(struct ravb_rx_desc), + .dbat_entry_num =3D 2, .aligned_tx =3D 1, .coalesce_irqs =3D 1, .tx_counters =3D 1, @@ -3025,7 +3030,7 @@ static int ravb_probe(struct platform_device *pdev) ravb_parse_delay_mode(np, ndev); =20 /* Allocate descriptor base address table */ - priv->desc_bat_size =3D sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; + priv->desc_bat_size =3D sizeof(struct ravb_desc) * info->dbat_entry_num; priv->desc_bat =3D dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_si= ze, &priv->desc_bat_dma, GFP_KERNEL); if (!priv->desc_bat) { @@ -3035,7 +3040,7 @@ static int ravb_probe(struct platform_device *pdev) error =3D -ENOMEM; goto out_rpm_put; } - for (q =3D RAVB_BE; q < DBAT_ENTRY_NUM; q++) + for (q =3D RAVB_BE; q < info->dbat_entry_num; q++) priv->desc_bat[q].die_dt =3D DT_EOS; =20 /* Initialise HW timestamp list */ --=20 2.43.0