From nobody Tue Feb 10 05:09:43 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 60CA62F39B9; Thu, 23 Oct 2025 08:20:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761207631; cv=none; b=GR4owAFRA+wLAhdbbCNZ7thdNZOOKV9ji7FZ7kZjZMrCbwPRvpMC6Wfqn8rZ2qvyIxDCvIK5czae8o2Q/hGfDXFHpSr/rT+SfYINHdkgvlutVrAaNhZaw2OesrmY9XVfxyuaXSPbnE/x35F0OHLJLmYe5mKsaagFuRl1/GwNTic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761207631; c=relaxed/simple; bh=Stj18Qd+XArNtfv+ovPOZBZd6ZIg/WDzc0UuZ3vuZIM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uVALc/3V17NX1XJZ5bjyFonB04YCwrGsqaw979PuKtuKNK5+0QJYbPBHJOTm9lh97cN3hw336j6neYCtA4qYNnnXGTpaWTCm66lWR3dlu2+mgI0VVIVmJIolWUoC3FF7LPOubpU4rZ+mfrcEZoR1pGYukuZSqahcEky+abnWeZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: RtLKIBtWR2il/HUT5E69aQ== X-CSE-MsgGUID: NTXLpINlS0WIBbJc4UXwXg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Oct 2025 17:20:28 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.77]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 577B2417CA94; Thu, 23 Oct 2025 17:20:22 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Cosmin Tanislav Subject: [PATCH 04/10] thermal: renesas: rzg3e: make calibration value retrieval per-chip Date: Thu, 23 Oct 2025 11:19:18 +0300 Message-ID: <20251023081925.2412325-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1.dirty In-Reply-To: <20251023081925.2412325-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251023081925.2412325-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the temperature calibration data via SMC SIP calls. Prepare for them by moving the syscon usage into a single function, and placing it in the chip-specific struct. Rename the functions to match their functionality, and remove single-use variables from the private state. Also, move the calibration value mask into a macro. Signed-off-by: Cosmin Tanislav --- drivers/thermal/renesas/rzg3e_thermal.c | 62 +++++++++++++------------ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c index 3c9ff5e43d7e..d2525ad3ffcc 100644 --- a/drivers/thermal/renesas/rzg3e_thermal.c +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -70,7 +70,12 @@ #define TSU_POLL_DELAY_US 10 /* Polling interval */ #define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ =20 +#define TSU_TEMP_MASK GENMASK(11, 0) + +struct rzg3e_thermal_priv; + struct rzg3e_thermal_info { + int (*get_trim)(struct rzg3e_thermal_priv *priv); int temp_d_mc; int temp_e_mc; }; @@ -91,13 +96,11 @@ struct rzg3e_thermal_info { struct rzg3e_thermal_priv { void __iomem *base; struct device *dev; - struct regmap *syscon; struct thermal_zone_device *zone; struct reset_control *rstc; const struct rzg3e_thermal_info *info; u16 trmval0; u16 trmval1; - u32 trim_offset; struct mutex lock; }; =20 @@ -334,22 +337,8 @@ static const struct thermal_zone_device_ops rzg3e_tz_o= ps =3D { .set_trips =3D rzg3e_thermal_set_trips, }; =20 -static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv) +static int rzg3e_validate_calibration(struct rzg3e_thermal_priv *priv) { - u32 val; - int ret; - - /* Read calibration values from syscon */ - ret =3D regmap_read(priv->syscon, priv->trim_offset, &val); - if (ret) - return ret; - priv->trmval0 =3D val & GENMASK(11, 0); - - ret =3D regmap_read(priv->syscon, priv->trim_offset + 4, &val); - if (ret) - return ret; - priv->trmval1 =3D val & GENMASK(11, 0); - /* Validate calibration data */ if (!priv->trmval0 || !priv->trmval1 || priv->trmval0 =3D=3D priv->trmval1 || @@ -365,17 +354,30 @@ static int rzg3e_thermal_get_calibration(struct rzg3e= _thermal_priv *priv) return 0; } =20 -static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) +static int rzg3e_thermal_get_syscon_trim(struct rzg3e_thermal_priv *priv) { struct device_node *np =3D priv->dev->of_node; + struct regmap *syscon; u32 offset; + int ret; + u32 val; =20 - priv->syscon =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-tr= im", 1, &offset); - if (IS_ERR(priv->syscon)) - return dev_err_probe(priv->dev, PTR_ERR(priv->syscon), + syscon =3D syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1= , &offset); + if (IS_ERR(syscon)) + return dev_err_probe(priv->dev, PTR_ERR(syscon), "Failed to parse renesas,tsu-trim\n"); =20 - priv->trim_offset =3D offset; + /* Read calibration values from syscon */ + ret =3D regmap_read(syscon, offset, &val); + if (ret) + return ret; + priv->trmval0 =3D val & TSU_TEMP_MASK; + + ret =3D regmap_read(syscon, offset + 4, &val); + if (ret) + return ret; + priv->trmval1 =3D val & TSU_TEMP_MASK; + return 0; } =20 @@ -402,11 +404,16 @@ static int rzg3e_thermal_probe(struct platform_device= *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); =20 - /* Parse device tree for trim register info */ - ret =3D rzg3e_thermal_parse_dt(priv); + ret =3D priv->info->get_trim(priv); if (ret) return ret; =20 + /* Validate calibration data */ + ret =3D rzg3e_validate_calibration(priv); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get valid calibration data\n"); + /* Get clock to verify frequency - clock is managed by power domain */ clk =3D devm_clk_get(dev, NULL); if (IS_ERR(clk)) @@ -423,12 +430,6 @@ static int rzg3e_thermal_probe(struct platform_device = *pdev) return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get/deassert reset control\n"); =20 - /* Get calibration data */ - ret =3D rzg3e_thermal_get_calibration(priv); - if (ret) - return dev_err_probe(dev, ret, - "Failed to get valid calibration data\n"); - /* Get comparison interrupt */ irq =3D platform_get_irq_byname(pdev, "adcmpi"); if (irq < 0) @@ -533,6 +534,7 @@ static const struct dev_pm_ops rzg3e_thermal_pm_ops =3D= { }; =20 static const struct rzg3e_thermal_info rzg3e_thermal_info =3D { + .get_trim =3D rzg3e_thermal_get_syscon_trim, .temp_d_mc =3D -41000, .temp_e_mc =3D 126000, }; --=20 2.51.1.dirty