From nobody Tue Feb 10 06:25:45 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8421E2F260A; Thu, 23 Oct 2025 08:20:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761207614; cv=none; b=GH/6LsZ0pWpssgxW8+QHuISRzJR9YELaQSM67kYkj7ZLukwHNajxCf5TkDi3eNry6HK5rGBAtmWA/tUBodvDZBuGHhgKsAaB19pc+FVa8WTqbWinGCHZW0YvM0V757RWqyDTNlt6Y8rHnHe+GAXffJhIgb4YE4dE0a2XbTqosUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761207614; c=relaxed/simple; bh=VhPtr6TDNe8OLVZ0qvExPnEgZsGRrfM30yFQB8ExEy0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z5Ak4merWL/BkV+R/xveQvy5DpK6ttycTPprNk2rvrGRRB/U7WgQe2qF9AnBRIiiW4l/ZmE4cDRF8gJfHPYq0FPf58Qf7M8y2b2wkJpiaWuPXVOsuQBf82S4UtLxjq+wQ7UC9pPz7bm2mVS+jo4Br7wvVM5fE7ziQCGnYLyUmzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: a8gUGW8zTVmv6QGKSR7v3Q== X-CSE-MsgGUID: CHzIUoSHQ+yBT++oK9YlVA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 23 Oct 2025 17:20:07 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.77]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 86A99417CA94; Thu, 23 Oct 2025 17:20:01 +0900 (JST) From: Cosmin Tanislav To: Cc: John Madieu , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Cosmin Tanislav Subject: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock Date: Thu, 23 Oct 2025 11:19:15 +0300 Message-ID: <20251023081925.2412325-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.1.dirty In-Reply-To: <20251023081925.2412325-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251023081925.2412325-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU peripheral with controlled by a module clock. The TSU module clock is enabled in register MSTPCRG (0x30c), at bit 7, resulting in a (0x30c - 0x300) / 4 * 100 + 7 =3D 307 index. Add it to the list of module clocks. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g077-cpg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 5dca5c44043e..79083165537c 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -195,6 +195,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), + DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL), DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM), DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM), DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM), --=20 2.51.1.dirty