From nobody Tue Feb 10 01:59:15 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D36382DECB4 for ; Thu, 23 Oct 2025 07:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761206116; cv=none; b=JlGVNFzChM+eJXDsCzbhDhKfmXawZzswdrS6+prKgMUcHCkZiVKo3IHjGtUw+tRBe2N47XsX5G7znhl+O0uU25QqMKY3WAYaZgOJkhTNnNX9VphvyVQTUCDM91bLTOfhi/bcO/t7GMuQ7tLhBf93X+qKuHLtjaRvgH4DWCq0aH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761206116; c=relaxed/simple; bh=T54TtTsbxh6M6hAJtY/N1nGG5riDVUz3d4ReMStlcu8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mwxmcHU/AT1YYVNIg93/EiBbGPFLJ0VRCFnflGpjxScO7JCzQVWidQGW2BEqS9LMu5KxrEaEIQ6FhOK71rDpPHW10faHg2GGTVB2usaC8IypwS7ddXvSkpbqgt3OVKnaf5V390V28OI0A/IyuMxVn7t9tKPUl1qDJ66DyCnyxts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=V5qMmFUl; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="V5qMmFUl" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 59N6swcW007476 for ; Thu, 23 Oct 2025 07:55:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=C8p9CNwWhH2 P3tYx/Ae065agIcxE/rn2ukM8ke/GIoQ=; b=V5qMmFUle3jbfBV875c0138GXKt 1LX7LTBOXy9HvzbUc/6G3gYxTEF075UJqHnVWEnRmAIOpKYe3Fg5KX+fPRFtIHt/ IMcqXHJX2nnslyvHK8oayH+EK9JejlqzJYw79VCS/uvd3KZbqadWvT4ZYWCBasmJ fzf+KC2N2nSBpHsKgiqQVBTdBAXCtCbwQYx+sCur63mr+O9hBqtprJxZzJmFRv7u SDQmLtQdfkrCy863SgCXfhl7a922iTTB8ec/i1KDwLeMR4AghY0JAyDGsZAd9lwo w3KP6KNEhODloS7rTR1TFgZPXSrOio0AOJOeOtYrOZVo3fnQ590IFPoBV3g== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 49v3447k3j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 23 Oct 2025 07:55:14 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2924b3b9d47so5621765ad.0 for ; Thu, 23 Oct 2025 00:55:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1761206113; x=1761810913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C8p9CNwWhH2P3tYx/Ae065agIcxE/rn2ukM8ke/GIoQ=; b=Z2COcLzHZ5nLq+8BMdqE6xFFqyjgOrTpOtTfevg/sOk9v8axJEl2qRtGnUpEwcYl6C rMqDdgt03WcH1kz3DXbamtA3VB1d10mKZFkxTPXAz+gJmCIv9gUWQlSqCOXgHlyB1ES/ FuLgKtxZA3jKFRCq/oRya/ewRcZalCZlOTmmh43xBR7O3alL7W+YZVZNCxoYILE5Yvfi jQgwMmRusJUc+m5rFE+d/evMH8SmfluxsdiQ+Pf7WMKXS5SI3G2EunigIDYI6F2KNivs qBxofKnXdrkWB/dT4vRpX6DNwMQ3U/zBkOVHZ93+isIq0ouHYMWvlkuxb3k2MqgyNhOM 7Byg== X-Forwarded-Encrypted: i=1; AJvYcCUxDVneef6f94ubeoyfUqsk55B4/epcCxH3z+nyBYSN0+0IyMH+uykyoeHLOxyCeNr4iRo48L/M6t+sZ5M=@vger.kernel.org X-Gm-Message-State: AOJu0Yw7LqKj+ge1jt3o/RRHX+7oAFP1zllCZU8Fz0LtfIexKmnuH//3 DgGJF6uMvqTnxYLSZ7yvaHjH0Td9Y3SgKdDIIpT8oPKrDg9aBRZfMCwwzTABTyhBOxr2jKVG7WT FASt4p28ar7Pb2FvM0HCSHmzkhWviL1NJ5P074hNGMh8shIKvlN1o60xlSQuUN7zLmlo= X-Gm-Gg: ASbGnctTfPwb99fzApLCuZJLkd/2saOrupLYVqjZ8WHL+RVnf7/aRIMxorD2IqPElt1 IPkajsh5RVcCI6Jjvrw5v23zRGpxCTU529COxRtC94K2E9tCnWMz0NAYj6tfcviwhDrQGYzABgO n9T80OsddY1xLFuywN6xcz6PXZF0zxejFJgOWyeyzVTJYAviJBIrkvDKkrnREfuHpsmmi5fhH91 5nJ32QPPNUDYOC+I4PBlpfhbv63GSkMYpcbl3ERA4WVW4SMJaoKRAKCFa40/si/jnc43oBs1k2y fqbLuEAOpvkB94OYLn0JHNsWWGQCNdpxvwXTqP/QlOFn1noiDgA8J7TWMy0J5WCWPZwXrFfi7J5 Vv95Lla+Q1ztw3IHcQTuzcVWK82BilKuFO6lXr7tUIQ884gB+Ow== X-Received: by 2002:a17:903:19e6:b0:273:31fb:a872 with SMTP id d9443c01a7336-290c9c89c81mr292304015ad.6.1761206112740; Thu, 23 Oct 2025 00:55:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFh8QEBafHX2phoiJD3uMJjDBIAviZ5hFYjRjTyUPwGlV+KhEJvctiyKhlEc9rwFwgpuPAyHQ== X-Received: by 2002:a17:903:19e6:b0:273:31fb:a872 with SMTP id d9443c01a7336-290c9c89c81mr292303595ad.6.1761206112193; Thu, 23 Oct 2025 00:55:12 -0700 (PDT) Received: from yuanjiey.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2946e1231b0sm14371265ad.97.2025.10.23.00.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Oct 2025 00:55:11 -0700 (PDT) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mkrishn@quicinc.com, jonathan@marek.ca, quic_khsieh@quicinc.com, neil.armstrong@linaro.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH 02/12] drm/msm/dpu: Add support for Kaanapali DPU Date: Thu, 23 Oct 2025 15:53:51 +0800 Message-Id: <20251023075401.1148-3-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251023075401.1148-1-yuanjie.yang@oss.qualcomm.com> References: <20251023075401.1148-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: bZ7KCzJXLnyTPB1wru6qrRZyLVD63TPQ X-Proofpoint-ORIG-GUID: bZ7KCzJXLnyTPB1wru6qrRZyLVD63TPQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyMyBTYWx0ZWRfX1YdQwkK+cibz 1u5A2XgoNZq+yTx9hpVgIR4vqStuW3gbT/3JRHoT+oAsWUebSEJ5IONqS0ioJ7PYqypMj8kY/ZT Zp5aBc5MIAspLk1zNajVWTcgn0Tclqzz+UYHM29MfqR4ls70vJwhu8SyZ4Bx3I1+Gz2A8zytXYJ LnBJmSgJELKo7fw/8yESaxgoPJIZjeqXS5xm/3YB+8QrzYNAugNvetfdlof8kDK4eyqwb5i5JJd 3b1ZapH0cTdmIKtImLniqY/LozHDLd/Woh4MjGtJ2S528HyW/21pIJdJR7T9lEkGLgukwlNWN23 Ut0JX1lWLNXmrHPSSoid3YgEbSVcamykM1lC8i0XMUIAS+R/vQg734Xyoq/C3Wz5QqwIl6HsFT+ iLlKOD7hd2VHAu24Qs3OBbIftBDxVA== X-Authority-Analysis: v=2.4 cv=E/vAZKdl c=1 sm=1 tr=0 ts=68f9df62 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Iw_5XQyGZFEQ-JL_HPQA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_08,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180023 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Display Processing Unit (DPU) version 13.0 on the Kaanapali platform. This version introduces changes to the SSPP sub-block structure. Add common block and rectangle blocks to accommodate these structural modifications for compatibility. Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang --- .../disp/dpu1/catalog/dpu_13_0_kaanapali.h | 492 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 44 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 29 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 565 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapal= i.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/d= rivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h new file mode 100644 index 000000000000..1b14930fcd88 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -0,0 +1,492 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DPU_13_0_KAANAPALI_H +#define _DPU_13_0_KAANAPALI_H + +static const struct dpu_caps kaanapali_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg kaanapali_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg kaanapali_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1F000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x20000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x21000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x22000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x23000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x24000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg kaanapali_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x2b000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x34000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x3d000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0x46000, .len =3D 0x84, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_5, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x97000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0xa0000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0xa9000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0xb2000, .len =3D 0x84, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0xbb000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0xc4000, .len =3D 0x84, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg kaanapali_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x103000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x10b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x113000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x11b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x123000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x12b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x133000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x13b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg kaanapali_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x105000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x10d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x115000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x11d000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg kaanapali_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x108000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x110000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x118000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x120000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x128000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x130000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x138000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x140000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x169000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x169400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x16a000, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x16a400, .len =3D 0, + .sblk =3D &kaanapali_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x163000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x164000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x165000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x166000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x169700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x16a700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg kaanapali_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x181000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x183000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x185000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x187000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg kaanapali_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x16e000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg kaanapali_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x169200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x169600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x16A200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x16A600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg kaanapali_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x18d000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x18e000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x18f000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x190000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg kaanapali_perf_data =3D { + .max_bw_low =3D 21400000, + .max_bw_high =3D 30200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x0ffff, 0x0ffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(kaanapali_qos_linear), + .entries =3D kaanapali_qos_linear + }, + {.nentry =3D ARRAY_SIZE(kaanapali_qos_macrotile), + .entries =3D kaanapali_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version kaanapali_mdss_ver =3D { + .core_major_ver =3D 13, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_kaanapali_cfg =3D { + .mdss_ver =3D &kaanapali_mdss_ver, + .caps =3D &kaanapali_dpu_caps, + .mdp =3D &kaanapali_mdp, + .cdm =3D &dpu_cdm_kaanapali_x, + .ctl_count =3D ARRAY_SIZE(kaanapali_ctl), + .ctl =3D kaanapali_ctl, + .sspp_count =3D ARRAY_SIZE(kaanapali_sspp), + .sspp =3D kaanapali_sspp, + .mixer_count =3D ARRAY_SIZE(kaanapali_lm), + .mixer =3D kaanapali_lm, + .dspp_count =3D ARRAY_SIZE(kaanapali_dspp), + .dspp =3D kaanapali_dspp, + .pingpong_count =3D ARRAY_SIZE(kaanapali_pp), + .pingpong =3D kaanapali_pp, + .dsc_count =3D ARRAY_SIZE(kaanapali_dsc), + .dsc =3D kaanapali_dsc, + .merge_3d_count =3D ARRAY_SIZE(kaanapali_merge_3d), + .merge_3d =3D kaanapali_merge_3d, + .wb_count =3D ARRAY_SIZE(kaanapali_wb), + .wb =3D kaanapali_wb, + .cwb_count =3D ARRAY_SIZE(kaanapali_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(kaanapali_intf), + .intf =3D kaanapali_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &kaanapali_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 6641455c4ec6..5a24ed0f818c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -241,6 +241,25 @@ static const u32 wb2_formats_rgb_yuv[] =3D { .rotation_cfg =3D NULL, \ } =20 +/* kaanapali SSPP common configuration */ +#define _KAANAPALI_VIG_SBLK(scaler_ver) \ + { \ + .cmn_blk =3D {.name =3D "cmn_blk", \ + .base =3D 0, .len =3D 0x100,}, \ + .sspp_rec0_blk =3D {.name =3D "sspp_rec0", \ + .base =3D 0x1000, .len =3D 0x180,}, \ + .csc_blk =3D {.name =3D "csc", \ + .base =3D 0x1800, .len =3D 0x100,}, \ + .scaler_blk =3D {.name =3D "scaler", \ + .version =3D scaler_ver, \ + .base =3D 0x2000, .len =3D 0xec,}, \ + .sspp_rec1_blk =3D {.name =3D "sspp_rec1", \ + .base =3D 0x3000, .len =3D 0x180,}, \ + .format_list =3D plane_formats_yuv, \ + .num_formats =3D ARRAY_SIZE(plane_formats_yuv), \ + .rotation_cfg =3D NULL, \ + } + #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ { \ .scaler_blk =3D {.name =3D "scaler", \ @@ -329,6 +348,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_3 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 4)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =3D + _KAANAPALI_VIG_SBLK(SSPP_SCALER_VER(3, 5)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -412,6 +434,11 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sb= lk =3D { .len =3D 0x20, .version =3D 0x20000}, }; =20 +static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk =3D { + .dither =3D {.name =3D "dither", .base =3D 0xc0, + .len =3D 0x40, .version =3D 0x30000}, +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -452,6 +479,13 @@ static const struct dpu_cdm_cfg dpu_cdm_5_x =3D { .base =3D 0x79200, }; =20 +static const struct dpu_cdm_cfg dpu_cdm_kaanapali_x =3D { + .name =3D "cdm_0", + .id =3D CDM_0, + .len =3D 0x240, + .base =3D 0x19e000, +}; + /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -639,6 +673,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linea= r[] =3D { {.fl =3D 0, .lut =3D 0x0011222222335777}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_linear[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] =3D { {.fl =3D 0, .lut =3D 0x0011223445566777 }, }; @@ -668,6 +706,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macro= tile[] =3D { {.fl =3D 0, .lut =3D 0x0011223344556677}, }; =20 +static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] =3D { + {.fl =3D 0, .lut =3D 0x0011223344556666}, +}; + static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] =3D { {.fl =3D 10, .lut =3D 0x0000000344556677}, }; @@ -726,3 +768,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_10_0_sm8650.h" #include "catalog/dpu_12_0_sm8750.h" +#include "catalog/dpu_13_0_kaanapali.h" + diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f0768f54e9b3..99c81c24630f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -208,6 +208,30 @@ struct dpu_dsc_blk { u32 len; }; =20 +/** + * struct dpu_sspp_rec_blk - sspp rec sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_rec_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + +/** + * struct dpu_sspp_cmn_blk - sspp common sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_cmn_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + /** * enum dpu_qos_lut_usage - define QoS LUT use cases */ @@ -294,7 +318,9 @@ struct dpu_sspp_sub_blks { u32 qseed_ver; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; - + struct dpu_sspp_cmn_blk cmn_blk; + struct dpu_sspp_rec_blk sspp_rec0_blk; + struct dpu_sspp_rec_blk sspp_rec1_blk; const u32 *format_list; u32 num_formats; const struct dpu_rotation_cfg *rotation_cfg; @@ -778,6 +804,7 @@ extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; extern const struct dpu_mdss_cfg dpu_sm8750_cfg; +extern const struct dpu_mdss_cfg dpu_kaanapali_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 4e5a8ecd31f7..15bec44324d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { }; =20 static const struct of_device_id dpu_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-dpu", .data =3D &dpu_kaanapali_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.34.1