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charset="utf-8" Add cooling-maps to the cpu1, cpu2, and cpu3 thermal zones to associate passive trip points with CPU cooling devices. This enables proper thermal mitigation by allowing the thermal framework to throttle CPUs based on temperature thresholds. Also, label the trip points to allow referencing them in the cooling maps. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 61 +++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index ef2b52f3597d..e4a51eeefeac 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -57,6 +58,7 @@ cpu0: cpu@0 { clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells =3D <2>; =20 l2_0: l2-cache { compatible =3D "cache"; @@ -82,6 +84,7 @@ cpu1: cpu@100 { clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells =3D <2>; =20 l2_100: l2-cache { compatible =3D "cache"; @@ -101,6 +104,7 @@ cpu2: cpu@200 { clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells =3D <2>; =20 l2_200: l2-cache { compatible =3D "cache"; @@ -120,6 +124,7 @@ cpu3: cpu@300 { clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells =3D <2>; =20 l2_300: l2-cache { compatible =3D "cache"; @@ -1235,18 +1240,28 @@ cpu0-thermal { thermal-sensors =3D <&tsens 14>; =20 trips { - cpu-critical { + cpu0_crit: cpu-critical { temperature =3D <120000>; hysteresis =3D <9000>; type =3D "critical"; }; =20 - cpu-passive { + cpu0_alert: cpu-passive { temperature =3D <110000>; hysteresis =3D <9000>; type =3D "passive"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu1-thermal { @@ -1254,18 +1269,28 @@ cpu1-thermal { thermal-sensors =3D <&tsens 12>; =20 trips { - cpu-critical { + cpu1_crit: cpu-critical { temperature =3D <120000>; hysteresis =3D <9000>; type =3D "critical"; }; =20 - cpu-passive { + cpu1_alert: cpu-passive { temperature =3D <110000>; hysteresis =3D <9000>; type =3D "passive"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu2-thermal { @@ -1273,18 +1298,28 @@ cpu2-thermal { thermal-sensors =3D <&tsens 11>; =20 trips { - cpu-critical { + cpu2_crit: cpu-critical { temperature =3D <120000>; hysteresis =3D <9000>; type =3D "critical"; }; =20 - cpu-passive { + cpu2_alert: cpu-passive { temperature =3D <110000>; hysteresis =3D <9000>; type =3D "passive"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu3-thermal { @@ -1292,18 +1327,28 @@ cpu3-thermal { thermal-sensors =3D <&tsens 13>; =20 trips { - cpu-critical { + cpu3_crit: cpu-critical { temperature =3D <120000>; hysteresis =3D <9000>; type =3D "critical"; }; =20 - cpu-passive { + cpu3_alert: cpu-passive { temperature =3D <110000>; hysteresis =3D <9000>; type =3D "passive"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 wcss-tile2-thermal { base-commit: fe45352cd106ae41b5ad3f0066c2e54dbb2dfd70 --=20 2.34.1