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charset="utf-8" Add a GPIO-controlled regulator node for the CPU rail on the IPQ5424 RDP466 platform. This regulator supports two voltage levels 850mV and 1000mV. Update CPU nodes to reference the regulator via the `cpu-supply` property, and add the required pinctrl configuration for GPIO17. Signed-off-by: Manikanta Mylavarapu --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 24 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 738618551203..6d14eb2fe821 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -46,6 +46,23 @@ led-0 { }; }; =20 + vreg_apc: regulator-vreg-apc { + compatible =3D "regulator-gpio"; + regulator-name =3D "vreg_apc"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <250>; + + gpios =3D <&tlmm 17 GPIO_ACTIVE_HIGH>; + gpios-states =3D <1>; + states =3D <850000 0>, <1000000 1>; + + pinctrl-0 =3D <®ulator_gpio_default>; + pinctrl-names =3D "default"; + }; + vreg_misc_3p3: regulator-usb-3p3 { compatible =3D "regulator-fixed"; regulator-min-microvolt =3D <3300000>; @@ -171,6 +188,13 @@ gpio_leds_default: gpio-leds-default-state { bias-pull-down; }; =20 + regulator_gpio_default: regulator-gpio-default-state { + pins =3D "gpio17"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + spi0_default_state: spi0-default-state { clk-pins { pins =3D "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index ef2b52f3597d..70702c80c626 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -56,6 +56,7 @@ cpu0: cpu@0 { clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; + cpu-supply =3D <&vreg_apc>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_0: l2-cache { @@ -81,6 +82,7 @@ cpu1: cpu@100 { clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; + cpu-supply =3D <&vreg_apc>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_100: l2-cache { @@ -100,6 +102,7 @@ cpu2: cpu@200 { clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; + cpu-supply =3D <&vreg_apc>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_200: l2-cache { @@ -119,6 +122,7 @@ cpu3: cpu@300 { clocks =3D <&apss_clk APSS_SILVER_CORE_CLK>; clock-names =3D "cpu"; operating-points-v2 =3D <&cpu_opp_table>; + cpu-supply =3D <&vreg_apc>; interconnects =3D <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; =20 l2_300: l2-cache { base-commit: fe45352cd106ae41b5ad3f0066c2e54dbb2dfd70 --=20 2.34.1