From nobody Fri Dec 19 20:40:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 667C2344037; Thu, 23 Oct 2025 17:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239755; cv=none; b=t9r5HhJkHfwF4kNQyeMMfdeoG+5IGOHztwkNHcKUuS26MpFk3FwPNeXDLiuczFugRyHywSdsBDZJlouP7NZU7RPiC8AGNEVvFYLBtr+J2ZctU6eLkvdXUFw49dn1goM6h0j12yhxixF7pBvW9VAHqurJ5TamdGnzV3i0+ZsVhkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239755; c=relaxed/simple; bh=sJLV+AOEgXSDa+76TCJd6A5exrvjVAAgqdATPU6u/0g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E23oXnTEWmezy/e0gMZfKc0YDWryQbnBzUauwroHkdg1bq2cbzfiYz7tiPl9pHqPfhJ1tC7BLIashemCvocLf57RsvRoDxy0moeBScLE220olgnDVk7lZmaoaPhKd6F1RhEPS0Q+xrcZTzKoGVZUy4cyN5+qqLCgheNCSnVcYJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BdQ7IK3l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BdQ7IK3l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2E7E2C4CEFF; Thu, 23 Oct 2025 17:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761239755; bh=sJLV+AOEgXSDa+76TCJd6A5exrvjVAAgqdATPU6u/0g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BdQ7IK3lFjx3W3LDbvv2u8y1m3dM+v5LSY4Y+7E4Xccom48eGnDdn/o+xjPSPBkcM i0N+V68P4qMfkFei3OJUYo1cZXvMPs/Y+NlQNApCECg86FCWW2M+yRVplIh7UP6yeV fUEnYRJEbEskmWFuJBokJNYc2alEBdQX6FDpEAQhrig5DGmJ2u5OFM4ozC8kiEgdKB ZfNkvvaj0I2NBkL5DX9rlgL+yoGLgrOBmLQ7NgkeniTHdVJJLyvrWK8AKruigdcPb6 nkHZxzZ2RXAQLEV/ACQCwtEkJ9RZJEcW3Kbo0hcthzFopDCv8ztzoqt9+9+rCubRK2 zPRrcip5IqpXQ== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v4 1/5] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux Date: Thu, 23 Oct 2025 18:14:57 +0100 Message-ID: <20251023-charred-uncoiled-5ec60dca2e0e@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251023-stopwatch-cough-47d5497be5aa@spud> References: <20251023-stopwatch-cough-47d5497be5aa@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4079; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=exFz1am8XBDJshVdMiZMDOl7XpxMcq7ppZnXc7V2LIk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBm/kiYUfo7gZD3eECb2XDQ1TmNr5tq/19JPljr1ZPx2X qGg+yK9o5SFQYyLQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABNJfcrIcMbwpuRL7xVBUe9K J9zgfnup1rJB6VvMjpItn2/MTJXQ6WP4H3OWwZJjgsLiUJ836nlODybwpVdv1N74q0z+/t/dhbP YGAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Currently there is no documentation about what each bit actually does that is publicly available, nor (I believe) what pins are affected. That info is as follows: pin role (1/0) Reviewed-by: Rob Herring (Arm) --- ---------- E14 MAC_0_MDC/GPIO_2_0 E15 MAC_0_MDIO/GPIO_2_1 F16 MAC_1_MDC/GPIO_2_2 F17 MAC_1_MDIO/GPIO_2_3 D19 SPI_0_CLK/GPIO_2_4 B18 SPI_0_SS0/GPIO_2_5 B10 CAN_0_RXBUS/GPIO_2_6 C14 PCIE_PERST_2#/GPIO_2_7 E18 PCIE_WAKE#/GPIO_2_8 D18 PCIE_PERST_1#/GPIO_2_9 E19 SPI_0_DO/GPIO_2_10 C7 SPI_0_DI/GPIO_2_11 D6 QSPI_SS0/GPIO_2_12 D7 QSPI_CLK (B)/GPIO_2_13 C9 QSPI_DATA0/GPIO_2_14 C10 QSPI_DATA1/GPIO_2_15 A5 QSPI_DATA2/GPIO_2_16 A6 QSPI_DATA3/GPIO_2_17 D8 MMUART_3_RXD/GPIO_2_18 D9 MMUART_3_TXD/GPIO_2_19 B8 MMUART_4_RXD/GPIO_2_20 A8 MMUART_4_TXD/GPIO_2_21 C12 CAN_1_TXBUS/GPIO_2_22 B12 CAN_1_RXBUS/GPIO_2_23 A11 CAN_0_TX_EBL_N/GPIO_2_24 A10 CAN_1_TX_EBL_N/GPIO_2_25 D11 MMUART_2_RXD/GPIO_2_26 C11 MMUART_2_TXD/GPIO_2_27 B9 CAN_0_TXBUS/GPIO_2_28 Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../microchip,pic64gx-pinctrl-gpio2.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic= 64gx-pinctrl-gpio2.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pi= nctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic6= 4gx-pinctrl-gpio2.yaml new file mode 100644 index 000000000000..e3792679de58 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-g= pio2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux via iomux0 for settings here to have any impact. + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, = uart2, gpio ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1= , uart2, + gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, + gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2= ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@41000000 { + compatible =3D "microchip,pic64gx-pinctrl-gpio2"; + reg =3D <0x41000000 0x4>; + pinctrl-use-default; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_= gpio2>, + <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gp= io2>, + <&uart2_gpio2>; + + mux-gpio2 { + function =3D "gpio"; + groups =3D "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; + }; + }; + +... --=20 2.51.0 From nobody Fri Dec 19 20:40:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5966634405A; Thu, 23 Oct 2025 17:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239757; cv=none; b=TfegzCwEpnFERaWgtNx0oH+7tks5Q6rCU7eJLhojaSOxarDA14NmpSLbge4Dh/y6CdKxC2S7qslk3gF5HdbQwBlQ3UapazSABqULcGhXevhlxKpDPtKh0iWoHOVpOpg9cd0V/luEFbNfU2ZhV1ZUwC/s96A40fbxapKvLnDWVzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239757; c=relaxed/simple; bh=1RIR6sd/TBREn2myqoXqIybk1h8ttf7pSz2j+UceWT4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ek1oAjfAOEdovJmaUOu1CTRcTRNdJmoaJe7XOgUXOav9DFFwdoug4yY2CI2XoIqQ1GK3ALVvFmX8/Nr9ax/UowyQI3V00qRRvv/fVH+V3CWAcHilUicZVd2RwcnXCNJnZ1bsytx3U9ZVSNL6q6Y7fJLY1iQHVNyAqEf4nkQQmRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=heTxKEv2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="heTxKEv2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60FC4C4CEE7; Thu, 23 Oct 2025 17:15:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761239757; bh=1RIR6sd/TBREn2myqoXqIybk1h8ttf7pSz2j+UceWT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=heTxKEv2DwSF7DCE262Aoanc7lGGGeCiApbOM5gDXo4BSFvXFB+tBtNvfh/+v4Jr7 l44qMuqYJApVtvL+r1uVXd+4GQRbEYutr9z41yvtvYoX8CkJzzmulG36+8a3eSfPgW +sxVz1bEfIrXrhWfv8FXVfBjzkeyjAu62GdlqM4sUJJ450oI0zBNOGqyuJtW6PeO8x pen1/Ebl2PozUVGIgDuRX3FXLmWYswm1bk9sKOknjcLLB+q2loawE/nZDYYlUOYrd+ 0t7jX0RLz0MPwcPWuCOf8ytnXesmIsP4uB9woSV7n77BHZkvH6H0tiLaK783F0O85N 64sBctaHOIpXg== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v4 2/5] pinctrl: add pic64gx "gpio2" pinmux driver Date: Thu, 23 Oct 2025 18:14:58 +0100 Message-ID: <20251023-share-regular-587d627d5660@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251023-stopwatch-cough-47d5497be5aa@spud> References: <20251023-stopwatch-cough-47d5497be5aa@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12131; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=81hTZ4qEz/0MgkwoUR5e217Jfv2h0ZsKkrTXugpFNag=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBm/kiaWK355qTHD/sOpq1sdK//4Pa/9pp1gVfhm7t5z7 5YcnXJjYUcpC4MYF4OsmCJL4u2+Fqn1f1x2OPe8hZnDygQyhIGLUwBushEjwwvu5Uubz1xulNA4 eX6L/gKPqs/y3o2X7Y41iMvJz/js95iR4aVMbfD1fYeVi59N49ybNflh3YR0u3cC0UZd3EzzNLx mMgIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Add a driver for it. Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-pic64gx-gpio2.c | 356 ++++++++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-pic64gx-gpio2.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4f8507ebbdac..e83fda9bf308 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -486,6 +486,14 @@ config PINCTRL_PIC32MZDA def_bool y if PIC32MZDA select PINCTRL_PIC32 =20 +config PINCTRL_PIC64GX + bool "pic64gx gpio2 pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for gpio2 on pic64gx. + config PINCTRL_PISTACHIO bool "IMG Pistachio SoC pinctrl driver" depends on OF && (MIPS || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e0cfb9b7c99b..f33976a6c91b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) +=3D pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_PALMAS) +=3D pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o +obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/pinc= trl-pic64gx-gpio2.c new file mode 100644 index 000000000000..f322bb5e6181 --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define PIC64GX_PINMUX_REG 0x0 + +static const struct regmap_config pic64gx_gpio2_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D 0x0, +}; + +struct pic64gx_gpio2_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct pic64gx_gpio2_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 setting; +}; + +struct pic64gx_gpio2_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const struct pinctrl_pin_desc pic64gx_gpio2_pins[] =3D { + PINCTRL_PIN(0, "E14"), + PINCTRL_PIN(1, "E15"), + PINCTRL_PIN(2, "F16"), + PINCTRL_PIN(3, "F17"), + PINCTRL_PIN(4, "D19"), + PINCTRL_PIN(5, "B18"), + PINCTRL_PIN(6, "B10"), + PINCTRL_PIN(7, "C14"), + PINCTRL_PIN(8, "E18"), + PINCTRL_PIN(9, "D18"), + PINCTRL_PIN(10, "E19"), + PINCTRL_PIN(11, "C7"), + PINCTRL_PIN(12, "D6"), + PINCTRL_PIN(13, "D7"), + PINCTRL_PIN(14, "C9"), + PINCTRL_PIN(15, "C10"), + PINCTRL_PIN(16, "A5"), + PINCTRL_PIN(17, "A6"), + PINCTRL_PIN(18, "D8"), + PINCTRL_PIN(19, "D9"), + PINCTRL_PIN(20, "B8"), + PINCTRL_PIN(21, "A8"), + PINCTRL_PIN(22, "C12"), + PINCTRL_PIN(23, "B12"), + PINCTRL_PIN(24, "A11"), + PINCTRL_PIN(25, "A10"), + PINCTRL_PIN(26, "D11"), + PINCTRL_PIN(27, "C11"), + PINCTRL_PIN(28, "B9"), +}; + +static const unsigned int pic64gx_gpio2_mdio0_pins[] =3D { + 0, 1 +}; + +static const unsigned int pic64gx_gpio2_mdio1_pins[] =3D { + 2, 3 +}; + +static const unsigned int pic64gx_gpio2_spi0_pins[] =3D { + 4, 5, 10, 11 +}; + +static const unsigned int pic64gx_gpio2_can0_pins[] =3D { + 6, 24, 28 +}; + +static const unsigned int pic64gx_gpio2_pcie_pins[] =3D { + 7, 8, 9 +}; + +static const unsigned int pic64gx_gpio2_qspi_pins[] =3D { + 12, 13, 14, 15, 16, 17 +}; + +static const unsigned int pic64gx_gpio2_uart3_pins[] =3D { + 18, 19 +}; + +static const unsigned int pic64gx_gpio2_uart4_pins[] =3D { + 20, 21 +}; + +static const unsigned int pic64gx_gpio2_can1_pins[] =3D { + 22, 23, 25 +}; + +static const unsigned int pic64gx_gpio2_uart2_pins[] =3D { + 26, 27 +}; + +#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \ + .name =3D "gpio_" #_name, \ + .pins =3D pic64gx_gpio2_##_name##_pins, \ + .num_pins =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask =3D _mask, \ + .setting =3D 0x0, \ +}, { \ + .name =3D #_name, \ + .pins =3D pic64gx_gpio2_##_name##_pins, \ + .num_pins =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask =3D _mask, \ + .setting =3D _mask, \ +} + +static const struct pic64gx_gpio2_pin_group pic64gx_gpio2_pin_groups[] =3D= { + PIC64GX_PINCTRL_GROUP(mdio0, BIT(0) | BIT(1)), + PIC64GX_PINCTRL_GROUP(mdio1, BIT(2) | BIT(3)), + PIC64GX_PINCTRL_GROUP(spi0, BIT(4) | BIT(5) | BIT(10) | BIT(11)), + PIC64GX_PINCTRL_GROUP(can0, BIT(6) | BIT(24) | BIT(28)), + PIC64GX_PINCTRL_GROUP(pcie, BIT(7) | BIT(8) | BIT(9)), + PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)), + PIC64GX_PINCTRL_GROUP(uart3, BIT(18) | BIT(19)), + PIC64GX_PINCTRL_GROUP(uart4, BIT(20) | BIT(21)), + PIC64GX_PINCTRL_GROUP(can1, BIT(22) | BIT(23) | BIT(25)), + PIC64GX_PINCTRL_GROUP(uart2, BIT(26) | BIT(27)), +}; + +static const char * const pic64gx_gpio2_gpio_groups[] =3D { + "gpio_mdio0", "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1", "gpio_uart2" +}; + +static const char * const pic64gx_gpio2_mdio0_groups[] =3D { + "mdio0" +}; + +static const char * const pic64gx_gpio2_mdio1_groups[] =3D { + "mdio1" +}; + +static const char * const pic64gx_gpio2_spi0_groups[] =3D { + "spi0" +}; + +static const char * const pic64gx_gpio2_can0_groups[] =3D { + "can0" +}; + +static const char * const pic64gx_gpio2_pcie_groups[] =3D { + "pcie" +}; + +static const char * const pic64gx_gpio2_qspi_groups[] =3D { + "qspi" +}; + +static const char * const pic64gx_gpio2_uart3_groups[] =3D { + "uart3" +}; + +static const char * const pic64gx_gpio2_uart4_groups[] =3D { + "uart4" +}; + +static const char * const pic64gx_gpio2_can1_groups[] =3D { + "can1" +}; + +static const char * const pic64gx_gpio2_uart2_groups[] =3D { + "uart2" +}; + +#define PIC64GX_PINCTRL_FUNCTION(_name) { \ + .name =3D #_name, \ + .groups =3D pic64gx_gpio2_##_name##_groups, \ + .num_groups =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_groups), \ +} + +static const struct pic64gx_gpio2_function pic64gx_gpio2_functions[] =3D { + PIC64GX_PINCTRL_FUNCTION(gpio), + PIC64GX_PINCTRL_FUNCTION(mdio0), + PIC64GX_PINCTRL_FUNCTION(mdio1), + PIC64GX_PINCTRL_FUNCTION(spi0), + PIC64GX_PINCTRL_FUNCTION(can0), + PIC64GX_PINCTRL_FUNCTION(pcie), + PIC64GX_PINCTRL_FUNCTION(qspi), + PIC64GX_PINCTRL_FUNCTION(uart3), + PIC64GX_PINCTRL_FUNCTION(uart4), + PIC64GX_PINCTRL_FUNCTION(can1), + PIC64GX_PINCTRL_FUNCTION(uart2), +}; + +static void pic64gx_gpio2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, stru= ct seq_file *seq, + unsigned int pin) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + u32 val; + + regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val); + val =3D (val & BIT(pin)) >> pin; + seq_printf(seq, "pin: %u val: %x\n", pin, val); +} + +static int pic64gx_gpio2_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pic64gx_gpio2_pin_groups); +} + +static const char *pic64gx_gpio2_group_name(struct pinctrl_dev *pctldev, u= nsigned int selector) +{ + return pic64gx_gpio2_pin_groups[selector].name; +} + +static int pic64gx_gpio2_group_pins(struct pinctrl_dev *pctldev, unsigned = int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins =3D pic64gx_gpio2_pin_groups[selector].pins; + *num_pins =3D pic64gx_gpio2_pin_groups[selector].num_pins; + + return 0; +} + +static const struct pinctrl_ops pic64gx_gpio2_pinctrl_ops =3D { + .get_groups_count =3D pic64gx_gpio2_groups_count, + .get_group_name =3D pic64gx_gpio2_group_name, + .get_group_pins =3D pic64gx_gpio2_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinctrl_utils_free_map, + .pin_dbg_show =3D pic64gx_gpio2_pin_dbg_show, +}; + +static int pic64gx_gpio2_pinmux_get_funcs_count(struct pinctrl_dev *pctlde= v) +{ + return ARRAY_SIZE(pic64gx_gpio2_functions); +} + +static const char *pic64gx_gpio2_pinmux_get_func_name(struct pinctrl_dev *= pctldev, + unsigned int selector) +{ + return pic64gx_gpio2_functions[selector].name; +} + +static int pic64gx_gpio2_pinmux_get_groups(struct pinctrl_dev *pctldev, un= signed int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D pic64gx_gpio2_functions[selector].groups; + *num_groups =3D pic64gx_gpio2_functions[selector].num_groups; + + return 0; +} + +static int pic64gx_gpio2_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, uns= igned int fsel, + unsigned int gsel) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + struct device *dev =3D pctrl->dev; + const struct pic64gx_gpio2_pin_group *group; + const struct pic64gx_gpio2_function *function; + + group =3D &pic64gx_gpio2_pin_groups[gsel]; + function =3D &pic64gx_gpio2_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, PIC64GX_PINMUX_REG, group->mask, group-= >setting); + + return 0; +} + +static const struct pinmux_ops pic64gx_gpio2_pinmux_ops =3D { + .get_functions_count =3D pic64gx_gpio2_pinmux_get_funcs_count, + .get_function_name =3D pic64gx_gpio2_pinmux_get_func_name, + .get_function_groups =3D pic64gx_gpio2_pinmux_get_groups, + .set_mux =3D pic64gx_gpio2_pinmux_set_mux, +}; + +static int pic64gx_gpio2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pic64gx_gpio2_pinctrl *pctrl; + void __iomem *base; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "Failed get resource\n"); + return PTR_ERR(base); + } + + pctrl->regmap =3D devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_regmap_= config); + if (IS_ERR(pctrl->regmap)) { + dev_err(dev, "Failed to map regmap\n"); + return PTR_ERR(pctrl->regmap); + } + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D pic64gx_gpio2_pins; + pctrl->desc.npins =3D ARRAY_SIZE(pic64gx_gpio2_pins); + pctrl->desc.pctlops =3D &pic64gx_gpio2_pinctrl_ops; + pctrl->desc.pmxops =3D &pic64gx_gpio2_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id pic64gx_gpio2_of_match[] =3D { + { .compatible =3D "microchip,pic64gx-pinctrl-gpio2" }, + { } +}; +MODULE_DEVICE_TABLE(of, pic64gx_gpio2_of_match); + +static struct platform_driver pic64gx_gpio2_driver =3D { + .driver =3D { + .name =3D "pic64gx-pinctrl-gpio2", + .of_match_table =3D pic64gx_gpio2_of_match, + }, + .probe =3D pic64gx_gpio2_probe, +}; +module_platform_driver(pic64gx_gpio2_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Fri Dec 19 20:40:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0B11345CC4; Thu, 23 Oct 2025 17:15:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239759; cv=none; b=RNxIX5D1zDH4e8Wag0llZpqbBkZfQRiYO/hq+JUA0OpMrOEhe6hLszFXYS0zW/H1Xqktutecmd9CwiymRSc1qy/lZu6/KKobMdZZH6TvqGdZGmCIhg/vSEYbMVveEnMv9o9+H9PV0JXFMTEvic+8nip745ROsHkqpmaAftvnQzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239759; c=relaxed/simple; bh=ttHPVffNl2GANNze4h4Gh+P6qAE5Zl9xo7sVI2L9ZU8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uZknW0X02XvfKC/yCy/T/4RcxMceMS/XObMARbFe0ZCseKeIwVNvdsDulsOE5nXz8vQjBeCU2S9BP9w/6wvSYyygl8tdeNUeH65iC0x40hv0tfHUsnDxEeLgEmXVc/PZwPH49VaQGlZFeoC4MMwfq1f/C5LEwvb2bDfuM3qCGyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oLIJCgou; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oLIJCgou" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93668C113D0; Thu, 23 Oct 2025 17:15:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761239759; bh=ttHPVffNl2GANNze4h4Gh+P6qAE5Zl9xo7sVI2L9ZU8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oLIJCgoutxtTs5S4P9dCraInt+omDM17L5u9jztEauvqsIYukkX+NMl5gMtYHItJx NT8BzX31Gv/C72I4gxY0dN2Q85Nsl4m3HybYwj6PqRKbbscwQ7P97BuduAtJbuNwtd m0vEa+XVAjE2NExn0G+pEWp9Tptp+ZUCJaTi4ezqpz2Zph0dlvIEm9x3CqJDaSxQ8g W4re3kboCEfculLS+Oney24ecmJfBV293HHV9CDYBl5v75iGlJ3j+dVlk4/xEiLs+l n3FHGr3El4K1avk3pR56yLbD1cov+TZKpe5bpX9pVIJ+wlD9cMW0aOSAz4AAQtkR9a 4MmIv4pH8iukw== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v4 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux Date: Thu, 23 Oct 2025 18:14:59 +0100 Message-ID: <20251023-polka-plunder-1376b734c72c@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251023-stopwatch-cough-47d5497be5aa@spud> References: <20251023-stopwatch-cough-47d5497be5aa@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4853; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=7d4ab0FAvzd52dMlnhHDv/DB9u7Voznk7u8VEd9E7Uc=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBm/kiZ2p+0Rmrfx32eWy/PWbOZj7Vm8OOmubrjUdqa3T pF37+390FHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ3J/PyHDSyKjoR3R8yr7C 5cdTFvm9m+3y6vBvgw1MOzSCkzYdnXCJkaGx175MtUf+9aWepXcWbbPu6JIV9s25tqzVRDHr+DQ hAXYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../microchip,mpfs-pinctrl-iomux0.yaml | 89 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 13 ++- 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpf= s-pinctrl-iomux0.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinct= rl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-p= inctrl-iomux0.yaml new file mode 100644 index 000000000000..3c98eb35fb82 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomu= x0.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley + +description: + iomux0 is responsible for routing some functions to either the FPGA fabr= ic, + or to MSSIOs. It only performs muxing, and has no IO configuration role,= as + fabric IOs are configured separately and just routing a function to MSSI= Os is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, ua= rt2, + uart3, uart4, mdio0, mdio1 ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_f= abric, + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_m= ssio, + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio, + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio, + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio, + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio, + mdio1_fabric, mdio1_mssio ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #size-cells =3D <1>; + #address-cells =3D <1>; + + pinctrl@200 { + compatible =3D "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + + mux-spi0-fabric { + function =3D "spi0"; + groups =3D "spi0_fabric"; + }; + + mux-spi1-mssio { + function =3D "spi1"; + groups =3D "spi1_mssio"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 1ab691db8795..39987f722411 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -18,10 +18,17 @@ properties: items: - const: microchip,mpfs-mss-top-sysreg - const: syscon + - const: simple-mfd =20 reg: maxItems: 1 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#reset-cells': description: The AHB/AXI peripherals on the PolarFire SoC have reset support, so @@ -31,6 +38,10 @@ properties: of PolarFire clock/reset IDs. const: 1 =20 + pinctrl@200: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + required: - compatible - reg @@ -40,7 +51,7 @@ additionalProperties: false examples: - | syscon@20002000 { - compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mf= d"; reg =3D <0x20002000 0x1000>; #reset-cells =3D <1>; }; --=20 2.51.0 From nobody Fri Dec 19 20:40:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26FC7238C2A; Thu, 23 Oct 2025 17:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239762; cv=none; b=c+H9oLGLCxIzG96d/TGcxUuO7cIPpYb+k2CoLz/2SZDVBEi2W2lmutE82UXB3cvdoEDxYkCpEKCTmW0ZoPEgrC8/XMB4KNiJRltO2D/mxs93Xb1arHFkoryZiHxdAHcZpUy51tIZAcY4mSW0v0O1V6BBy9rz/v4lYAu55eySPLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761239762; c=relaxed/simple; bh=USKbnz/WWtmRAu/WsgpdJwkstKtmlsjlsNtL8jTy6Fw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z2W2rqX+9OEOkLTic/8sixAQv4EVrSLI9mg7U3mG03wWUhbbT/VMqmRgUlVGMfIcnJnwDFfb8xrn6qHIsriprqFrO0RmwLKkidgcvSuxTA+AdTi8GCXv438jDhG75BgUaHkNZ7++2ZjYP7yC1yC7MRRlfcUqlkZEhkllWBl7FOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bHP8BhKp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bHP8BhKp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5A6AC4CEE7; Thu, 23 Oct 2025 17:15:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761239761; bh=USKbnz/WWtmRAu/WsgpdJwkstKtmlsjlsNtL8jTy6Fw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bHP8BhKpIKTpQRytdcJX2VF1LdlaWvIbhTdU2/cxonQdXN+Kmal8uhfnFv6Je41xe jvxD3vXR0E44tITvWAg6mdnldKDwjJqH9JL2prtfAf84cZwk2nl0DXNZozYrs3+Y53 NPyCcQ43QkqvWIdQLo2KXhV6F19W8FH96IuGRuhKZK92VduM1h//LVfycwNAqjBPuV 1qoBNJtplqux90zHeJcUdf1r7y43rebp0h/JWzQvwp/E9fKJCAhY1YWkJSSmmbJqwf A0QQeUEPWebbZF9wjrtqh41gb1Mq80wXq756zYEeoyD8mA0j1pcYn7/Yk/SbVc6YdM 9joTOw4Q1SyLw== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v4 4/5] pinctrl: add polarfire soc iomux0 pinmux driver Date: Thu, 23 Oct 2025 18:15:00 +0100 Message-ID: <20251023-challenge-facecloth-339abdf3513f@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251023-stopwatch-cough-47d5497be5aa@spud> References: <20251023-stopwatch-cough-47d5497be5aa@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11389; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=FspkpCwBeD2MbueZeRJsfAuxKRuAcH0xEJ18CVdNA/o=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBm/kibWKOScMVgl+6BUTqnT+n5PYkTWr3CdZGPLrx0bj p2ymBbaUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgInY+jMyvHk+y/XsIk8Z2xjL vfy2/EFNXyJ3bjhs+pM1+3/b22MPFRgZ3t1KvN97yi/uhbuhvp141lTWCQEXdzMvk3mXmPrPttS bFwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Add a driver for it. Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mpfs-iomux0.c | 278 ++++++++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-mpfs-iomux0.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e83fda9bf308..4ec2bb7f67cf 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -505,6 +505,14 @@ config PINCTRL_PISTACHIO help This support pinctrl and GPIO driver for IMG Pistachio SoC. =20 +config PINCTRL_POLARFIRE_SOC + bool "Polarfire SoC pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for Microchip Polarfire SoC. + config PINCTRL_RK805 tristate "Pinctrl and GPIO driver for RK805 PMIC" depends on MFD_RK8XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f33976a6c91b..ea4e890766e1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RP1) +=3D pinctrl-rp1.o diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctr= l-mpfs-iomux0.c new file mode 100644 index 000000000000..49d9fcec0a16 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define MPFS_IOMUX0_REG 0x200 + +struct mpfs_iomux0_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct mpfs_iomux0_pin_group { + const char *name; + const unsigned int *pins; + u32 mask; + u32 setting; +}; + +struct mpfs_iomux0_function { + const char *name; + const char * const *groups; +}; + +static const struct pinctrl_pin_desc mpfs_iomux0_pins[] =3D { + PINCTRL_PIN(0, "spi0"), + PINCTRL_PIN(1, "spi1"), + PINCTRL_PIN(2, "i2c0"), + PINCTRL_PIN(3, "i2c1"), + PINCTRL_PIN(4, "can0"), + PINCTRL_PIN(5, "can1"), + PINCTRL_PIN(6, "qspi"), + PINCTRL_PIN(7, "uart0"), + PINCTRL_PIN(8, "uart1"), + PINCTRL_PIN(9, "uart2"), + PINCTRL_PIN(10, "uart3"), + PINCTRL_PIN(11, "uart4"), + PINCTRL_PIN(12, "mdio0"), + PINCTRL_PIN(13, "mdio1"), +}; + +static const unsigned int mpfs_iomux0_spi0_pins[] =3D { 0 }; +static const unsigned int mpfs_iomux0_spi1_pins[] =3D { 1 }; +static const unsigned int mpfs_iomux0_i2c0_pins[] =3D { 2 }; +static const unsigned int mpfs_iomux0_i2c1_pins[] =3D { 3 }; +static const unsigned int mpfs_iomux0_can0_pins[] =3D { 4 }; +static const unsigned int mpfs_iomux0_can1_pins[] =3D { 5 }; +static const unsigned int mpfs_iomux0_qspi_pins[] =3D { 6 }; +static const unsigned int mpfs_iomux0_uart0_pins[] =3D { 7 }; +static const unsigned int mpfs_iomux0_uart1_pins[] =3D { 8 }; +static const unsigned int mpfs_iomux0_uart2_pins[] =3D { 9 }; +static const unsigned int mpfs_iomux0_uart3_pins[] =3D { 10 }; +static const unsigned int mpfs_iomux0_uart4_pins[] =3D { 11 }; +static const unsigned int mpfs_iomux0_mdio0_pins[] =3D { 12 }; +static const unsigned int mpfs_iomux0_mdio1_pins[] =3D { 13 }; + +#define MPFS_IOMUX0_GROUP(_name) { \ + .name =3D #_name "_mssio", \ + .pins =3D mpfs_iomux0_##_name##_pins, \ + .mask =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting =3D 0x0, \ +}, { \ + .name =3D #_name "_fabric", \ + .pins =3D mpfs_iomux0_##_name##_pins, \ + .mask =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ +} + +static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] =3D { + MPFS_IOMUX0_GROUP(spi0), + MPFS_IOMUX0_GROUP(spi1), + MPFS_IOMUX0_GROUP(i2c0), + MPFS_IOMUX0_GROUP(i2c1), + MPFS_IOMUX0_GROUP(can0), + MPFS_IOMUX0_GROUP(can1), + MPFS_IOMUX0_GROUP(qspi), + MPFS_IOMUX0_GROUP(uart0), + MPFS_IOMUX0_GROUP(uart1), + MPFS_IOMUX0_GROUP(uart2), + MPFS_IOMUX0_GROUP(uart3), + MPFS_IOMUX0_GROUP(uart4), + MPFS_IOMUX0_GROUP(mdio0), + MPFS_IOMUX0_GROUP(mdio1), +}; + +static const char * const mpfs_iomux0_spi0_groups[] =3D { "spi0_mssio", "s= pi0_fabric" }; +static const char * const mpfs_iomux0_spi1_groups[] =3D { "spi1_mssio", "s= pi1_fabric" }; +static const char * const mpfs_iomux0_i2c0_groups[] =3D { "i2c0_mssio", "i= 2c0_fabric" }; +static const char * const mpfs_iomux0_i2c1_groups[] =3D { "i2c1_mssio", "i= 2c1_fabric" }; +static const char * const mpfs_iomux0_can0_groups[] =3D { "can0_mssio", "c= an0_fabric" }; +static const char * const mpfs_iomux0_can1_groups[] =3D { "can1_mssio", "c= an1_fabric" }; +static const char * const mpfs_iomux0_qspi_groups[] =3D { "qspi_mssio", "q= spi_fabric" }; +static const char * const mpfs_iomux0_uart0_groups[] =3D { "uart0_mssio", = "uart0_fabric" }; +static const char * const mpfs_iomux0_uart1_groups[] =3D { "uart1_mssio", = "uart1_fabric" }; +static const char * const mpfs_iomux0_uart2_groups[] =3D { "uart2_mssio", = "uart2_fabric" }; +static const char * const mpfs_iomux0_uart3_groups[] =3D { "uart3_mssio", = "uart3_fabric" }; +static const char * const mpfs_iomux0_uart4_groups[] =3D { "uart4_mssio", = "uart4_fabric" }; +static const char * const mpfs_iomux0_mdio0_groups[] =3D { "mdio0_mssio", = "mdio0_fabric" }; +static const char * const mpfs_iomux0_mdio1_groups[] =3D { "mdio1_mssio", = "mdio1_fabric" }; + +#define MPFS_IOMUX0_FUNCTION(_name) { \ + .name =3D #_name, \ + .groups =3D mpfs_iomux0_##_name##_groups, \ +} + +static const struct mpfs_iomux0_function mpfs_iomux0_functions[] =3D { + MPFS_IOMUX0_FUNCTION(spi0), + MPFS_IOMUX0_FUNCTION(spi1), + MPFS_IOMUX0_FUNCTION(i2c0), + MPFS_IOMUX0_FUNCTION(i2c1), + MPFS_IOMUX0_FUNCTION(can0), + MPFS_IOMUX0_FUNCTION(can1), + MPFS_IOMUX0_FUNCTION(qspi), + MPFS_IOMUX0_FUNCTION(uart0), + MPFS_IOMUX0_FUNCTION(uart1), + MPFS_IOMUX0_FUNCTION(uart2), + MPFS_IOMUX0_FUNCTION(uart3), + MPFS_IOMUX0_FUNCTION(uart4), + MPFS_IOMUX0_FUNCTION(mdio0), + MPFS_IOMUX0_FUNCTION(mdio1), +}; + +static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct= seq_file *seq, + unsigned int pin) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + + seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin); + + regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val); + val =3D (val & BIT(pin)) >> pin; + + seq_printf(seq, "val: %x\n", val); +} + +static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_pin_groups); +} + +static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, uns= igned int selector) +{ + return mpfs_iomux0_pin_groups[selector].name; +} + +static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned in= t selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins =3D mpfs_iomux0_pin_groups[selector].pins; + *num_pins =3D 1; + + return 0; +} + +static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops =3D { + .get_groups_count =3D mpfs_iomux0_groups_count, + .get_group_name =3D mpfs_iomux0_group_name, + .get_group_pins =3D mpfs_iomux0_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinctrl_utils_free_map, + .pin_dbg_show =3D mpfs_iomux0_pin_dbg_show, +}; + +static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsig= ned int fsel, + unsigned int gsel) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev =3D pctrl->dev; + const struct mpfs_iomux0_pin_group *group; + const struct mpfs_iomux0_function *function; + + group =3D &mpfs_iomux0_pin_groups[gsel]; + function =3D &mpfs_iomux0_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->se= tting); + + return 0; +} + +static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_functions); +} + +static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pc= tldev, + unsigned int selector) +{ + return mpfs_iomux0_functions[selector].name; +} + +static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsi= gned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D mpfs_iomux0_functions[selector].groups; + *num_groups =3D 2; + + return 0; +} + +static const struct pinmux_ops mpfs_iomux0_pinmux_ops =3D { + .get_functions_count =3D mpfs_iomux0_pinmux_get_funcs_count, + .get_function_name =3D mpfs_iomux0_pinmux_get_func_name, + .get_function_groups =3D mpfs_iomux0_pinmux_get_groups, + .set_mux =3D mpfs_iomux0_pinmux_set_mux, +}; + +static int mpfs_iomux0_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mpfs_iomux0_pinctrl *pctrl; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(pctrl->regmap)) + dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap= \n"); + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D mpfs_iomux0_pins; + pctrl->desc.npins =3D ARRAY_SIZE(mpfs_iomux0_pins); + pctrl->desc.pctlops =3D &mpfs_iomux0_pinctrl_ops; + pctrl->desc.pmxops =3D &mpfs_iomux0_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id mpfs_iomux0_of_match[] =3D { + { .compatible =3D "microchip,mpfs-pinctrl-iomux0" }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match); + +static struct platform_driver mpfs_iomux0_driver =3D { + .driver =3D { + .name =3D "mpfs-pinctrl-iomux0", + .of_match_table =3D mpfs_iomux0_of_match, + }, + .probe =3D mpfs_iomux0_probe, +}; +module_platform_driver(mpfs_iomux0_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Fri Dec 19 20:40:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01969346797; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LrpkYfcJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DFD4C116B1; Thu, 23 Oct 2025 17:16:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761239763; bh=OUQyFuTsycRdDJyc4s7jio9r2I2Q187UaqN1mLSvjPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LrpkYfcJ0XaHZv+npKsnZvpSxmMXlkAuGd+5ayAAY78rw2S+aliNApv3vf3RgLbiT nlf6ZhOhblexQzwhPrzuWdpng4OjFsM0opsXhzOo+gMcEwB0SPV9g2uLhE1wCUpnwA qZKzcGNHQCwHlU3PyZA8BmbnXvzyoC9yWjeKw7qbJRXBg//ZBMjA8ZH9XtWgm66ca0 digOVgEszw1qgAI1nfJb/FntE/UGpDhqUsuVZxZXMXN5rnWcrrbGMJ69FcdJ/yJuQc jLZzdGfCdn4RbC/qtNc0VeGdPrUm0z4ka/8CTq3RcM/qdRysbGaJRqQgzh75/FIaXF fKQoLhwUuHxkw== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v4 5/5] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry Date: Thu, 23 Oct 2025 18:15:01 +0100 Message-ID: <20251023-footing-tiger-61835aac1321@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251023-stopwatch-cough-47d5497be5aa@spud> References: <20251023-stopwatch-cough-47d5497be5aa@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1422; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=yIOJ8zWE39Nk9VFv1VjhPf9MABofVWCX3ryvpaofjMU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBm/kibuXMJzncUhek3nqunTeZ/tW/7Cco/N6qoXwSebD vO216rN7yhlYRDjYpAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEtDYxMnwSurz6WtQy7U6p 0NZgy5x5v9nln++rPbH4P3f3tAcyVdsYGS45vVjkevW18xc3Z6VFsm9mvnJsjMp84LVa5GL4m40 x9uwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the new gpio2 and iomux0 drivers and bindings to the existing entry for Microchip RISC-V devices. Signed-off-by: Conor Dooley --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..5d4825073fcd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22089,6 +22089,8 @@ F: Documentation/devicetree/bindings/gpio/microchip= ,mpfs-gpio.yaml F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0= .yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpi= o2.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml F: Documentation/devicetree/bindings/riscv/microchip.yaml F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-cont= roller.yaml @@ -22102,6 +22104,8 @@ F: drivers/gpio/gpio-mpfs.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/plda/pcie-microchip-host.c +F: drivers/pinctrl/pinctrl-mpfs-iomux0.c +F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c --=20 2.51.0