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+static DEFINE_IDA(db_ida); =20 /* DDR Perf hardware feature */ #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */ #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID= filter */ #define DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER 0x4 /* support AXI ID PORT CHAN= NEL filter */ =20 +/* Perf type */ +enum fsl_ddr_type { + DDR_PERF_TYPE =3D 0, /* ddr Perf (default) */ + DB_PERF_TYPE, /* db Perf */ +}; + struct fsl_ddr_devtype_data { unsigned int quirks; /* quirks needed for different DDR Perf core */ const char *identifier; /* system PMU identifier for userspace */ + enum fsl_ddr_type type; /* types of Perf, ddr or db */ }; =20 static const struct fsl_ddr_devtype_data imx8_devtype_data; @@ -98,6 +107,12 @@ static const struct fsl_ddr_devtype_data imx8dxl_devtyp= e_data =3D { .identifier =3D "i.MX8DXL", }; =20 +static const struct fsl_ddr_devtype_data imx8dxl_db_devtype_data =3D { + .quirks =3D DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER, + .identifier =3D "i.MX8DXL", + .type =3D DB_PERF_TYPE, +}; + static const struct of_device_id imx_ddr_pmu_dt_ids[] =3D { { .compatible =3D "fsl,imx8-ddr-pmu", .data =3D &imx8_devtype_data}, { .compatible =3D "fsl,imx8m-ddr-pmu", .data =3D &imx8m_devtype_data}, @@ -106,6 +121,7 @@ static const struct of_device_id imx_ddr_pmu_dt_ids[] = =3D { { .compatible =3D "fsl,imx8mn-ddr-pmu", .data =3D &imx8mn_devtype_data}, { .compatible =3D "fsl,imx8mp-ddr-pmu", .data =3D &imx8mp_devtype_data}, { .compatible =3D "fsl,imx8dxl-ddr-pmu", .data =3D &imx8dxl_devtype_data}, + { .compatible =3D "fsl,imx8dxl-db-pmu", .data =3D &imx8dxl_db_devtype_dat= a}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); @@ -290,6 +306,18 @@ static const struct attribute_group ddr_perf_events_at= tr_group =3D { .attrs =3D ddr_perf_events_attrs, }; =20 +static struct attribute *db_perf_events_attrs[] =3D { + IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID), + IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41), + IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42), + NULL, +}; + +static struct attribute_group db_perf_events_attr_group =3D { + .name =3D "events", + .attrs =3D db_perf_events_attrs, +}; + PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(axi_id, "config1:0-15"); PMU_FORMAT_ATTR(axi_mask, "config1:16-31"); @@ -310,7 +338,7 @@ static const struct attribute_group ddr_perf_format_att= r_group =3D { .attrs =3D ddr_perf_format_attrs, }; =20 -static const struct attribute_group *attr_groups[] =3D { +static const struct attribute_group *ddr_attr_groups[] =3D { &ddr_perf_events_attr_group, &ddr_perf_format_attr_group, &ddr_perf_cpumask_attr_group, @@ -319,6 +347,14 @@ static const struct attribute_group *attr_groups[] =3D= { NULL, }; =20 +static const struct attribute_group *db_attr_groups[] =3D { + &db_perf_events_attr_group, + &ddr_perf_format_attr_group, + &ddr_perf_cpumask_attr_group, + &ddr_perf_filter_cap_attr_group, + NULL, +}; + static bool ddr_perf_is_filtered(struct perf_event *event) { return event->attr.config =3D=3D 0x41 || event->attr.config =3D=3D 0x42; @@ -655,7 +691,6 @@ static void ddr_perf_init(struct ddr_pmu *pmu, void __i= omem *base, .parent =3D dev, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .task_ctx_nr =3D perf_invalid_context, - .attr_groups =3D attr_groups, .event_init =3D ddr_perf_event_init, .add =3D ddr_perf_event_add, .del =3D ddr_perf_event_del, @@ -737,6 +772,7 @@ static int ddr_perf_probe(struct platform_device *pdev) struct ddr_pmu *pmu; struct device_node *np; void __iomem *base; + struct ida *ida; char *name; int nclks; int num; @@ -761,21 +797,28 @@ static int ddr_perf_probe(struct platform_device *pde= v) if (nclks < 0) return dev_err_probe(&pdev->dev, nclks, "Failure get clks\n"); =20 - num =3D ida_alloc(&ddr_ida, GFP_KERNEL); + pmu->devtype_data =3D of_device_get_match_data(&pdev->dev); + + ida =3D pmu->devtype_data->type =3D=3D DDR_PERF_TYPE ? &ddr_ida : &db_ida; + num =3D ida_alloc(ida, GFP_KERNEL); if (num < 0) return num; =20 pmu->id =3D num; =20 - name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", - num); + if (pmu->devtype_data->type =3D=3D DDR_PERF_TYPE) { + pmu->pmu.attr_groups =3D ddr_attr_groups; + name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", = num); + } else { + pmu->pmu.attr_groups =3D db_attr_groups; + name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, DB_PERF_DEV_NAME "%d", n= um); + } + if (!name) { ret =3D -ENOMEM; goto idr_free; } =20 - pmu->devtype_data =3D of_device_get_match_data(&pdev->dev); - pmu->cpu =3D raw_smp_processor_id(); ret =3D cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DDR_CPUHP_CB_NAME, @@ -832,7 +875,7 @@ static int ddr_perf_probe(struct platform_device *pdev) cpuhp_instance_err: cpuhp_remove_multi_state(pmu->cpuhp_state); idr_free: - ida_free(&ddr_ida, pmu->id); + ida_free(ida, pmu->id); dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret); return ret; } @@ -846,7 +889,11 @@ static void ddr_perf_remove(struct platform_device *pd= ev) =20 perf_pmu_unregister(&pmu->pmu); =20 - ida_free(&ddr_ida, pmu->id); + if (pmu->devtype_data->type =3D=3D DDR_PERF_TYPE) + ida_free(&ddr_ida, pmu->id); + else + ida_free(&db_ida, pmu->id); + } =20 static struct platform_driver imx_ddr_pmu_driver =3D { --=20 2.34.1