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Wed, 22 Oct 2025 15:08:11 -0700 (PDT) From: Usama Arif To: dwmw@amazon.co.uk, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, ardb@kernel.org, hpa@zytor.com Cc: x86@kernel.org, apopple@nvidia.com, thuth@redhat.com, nik.borisov@suse.com, kas@kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kernel-team@meta.com, Usama Arif , Michael van der Westhuizen , Tobias Fleig Subject: [PATCH 1/3] x86/boot: Fix page table access in 5-level to 4-level paging transition Date: Wed, 22 Oct 2025 23:06:25 +0100 Message-ID: <20251022220755.1026144-2-usamaarif642@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251022220755.1026144-1-usamaarif642@gmail.com> References: <20251022220755.1026144-1-usamaarif642@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When transitioning from 5-level to 4-level paging, the existing code incorrectly accesses page table entries by directly dereferencing CR3 and applying PAGE_MASK. This approach has several issues: - __native_read_cr3() returns the raw CR3 register value, which on x86_64 includes not just the physical address but also flags. Bits above the physical address width of the system i.e. above __PHYSICAL_MASK_SHIFT) are also not masked. - The PGD entry is masked by PAGE_SIZE which doesn't take into account the higher bits such as _PAGE_BIT_NOPTISHADOW. Replace this with proper accessor functions: - read_cr3_pa(): Uses CR3_ADDR_MASK properly clearing SME encryption bit and extracting only the physical address portion. - mask pgd value with PTE_PFN_MASK instead of PAGE_MASK, accounting for flags above physical address (_PAGE_BIT_NOPTISHADOW in particular). Fixes: e9d0e6330eb8 ("x86/boot/compressed/64: Prepare new top-level page ta= ble for trampoline") Co-developed-by: Kiryl Shutsemau Signed-off-by: Kiryl Shutsemau Signed-off-by: Usama Arif Reported-by: Michael van der Westhuizen Reported-by: Tobias Fleig --- arch/x86/boot/compressed/pgtable_64.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compress= ed/pgtable_64.c index bdd26050dff77..a56449938b7ec 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -170,7 +170,8 @@ asmlinkage void configure_5level_paging(struct boot_par= ams *bp, void *pgtable) */ *trampoline_32bit =3D __native_read_cr3() | _PAGE_TABLE_NOENC; } else { - unsigned long src; + u64 *new_cr3; + pgd_t *pgdp; =20 /* * For 5- to 4-level paging transition, copy page table pointed @@ -180,8 +181,9 @@ asmlinkage void configure_5level_paging(struct boot_par= ams *bp, void *pgtable) * We cannot just point to the page table from trampoline as it * may be above 4G. */ - src =3D *(unsigned long *)__native_read_cr3() & PAGE_MASK; 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charset="utf-8" When transitioning from 5-level to 4-level paging, the existing code incorrectly accesses page table entries by directly dereferencing CR3 and applying PAGE_MASK. This approach has several issues: - __native_read_cr3() returns the raw CR3 register value, which on x86_64 includes not just the physical address but also flags Bits above the physical address width of the system (i.e. above __PHYSICAL_MASK_SHIFT) are also not masked. - The pgd value is masked by PAGE_SIZE which doesn't take into account the higher bits such as _PAGE_BIT_NOPTISHADOW. Replace this with proper accessor functions: - read_cr3_pa(): Uses CR3_ADDR_MASK properly clearing SME encryption bit and extracting only the physical address portion. - mask pgd value with PTE_PFN_MASK instead of PAGE_MASK, accounting for flags above physical address (_PAGE_BIT_NOPTISHADOW in particular). Fixes: cb1c9e02b0c1 ("x86/efistub: Perform 4/5 level paging switch from the= stub") Co-developed-by: Kiryl Shutsemau Signed-off-by: Kiryl Shutsemau Signed-off-by: Usama Arif Reported-by: Michael van der Westhuizen Reported-by: Tobias Fleig --- drivers/firmware/efi/libstub/x86-5lvl.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi= /libstub/x86-5lvl.c index f1c5fb45d5f7c..34b72da457487 100644 --- a/drivers/firmware/efi/libstub/x86-5lvl.c +++ b/drivers/firmware/efi/libstub/x86-5lvl.c @@ -81,8 +81,11 @@ void efi_5level_switch(void) new_cr3 =3D memset(pgt, 0, PAGE_SIZE); new_cr3[0] =3D (u64)cr3 | _PAGE_TABLE_NOENC; } else { + pgd_t *pgdp; + + pgdp =3D (pgd_t *)read_cr3_pa(); /* take the new root table pointer from the current entry #0 */ - new_cr3 =3D (u64 *)(cr3[0] & PAGE_MASK); + new_cr3 =3D (u64 *)(pgd_val(pgdp[0]) & PTE_PFN_MASK); =20 /* copy the new root table if it is not 32-bit addressable */ if ((u64)new_cr3 > U32_MAX) --=20 2.47.3 From nobody Sun Feb 8 09:12:28 2026 Received: from mail-yw1-f179.google.com (mail-yw1-f179.google.com [209.85.128.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9555A3074A7 for ; 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Wed, 22 Oct 2025 15:08:15 -0700 (PDT) Received: from localhost ([2a03:2880:25ff:e::]) by smtp.gmail.com with ESMTPSA id 00721157ae682-785cd6cbe09sm1215107b3.36.2025.10.22.15.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Oct 2025 15:08:14 -0700 (PDT) From: Usama Arif To: dwmw@amazon.co.uk, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, ardb@kernel.org, hpa@zytor.com Cc: x86@kernel.org, apopple@nvidia.com, thuth@redhat.com, nik.borisov@suse.com, kas@kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kernel-team@meta.com, Usama Arif , Michael van der Westhuizen , Tobias Fleig Subject: [PATCH 3/3] x86/mm: Move _PAGE_BIT_NOPTISHADOW from bit 58 to bit 9 Date: Wed, 22 Oct 2025 23:06:27 +0100 Message-ID: <20251022220755.1026144-4-usamaarif642@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251022220755.1026144-1-usamaarif642@gmail.com> References: <20251022220755.1026144-1-usamaarif642@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Kexec from a kernel with 5-level page tables to one with 4-level page tables is broken because bits above the physical address width are not properly masked by the target kernel. This issue was particularly triggered by _PAGE_BIT_NOPTISHADOW, which uses _PAGE_BIT_SOFTW5 (bit 58). The ideal fix would be to mask the upper bits properly in all kernels. However, this is not feasible due to: - The logistical challenge of patching all older kernels in production - The patch not being applicable for live patching Instead, move _PAGE_BIT_NOPTISHADOW to use _PAGE_BIT_SOFTW1 (bit 9), which is already masked by older kernels using PAGE_MASK. This is safe as the other users of _PAGE_BIT_SOFTW1 (_PAGE_BIT_SPECIAL and _PAGE_BIT_CPA_TEST) are only used for leaf entries, while _PAGE_BIT_NOPTISHADOW is used for PGD and P4D entries only. Fixes: d0ceea662d45 ("x86/mm: Add _PAGE_NOPTISHADOW bit to avoid updating u= serspace page tables") Co-developed-by: Kiryl Shutsemau Signed-off-by: Kiryl Shutsemau Signed-off-by: Usama Arif Reported-by: Michael van der Westhuizen Reported-by: Tobias Fleig --- arch/x86/include/asm/pgtable_types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pg= table_types.h index 2ec250ba467e2..616e928d87973 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -29,6 +29,8 @@ #define _PAGE_BIT_PKEY_BIT3 62 /* Protection Keys, bit 4/4 */ #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ =20 +/* _PAGE_BIT_SPECIAL and _PAGE_BIT_CPA_TEST only used for leaf entries */ +#define _PAGE_BIT_NOPTISHADOW _PAGE_BIT_SOFTW1 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1 #define _PAGE_BIT_UFFD_WP _PAGE_BIT_SOFTW2 /* userfaultfd wrprotected */ @@ -37,11 +39,9 @@ =20 #ifdef CONFIG_X86_64 #define _PAGE_BIT_SAVED_DIRTY _PAGE_BIT_SOFTW5 /* Saved Dirty bit (leaf) */ -#define _PAGE_BIT_NOPTISHADOW _PAGE_BIT_SOFTW5 /* No PTI shadow (root PGD)= */ #else /* Shared with _PAGE_BIT_UFFD_WP which is not supported on 32 bit */ #define _PAGE_BIT_SAVED_DIRTY _PAGE_BIT_SOFTW2 /* Saved Dirty bit (leaf) */ -#define _PAGE_BIT_NOPTISHADOW _PAGE_BIT_SOFTW2 /* No PTI shadow (root PGD)= */ #endif =20 /* If _PAGE_BIT_PRESENT is clear, we use these: */ --=20 2.47.3