From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAD2D346E6D; Wed, 22 Oct 2025 13:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140042; cv=none; b=oWucMRXrCladU1rYnuo8GFFmYKBz9pNSl0iqxZ0IvEE5ehoSUChVs2ru+e5a8jIj0/4hUJUedkXEtRunzLzGIP+VIkGj5kNk37rVqOdw75jbtjE4Ag9vAgLBIXtRjzulrekxYjQmKW4jTn2UYJiQjSUEcu99D1TcT4SO+fMjg2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140042; c=relaxed/simple; bh=jU+vf5SQlVP4Swy33SeL2FgxRbN1I73BEiRw5Xyp7K0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=FeSAW28rF3tzs+fmd57B128AuM4VXfwghU5QxXVF+5LkBbu/F2IkvO1yogy9fWgZURZtHgMzOnI1kVmwYhHrMCid/GV3G4Qjvnblv6ezF1ceJMKtoANoJhaE8WPtgZo5nPPq+DSIKAIQGCoDB/sEu76zSZf1GzVUourOpLqCaf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kYiOVAD5; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kYiOVAD5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761140040; x=1792676040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jU+vf5SQlVP4Swy33SeL2FgxRbN1I73BEiRw5Xyp7K0=; b=kYiOVAD5B09VT+W6PoLvxLuDJf05nUPZXvRKSvwFO2nSv4hrVbygE7Js Re2yjIsqs2PMPSbfvVHW7uQN8F6njDoK3V6B6wEh0poFJRjv9imE0ylEM BaM5s/ZCC+qmMqDpAmNZYmXwPC3XU37xT7y4h3unqmOp1lBbm78gsMy8p Crkli2tAnef9naN/Lxxxg9KHbZCUGuB757Yo98K9zni85a3pCjGsuBXMW /ckfM9C7SFLAjBKd+tZhQJ19BmgvvdoQ6RoQbbZJg2ciP3YlBhUj4xLWA 9WLLd9U+89Tcbt6cmus2AFPsuvmXJYnX+lJFBWLk7R1JCZBB7Eg2xEpFk A==; X-CSE-ConnectionGUID: q52bsIHOSjyZVcJfxOg9Wg== X-CSE-MsgGUID: //jfwOUbQjaZi0vd66GFCw== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63435370" X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="63435370" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:33:59 -0700 X-CSE-ConnectionGUID: BZUblLzJRGKkNt+NAKyQvw== X-CSE-MsgGUID: SHmZXGgBSg6Qjmz6LZ/SJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="183045441" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:33:51 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 01/11] PCI: Move Resizable BAR code into rebar.c Date: Wed, 22 Oct 2025 16:33:21 +0300 Message-Id: <20251022133331.4357-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In the lack of better place to put it, Resizable BAR code has been placed inside pci.c and setup-res.c that do not use it for anything. Upcoming changes are going to add more Resizable BAR related API functions to PCI core increasing the Resizable BAR code size from the current. As pci.c is huge file as is, extract the Resizable BAR related code out of it into rebar.c and move the actual BAR resize code from setup-res.c as well. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- Documentation/driver-api/pci/pci.rst | 3 + drivers/pci/Makefile | 2 +- drivers/pci/pci.c | 145 ---------------- drivers/pci/pci.h | 1 + drivers/pci/rebar.c | 236 +++++++++++++++++++++++++++ drivers/pci/setup-res.c | 78 --------- 6 files changed, 241 insertions(+), 224 deletions(-) create mode 100644 drivers/pci/rebar.c diff --git a/Documentation/driver-api/pci/pci.rst b/Documentation/driver-ap= i/pci/pci.rst index 59d86e827198..99a1bbaaec5d 100644 --- a/Documentation/driver-api/pci/pci.rst +++ b/Documentation/driver-api/pci/pci.rst @@ -37,6 +37,9 @@ PCI Support Library .. kernel-doc:: drivers/pci/slot.c :export: =20 +.. kernel-doc:: drivers/pci/rebar.c + :export: + .. kernel-doc:: drivers/pci/rom.c :export: =20 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 67647f1880fb..f3c81c892786 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -4,7 +4,7 @@ =20 obj-$(CONFIG_PCI) +=3D access.o bus.o probe.o host-bridge.o \ remove.o pci.o pci-driver.o search.o \ - rom.o setup-res.o irq.o vpd.o \ + rebar.o rom.o setup-res.o irq.o vpd.o \ setup-bus.o vc.o mmap.o devres.o =20 obj-$(CONFIG_PCI) +=3D msi/ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006c..aedf6a9932ce 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1823,32 +1823,6 @@ static void pci_restore_config_space(struct pci_dev = *pdev) } } =20 -static void pci_restore_rebar_state(struct pci_dev *pdev) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - pos =3D pdev->rebar_cap; - if (!pos) - return; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - struct resource *res; - int bar_idx, size; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; - res =3D pci_resource_n(pdev, bar_idx); - size =3D pci_rebar_bytes_to_size(resource_size(res)); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - } -} - /** * pci_restore_state - Restore the saved state of a PCI device * @dev: PCI device that we're dealing with @@ -3687,125 +3661,6 @@ void pci_acs_init(struct pci_dev *dev) pci_enable_acs(dev); } =20 -void pci_rebar_init(struct pci_dev *pdev) -{ - pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); -} - -/** - * pci_rebar_find_pos - find position of resize ctrl reg for BAR - * @pdev: PCI device - * @bar: BAR to find - * - * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. - */ -static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - if (pci_resource_is_iov(bar)) { - pos =3D pci_iov_vf_rebar_cap(pdev); - bar =3D pci_resource_num_to_vf_bar(bar); - } else { - pos =3D pdev->rebar_cap; - } - - if (!pos) - return -ENOTSUPP; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - int bar_idx; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); - if (bar_idx =3D=3D bar) - return pos; - } - - return -ENOENT; -} - -/** - * pci_rebar_get_possible_sizes - get possible sizes for BAR - * @pdev: PCI device - * @bar: BAR to query - * - * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. - */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) -{ - int pos; - u32 cap; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return 0; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); - - /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ - if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && - bar =3D=3D 0 && cap =3D=3D 0x700) - return 0x3f00; - - return cap; -} -EXPORT_SYMBOL(pci_rebar_get_possible_sizes); - -/** - * pci_rebar_get_current_size - get the current size of a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. - */ -int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); -} - -/** - * pci_rebar_set_size - set a new size for a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) - * - * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. - */ -int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - return 0; -} - /** * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port * @dev: the PCI device diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b..fffd0a0cc803 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1020,6 +1020,7 @@ static inline int acpi_get_rc_resources(struct device= *dev, const char *hid, #endif =20 void pci_rebar_init(struct pci_dev *pdev); +void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); static inline u64 pci_rebar_size_to_bytes(int size) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c new file mode 100644 index 000000000000..8deee5bb33fa --- /dev/null +++ b/drivers/pci/rebar.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Resizable BAR Extended Capability handling. + */ + +#include +#include +#include +#include +#include +#include + +#include "pci.h" + +void pci_rebar_init(struct pci_dev *pdev) +{ + pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); +} + +/** + * pci_rebar_find_pos - find position of resize ctrl reg for BAR + * @pdev: PCI device + * @bar: BAR to find + * + * Helper to find the position of the ctrl register for a BAR. + * Returns -ENOTSUPP if resizable BARs are not supported at all. + * Returns -ENOENT if no ctrl register for the BAR could be found. + */ +static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + if (pci_resource_is_iov(bar)) { + pos =3D pci_iov_vf_rebar_cap(pdev); + bar =3D pci_resource_num_to_vf_bar(bar); + } else { + pos =3D pdev->rebar_cap; + } + + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); + if (bar_idx =3D=3D bar) + return pos; + } + + return -ENOENT; +} + +/** + * pci_rebar_get_possible_sizes - get possible sizes for BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the possible sizes of a resizable BAR as bitmask defined in the spec + * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + */ +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && + bar =3D=3D 0 && cap =3D=3D 0x700) + return 0x3f00; + + return cap; +} +EXPORT_SYMBOL(pci_rebar_get_possible_sizes); + +/** + * pci_rebar_get_current_size - get the current size of a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * + * Read the size of a BAR from the resizable BAR config. + * Returns size if found or negative error code. + */ +int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); +} + +/** + * pci_rebar_set_size - set a new size for a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * + * Set the new size of a BAR as defined in the spec. + * Returns zero if resizing was successful, error code otherwise. + */ +int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + return 0; +} + +void pci_restore_rebar_state(struct pci_dev *pdev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos =3D pdev->rebar_cap; + if (!pos) + return; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + struct resource *res; + int bar_idx, size; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; + res =3D pci_resource_n(pdev, bar_idx); + size =3D pci_rebar_bytes_to_size(resource_size(res)); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + } +} + +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, + int resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, + int size) +{ + resource_size_t res_size =3D pci_rebar_size_to_bytes(size); + struct resource *res =3D pci_resource_n(dev, resno); + + if (!pci_resource_is_iov(resno)) { + resource_set_size(res, res_size); + } else { + resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); + pci_iov_resource_set_size(dev, resno, res_size); + } +} + +int pci_resize_resource(struct pci_dev *dev, int resno, int size) +{ + struct resource *res =3D pci_resource_n(dev, resno); + struct pci_host_bridge *host; + int old, ret; + u32 sizes; + + /* Check if we must preserve the firmware's resource assignment */ + host =3D pci_find_host_bridge(dev->bus); + if (host->preserve_config) + return -ENOTSUPP; + + /* Make sure the resource isn't assigned before resizing it. */ + if (!(res->flags & IORESOURCE_UNSET)) + return -EBUSY; + + if (pci_resize_is_memory_decoding_enabled(dev, resno)) + return -EBUSY; + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + old =3D pci_rebar_get_current_size(dev, resno); + if (old < 0) + return old; + + ret =3D pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + pci_resize_resource_set_size(dev, resno, size); + + /* Check if the new config works by trying to assign everything. */ + if (dev->bus->self) { + ret =3D pbus_reassign_bridge_resources(dev->bus, res); + if (ret) + goto error_resize; + } + return 0; + +error_resize: + pci_rebar_set_size(dev, resno, old); + pci_resize_resource_set_size(dev, resno, old); + return ret; +} +EXPORT_SYMBOL(pci_resize_resource); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c3ba4ccecd43..e5fcadfc58b0 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -431,84 +431,6 @@ int pci_release_resource(struct pci_dev *dev, int resn= o) } EXPORT_SYMBOL(pci_release_resource); =20 -static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, - int resno) -{ - u16 cmd; - - if (pci_resource_is_iov(resno)) - return pci_iov_is_memory_decoding_enabled(dev); - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - - return cmd & PCI_COMMAND_MEMORY; -} - -static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, - int size) -{ - resource_size_t res_size =3D pci_rebar_size_to_bytes(size); - struct resource *res =3D pci_resource_n(dev, resno); - - if (!pci_resource_is_iov(resno)) { - resource_set_size(res, res_size); - } else { - resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); - pci_iov_resource_set_size(dev, resno, res_size); - } -} - -int pci_resize_resource(struct pci_dev *dev, int resno, int size) -{ - struct resource *res =3D pci_resource_n(dev, resno); - struct pci_host_bridge *host; - int old, ret; - u32 sizes; - - /* Check if we must preserve the firmware's resource assignment */ - host =3D pci_find_host_bridge(dev->bus); - if (host->preserve_config) - return -ENOTSUPP; - - /* Make sure the resource isn't assigned before resizing it. */ - if (!(res->flags & IORESOURCE_UNSET)) - return -EBUSY; - - if (pci_resize_is_memory_decoding_enabled(dev, resno)) - return -EBUSY; - - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) - return -EINVAL; - - old =3D pci_rebar_get_current_size(dev, resno); - if (old < 0) - return old; - - ret =3D pci_rebar_set_size(dev, resno, size); - if (ret) - return ret; - - pci_resize_resource_set_size(dev, resno, size); - - /* Check if the new config works by trying to assign everything. */ - if (dev->bus->self) { - ret =3D pbus_reassign_bridge_resources(dev->bus, res); - if (ret) - goto error_resize; - } - return 0; - -error_resize: - pci_rebar_set_size(dev, resno, old); - pci_resize_resource_set_size(dev, resno, old); - return ret; -} -EXPORT_SYMBOL(pci_resize_resource); - int pci_enable_resources(struct pci_dev *dev, int mask) { u16 cmd, old_cmd; --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5D2B34844E; Wed, 22 Oct 2025 13:34:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; 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a="63190399" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63190399" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:34:13 -0700 X-CSE-ConnectionGUID: uPn5dYWYTCeb9BTPiqzFNA== X-CSE-MsgGUID: RZoJpDH8TLKqnY+DttFJJQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="189001328" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:34:04 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 02/11] PCI: Cleanup pci_rebar_bytes_to_size() and move into rebar.c Date: Wed, 22 Oct 2025 16:33:22 +0300 Message-Id: <20251022133331.4357-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move pci_rebar_bytes_to_size() from include/linux/pci.h into rebar.c as it does not look very trivial and is not expected to be performance critical. Convert literals to use a newly added PCI_REBAR_MIN_SIZE define. Also add kernel doc for the function as the function is exported. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig Reviewed-by: Michael J. Ruhl --- drivers/pci/rebar.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 10 +++------- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 8deee5bb33fa..342b47022a5a 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -7,11 +7,34 @@ #include #include #include +#include #include +#include #include =20 #include "pci.h" =20 +#define PCI_REBAR_MIN_SIZE ((resource_size_t)SZ_1M) + +/** + * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size + * @bytes: size in bytes + * + * Convert bytes to BAR Size in Resizable BAR Capability (PCIe r6.2, + * sec. 7.8.6.3). + * + * Return: BAR Size as defined in the PCIe spec (0=3D1MB, 31=3D128TB). + */ +int pci_rebar_bytes_to_size(u64 bytes) +{ + int rebar_minsize =3D ilog2(PCI_REBAR_MIN_SIZE); + + bytes =3D roundup_pow_of_two(bytes); + + return max(ilog2(bytes), rebar_minsize) - rebar_minsize; +} +EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index d1fdf81fbe1e..540221d0df0b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1419,16 +1419,12 @@ void pcibios_reset_secondary_bus(struct pci_dev *de= v); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int pci_release_resource(struct pci_dev *dev, int resno); -static inline int pci_rebar_bytes_to_size(u64 bytes) -{ - bytes =3D roundup_pow_of_two(bytes); - - /* Return BAR size as defined in the resizable BAR specification */ - return max(ilog2(bytes), 20) - 20; -} =20 +/* Resizable BAR related routines */ +int pci_rebar_bytes_to_size(u64 bytes); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); + int pci_select_bars(struct pci_dev *dev, unsigned long flags); bool pci_device_is_present(struct pci_dev *pdev); void pci_ignore_hotplug(struct pci_dev *dev); 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 03/11] PCI: Move pci_rebar_size_to_bytes() and export it Date: Wed, 22 Oct 2025 16:33:23 +0300 Message-Id: <20251022133331.4357-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_rebar_size_to_bytes() is in drivers/pci/pci.h but would be useful for endpoint drivers as well. Move the function into rebar.c and export it. In addition, convert the literal to where the number comes from (PCI_REBAR_MIN_SIZE). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/pci.h | 4 ---- drivers/pci/rebar.c | 12 ++++++++++++ include/linux/pci.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index fffd0a0cc803..939a3a84b06e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1023,10 +1023,6 @@ void pci_rebar_init(struct pci_dev *pdev); void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); -static inline u64 pci_rebar_size_to_bytes(int size) -{ - return 1ULL << (size + 20); -} =20 struct device_node; =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 342b47022a5a..1d30dbb7fe82 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -35,6 +35,18 @@ int pci_rebar_bytes_to_size(u64 bytes) } EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); =20 +/** + * pci_rebar_size_to_bytes - Convert BAR Size to bytes + * @size: BAR Size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) + * + * Return: BAR size in bytes. + */ +resource_size_t pci_rebar_size_to_bytes(int size) +{ + return 1ULL << (size + ilog2(PCI_REBAR_MIN_SIZE)); +} +EXPORT_SYMBOL_GPL(pci_rebar_size_to_bytes); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index 540221d0df0b..0a50912c5ce5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1422,6 +1422,7 @@ int pci_release_resource(struct pci_dev *dev, int res= no); =20 /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); +resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); =20 --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E61B7347FF6; Wed, 22 Oct 2025 13:34:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 04/11] PCI: Improve Resizable BAR functions kernel doc Date: Wed, 22 Oct 2025 16:33:24 +0300 Message-Id: <20251022133331.4357-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix the copy-pasted errors in the Resizable BAR handling functions kernel doc and generally improve wording choices. Fix the formatting errors of the Return: line. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/rebar.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 1d30dbb7fe82..17e7b664c4ce 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -53,13 +53,15 @@ void pci_rebar_init(struct pci_dev *pdev) } =20 /** - * pci_rebar_find_pos - find position of resize ctrl reg for BAR + * pci_rebar_find_pos - find position of resize control reg for BAR * @pdev: PCI device * @bar: BAR to find * - * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. + * Helper to find the position of the control register for a BAR. + * + * Return: + * * %-ENOTSUPP if resizable BARs are not supported at all, + * * %-ENOENT if no control register for the BAR could be found. */ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) { @@ -92,12 +94,14 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) } =20 /** - * pci_rebar_get_possible_sizes - get possible sizes for BAR + * pci_rebar_get_possible_sizes - get possible sizes for Resizable BAR * @pdev: PCI device * @bar: BAR to query * - * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + * Get the possible sizes of a resizable BAR as bitmask. + * + * Return: A bitmask of possible sizes (bit 0=3D1MB, bit 31=3D128TB), or %= 0 if + * BAR isn't resizable. */ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { @@ -121,12 +125,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev= , int bar) EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 /** - * pci_rebar_get_current_size - get the current size of a BAR + * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device - * @bar: BAR to set size to + * @bar: BAR to get the size from * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. + * Reads the current size of a BAR from the Resizable BAR config. + * + * Return: BAR Size if @bar is resizable (0=3D1MB, 31=3D128TB), or negativ= e on + * error. */ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) { @@ -142,13 +148,14 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, = int bar) } =20 /** - * pci_rebar_set_size - set a new size for a BAR + * pci_rebar_set_size - set a new size for a Resizable BAR * @pdev: PCI device * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * @size: new size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) * * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. + * + * Return: %0 if resizing was successful, or negative on error. */ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) { --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E4A9347BD8; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 05/11] PCI: Add pci_rebar_size_supported() helper Date: Wed, 22 Oct 2025 16:33:25 +0300 Message-Id: <20251022133331.4357-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Many callers of pci_rebar_get_possible_sizes() are interested in finding out if a particular BAR Size (PCIe r6.2 sec. 7.8.6.3) is supported by the particular BAR. Add pci_rebar_size_supported() into PCI core to make it easy for the drivers to determine if the BAR Size is supported or not. Use the new function in pci_resize_resource() and in pci_iov_vf_bar_set_size(). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig Reviewed-by: Andi Shyti --- drivers/pci/iov.c | 7 +------ drivers/pci/rebar.c | 25 +++++++++++++++++++------ include/linux/pci.h | 1 + 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 77dee43b7858..02f4e9cd3fbe 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1339,7 +1339,6 @@ EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); */ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) { - u32 sizes; int ret; =20 if (!pci_resource_is_iov(resno)) @@ -1348,11 +1347,7 @@ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int= resno, int size) if (pci_iov_is_memory_decoding_enabled(dev)) return -EBUSY; =20 - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) + if (!pci_rebar_size_supported(dev, resno, size)) return -EINVAL; =20 ret =3D pci_rebar_set_size(dev, resno, size); diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 17e7b664c4ce..067cd75b394b 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -3,6 +3,7 @@ * PCI Resizable BAR Extended Capability handling. */ =20 +#include #include #include #include @@ -124,6 +125,23 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev,= int bar) } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 +/** + * pci_rebar_size_supported - check if size is supported for BAR + * @pdev: PCI device + * @bar: BAR to check + * @size: size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) + * + * Return: %true if @bar is resizable and @size is a supported, otherwise + * %false. + */ +bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size) +{ + u64 sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + + return BIT(size) & sizes; +} +EXPORT_SYMBOL_GPL(pci_rebar_size_supported); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device @@ -231,7 +249,6 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) struct resource *res =3D pci_resource_n(dev, resno); struct pci_host_bridge *host; int old, ret; - u32 sizes; =20 /* Check if we must preserve the firmware's resource assignment */ host =3D pci_find_host_bridge(dev->bus); @@ -245,11 +262,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno= , int size) if (pci_resize_is_memory_decoding_enabled(dev, resno)) return -EBUSY; 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Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Jani Nikula Subject: [PATCH v3 06/11] drm/i915/gt: Use pci_rebar_size_supported() Date: Wed, 22 Oct 2025 16:33:26 +0300 Message-Id: <20251022133331.4357-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported() that helps in checking if a BAR Size is supported for the BAR or not. Use it in i915_resize_lmem_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Jani Nikula Reviewed-by: Andi Shyti Acked-by: Christian K=C3=B6nig Acked-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/= i915/gt/intel_region_lmem.c index 51bb27e10a4f..69c65fc8a72d 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -61,16 +61,12 @@ static void i915_resize_lmem_bar(struct drm_i915_privat= e *i915, resource_size_t current_size =3D roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR= )); =20 if (i915->params.lmem_bar_size) { - u32 bar_sizes; - - rebar_size =3D i915->params.lmem_bar_size * - (resource_size_t)SZ_1M; - bar_sizes =3D pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR); - + rebar_size =3D i915->params.lmem_bar_size * (resource_size_t)SZ_1M; if (rebar_size =3D=3D current_size) return; =20 - if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) || + if (!pci_rebar_size_supported(pdev, GEN12_LMEM_BAR, + pci_rebar_bytes_to_size(rebar_size)) || rebar_size >=3D roundup_pow_of_two(lmem_size)) { rebar_size =3D lmem_size; =20 --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B98C1348864; Wed, 22 Oct 2025 13:35:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140120; cv=none; b=rmp8rB8/A9YbEUSwFfkB1t4sKLWTLISQW6bXdxxmy64nPXY5c78UzNcP9KeRVtKQoX8uRdGMaYB60LZUgcYEuTDECnjAifeDEYp+5RX2lXk3cs55sMWjSMKhoGBL5+0dbkvfuknWbMrm67jmlfRxRz+246L2yx5fDGeYqZ/2iRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140120; c=relaxed/simple; bh=rvq8S7Tm5qcOrmVwTnQP2K04nFjvwe8824uK1q80uXo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=VvPanpwDruXIWOKxcl79fmD4PbQDq7n/KciKt88b5AyyBffae7PaPYYSYENPy1XxgZkwucPfC6hxDOM4eWf9D2YJ23bZj1pDsNhQpJ6uuq19feJBOFw3ItUt5psa7vl3dREMnXmBj3fHxLO/fadS0LnxTjl8g9gUTWZtlFaP5sY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Mu8b0Dzy; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Mu8b0Dzy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761140119; x=1792676119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rvq8S7Tm5qcOrmVwTnQP2K04nFjvwe8824uK1q80uXo=; b=Mu8b0Dzysl5vGljtkEafvgj4ki2VbidHz//oIMktjdm4Bt6zmV0akyy4 fGsPQENOVoNVmWkPO1a/Drm4GeElUF2XS/5nMD5PwTEufGNka6BX/oZ17 ibSy9BKbhKgRjtYy/ZLU7oLShgWsoRecdJ3gNM0AOZMrH6gHI2lMGL0Jk 2AC8uYiM1Jh1pnvD0p91xQp3Tw1P5P53XkrNE9SD48oxo6aPpc58W2WBS G2Mo/I6FmzT7UNW+a9/aKROs6bRyTKABkov9NFPBGVfHSPfLKaWboxGbH iFJeUQTVdl/U/ug5sIU+2sBfKxVFj7IU99zIha1jgNf2/dAZHBGlP/UGs A==; X-CSE-ConnectionGUID: RtDlo1QlTrimM8T3aGW/Fw== X-CSE-MsgGUID: Fve/zid6Q7OPNtgfmwvlOA== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63325338" X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="63325338" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:18 -0700 X-CSE-ConnectionGUID: RPKSY7fORVOxMOWhTAvOgA== X-CSE-MsgGUID: ZvV9E3lTTNCHcTSI6lf9VQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="184275109" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:10 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 07/11] drm/xe/vram: Use PCI rebar helpers in resize_vram_bar() Date: Wed, 22 Oct 2025 16:33:27 +0300 Message-Id: <20251022133331.4357-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported() and pci_rebar_size_to_bytes(), use them in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Christian K=C3=B6nig Acked-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_vram.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index b44ebf50fedb..9ac053bb0b2e 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -24,8 +24,6 @@ #include "xe_vram.h" #include "xe_vram_types.h" =20 -#define BAR_SIZE_SHIFT 20 - static void _resize_bar(struct xe_device *xe, int resno, resource_size_t size) { @@ -74,25 +72,22 @@ static void resize_vram_bar(struct xe_device *xe) =20 /* set to a specific size? */ if (force_vram_bar_size) { - u32 bar_size_bit; - - rebar_size =3D force_vram_bar_size * (resource_size_t)SZ_1M; + rebar_size =3D pci_rebar_bytes_to_size(force_vram_bar_size * + (resource_size_t)SZ_1M); =20 - bar_size_bit =3D bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)= ); - - if (!bar_size_bit) { + if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", - (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); + (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, + bar_size_mask, (u64)current_size >> 20); return; } =20 - rebar_size =3D 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); - + rebar_size =3D pci_rebar_size_to_bytes(rebar_size); if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); + rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07B3A3491D9; Wed, 22 Oct 2025 13:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140132; cv=none; b=ozLt0glETU10E/G5jdL5k/t6Y2WwUwAIDcLq/dVQcoKQaZlN1jwPdPcIbNcbr1GYew9orJi1FcoWkE3B4hpWYP88t3ipjPFAjKDgI8A81QZWPtSjhnfw3cWtyS45LzTk6eG1Ft2EE055atEExJSev3qBQb5a0DBvRJN4XZvHQlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140132; c=relaxed/simple; bh=54u3PDRaemdPochxtkYh61DrCq3MZ1of0SKbBIseOrk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=V4gLaZ5xyc9xcvneDW1gNblKkTT+W2ESZ138bIIZrr9LpdlDZ1UgS3LU2rykh/2K9IGEWEnxEDDZU+dk88AoOdZuAz/ib2JEPn4v7dH+QR0KVLca1H/2gj7aselZHY1p0CwFWklwJAx/d1xnl2DjPo5MOtpR2ZP3ENKC1YL3pjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nNDavfcV; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nNDavfcV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761140131; x=1792676131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=54u3PDRaemdPochxtkYh61DrCq3MZ1of0SKbBIseOrk=; b=nNDavfcVMSXcPb4qoUAlHJ37m9H3To0HRSvoTKGdKv8cEe/GiJAnhhGX 1Kt81EpzcbOsrLb0nPNeo6S3+wiYEBNNWBbtLbwq7QeLiUvrx/kDXOuCo mlTDgcN3+SGsF1efVPxaUDF+axCh0yXKP3eT43uMq67ziTefM0k8yuEHP qtJ0U211tCAylK41GIrZHMlzTKtfeLf2yRKOW0Pir1wrJg2KofoYokE+K g23VUBs2va1oJCglNTlz89yyEI7uS0OirHt5jZfbWao+Q9HzYlX3w4DPu r/sJ0VXdlgLE3VZZSyOo+xzLMafFt9LJgxTRm/DTn1KmPqC7zEKAEgYy0 Q==; X-CSE-ConnectionGUID: G0D/Um0ISyOMto/H6NvZ4A== X-CSE-MsgGUID: 3NtVJbRETmao+h0U1tO0dg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63325352" X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="63325352" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:30 -0700 X-CSE-ConnectionGUID: Z1bNbHoxR7iEueWz+MvvEw== X-CSE-MsgGUID: LEJOV63XQySmg6mVyJyRBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="183580120" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:23 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 08/11] PCI: Add pci_rebar_get_max_size() Date: Wed, 22 Oct 2025 16:33:28 +0300 Message-Id: <20251022133331.4357-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add pci_rebar_get_max_size() into PCI core to allow simplifying code that wants to know the maximum possible size for a Resizable BAR. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/pci/rebar.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 067cd75b394b..1c30beb80f85 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -142,6 +143,28 @@ bool pci_rebar_size_supported(struct pci_dev *pdev, in= t bar, int size) } EXPORT_SYMBOL_GPL(pci_rebar_size_supported); =20 +/** + * pci_rebar_get_max_size - get the maximum supported size of a BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the largest supported size of a resizable BAR as a size. + * + * Returns: the maximum BAR size as defined in the PCIe spec (0=3D1MB, 31= =3D128TB), + * or %-NOENT on error. + */ +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) +{ + u32 sizes; + + sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + if (!sizes) + return -ENOENT; + + return __fls(sizes); +} +EXPORT_SYMBOL_GPL(pci_rebar_get_max_size); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device diff --git a/include/linux/pci.h b/include/linux/pci.h index cf833daddaee..61dcf5ff7df6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1425,6 +1425,7 @@ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); =20 int pci_select_bars(struct pci_dev *dev, unsigned long flags); --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6370B347BB5; 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Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 09/11] drm/xe/vram: Use pci_rebar_get_max_size() Date: Wed, 22 Oct 2025 16:33:29 +0300 Message-Id: <20251022133331.4357-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() from PCI core in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen Acked-by: Christian K=C3=B6nig Acked-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_vram.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 9ac053bb0b2e..55232dfe2cd8 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -56,16 +56,11 @@ static void resize_vram_bar(struct xe_device *xe) resource_size_t current_size; resource_size_t rebar_size; struct resource *root_res; - u32 bar_size_mask; + int max_size, i; u32 pci_cmd; - int i; =20 /* gather some relevant info */ current_size =3D pci_resource_len(pdev, LMEM_BAR); - bar_size_mask =3D pci_rebar_get_possible_sizes(pdev, LMEM_BAR); - - if (!bar_size_mask) - return; =20 if (force_vram_bar_size < 0) return; @@ -79,7 +74,8 @@ static void resize_vram_bar(struct xe_device *xe) drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, - bar_size_mask, (u64)current_size >> 20); + pci_rebar_get_possible_sizes(pdev, LMEM_BAR), + (u64)current_size >> 20); return; } =20 @@ -87,7 +83,10 @@ static void resize_vram_bar(struct xe_device *xe) if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); + max_size =3D pci_rebar_get_max_size(pdev, LMEM_BAR); + if (max_size < 0) + return; + rebar_size =3D pci_rebar_size_to_bytes(max_size); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77214347FF6; Wed, 22 Oct 2025 13:35:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140159; cv=none; b=LrBJhNK3qiz4DperQjbSqlxpF9Iio4JkMRX0IkFY63N6r2kM2GXux/iSef/HavB/tBNQ98wzhVfvDZ+ZwU/xzitqbaMZgx43za/3icPxHo832XTUCxHa2I8/J5KaV4Zz5pwx4jpadhoAOw4JNyQ0R4Vxb4Zg63TX3mkXp72HykQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140159; c=relaxed/simple; bh=EmpF6b0WmnNp0mwUO4CDpZ5esZ0cLfkjpTyG6Yghz5o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=U3BsSOGfMrWYdo9c2EzL4Ub1skOfT7Ubk9VHclwcLHIwzwcAHrgjgHRNWmzD5n6ZYHb4Z082lHSQ6v7Vp9WATAeVxILA4RxsesCx7rIy2tpvxRdTBuQwgL9fFDkPdt/tET7Dp7Q4wwrS0EC0WNWhAgg5y8d9psVatQdCG/Vl4Zs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FUWTVaXH; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FUWTVaXH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761140157; x=1792676157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EmpF6b0WmnNp0mwUO4CDpZ5esZ0cLfkjpTyG6Yghz5o=; b=FUWTVaXHHm9anLu9TCyDYWmxePWnhrhJRe1gIXoymgtoTgiqsdEwfpeL H3xLWDKRG8zzF/3LZhqNFVO7QlEUXitGGEq361eCIboSA7YsAdLwmvCqL XgNLJS/+b8b+erWgRIkH4e813XkqTPK7O5yAhMdYFf1Buxn1a4LSchhF6 iMg9FT3cD5O9abyBOuD4jro0AyizhWra9YV2UdBa2dKC2AXAkRSX6V023 f47Qcz5e4LbpsgARv/PKMVsLuunv0zbYABmS4iAaeoBsUe1yWYhIWFL5J vmStoNN1F1ec5itsTdZwJeCIvV6/BslBSfbMdbsZ5A+lbpfykQqqSpRCw A==; X-CSE-ConnectionGUID: Mgncv70GTxKtrgTA9C/Y1Q== X-CSE-MsgGUID: cfIFpMgvS4WnMWJ4PwRakw== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="67152658" X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="67152658" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:56 -0700 X-CSE-ConnectionGUID: 01BFCYMtRpeNxnwdyj8gHg== X-CSE-MsgGUID: Um+07uRyRZmfKkxVOh4lDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="188281691" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:35:49 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 10/11] drm/amdgpu: Use pci_rebar_get_max_size() Date: Wed, 22 Oct 2025 16:33:30 +0300 Message-Id: <20251022133331.4357-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() from PCI core to simplify code in amdgpu_device_resize_fb_bar(). Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index a77000c2e0bb..f2c4f6996c23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1673,9 +1673,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device = *adev) int rbar_size =3D pci_rebar_bytes_to_size(adev->gmc.real_vram_size); struct pci_bus *root; struct resource *res; + int max_size, r; unsigned int i; u16 cmd; - int r; =20 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; @@ -1721,8 +1721,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device= *adev) return 0; =20 /* Limit the BAR size to what is available */ - rbar_size =3D min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, - rbar_size); + max_size =3D pci_rebar_get_max_size(adev->pdev, 0); + if (max_size < 0) + return 0; + rbar_size =3D min(max_size, rbar_size); =20 /* Disable memory decoding while we change the BAR addresses and size */ pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); --=20 2.39.5 From nobody Sat Feb 7 05:01:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCB21347FCD; Wed, 22 Oct 2025 13:36:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140172; cv=none; b=hmrfX0M8PYKUZRt1s7VEiEZjAn++gB6bHaL/ynzV/HL/p8oSnUGZq1Lns83WrGvltiE77mBkcKiDQ1IdDyv6pe4hz9ECsezJihuJshUDbR+4LX1ZNFVMLqlPp8qpl2LJylFqp+vjQ29EvbsVIjrc+7IZTq+uZlfeP1Pxd+E5ZEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761140172; c=relaxed/simple; bh=vgdrsWGvy0swoIbcD1t6cJesDB5Ul+gmQHIizIpLf3U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=CxmgwyFDDKpgEme+XuH+x9ElqzE2cqZnxb/VH37wLHTceuMSw0WZGBOM/5wddrteNWCRF2zCvbCahUjjcLKMj6WEPZJTO3jzThyp8CorT5gK7Q/PZmV8HCi7XJgaUDn0SR19OIAeVfQTqx1i4D8REBRNgT7xIaJQKvv9NFl9jVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MXsQxwWa; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MXsQxwWa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761140171; x=1792676171; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vgdrsWGvy0swoIbcD1t6cJesDB5Ul+gmQHIizIpLf3U=; b=MXsQxwWa1UA3s8IygxddKIsnxuzUEUzoNX+rhwAAy9M08bl/ZcmMRJY4 +m0p4bZNGRLekfHCVnX02QUVYsL1JohosJmARWN0JwQlhh5yDzpB+oRX2 PgcFK7usDp9Jj7Eu/9jOxjHDTw4B9OFURqgpnvR/sVo58KdrKZYFIypqV yPLPHviz+/5mgMqv06/+EuqWYY+MvGlMe3mjjq3uKk3HgBmBSRPpm0B/t wRp/+YfxmHOijZsEiOi1WkHYOPvo60EAFNUIrZZH7aMOX3vl6lCN6QRq1 l/6QLogMpszY1vzEIoX9X8UgkoDznSSuIY7MC69e4pXA9K+xQjlWH37qJ A==; X-CSE-ConnectionGUID: d4AD3028TfaTTM3nlKfJhw== X-CSE-MsgGUID: PMXtevUgQfqSGqqIaDB6eg== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="62317507" X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="62317507" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:36:10 -0700 X-CSE-ConnectionGUID: 93A0HGFKS5SF/61i/IYhjw== X-CSE-MsgGUID: hqWZieMqT7S1LMIUGJ5wuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,247,1754982000"; d="scan'208";a="189152907" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.82]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 06:36:02 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , "Michael J . Ruhl" , Andi Shyti , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH v3 11/11] PCI: Convert BAR sizes bitmasks to u64 Date: Wed, 22 Oct 2025 16:33:31 +0300 Message-Id: <20251022133331.4357-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> References: <20251022133331.4357-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCIe r6.2 section 7.8.6 defines resizable BAR sizes beyond the currently supported maximum of 128TB which will require more than u32 to store the entire bitmask. Convert Resizable BAR related functions to use u64 bitmask for BAR sizes to make the typing more future-proof. The support for the larger BAR sizes themselves is not added at this point. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Christian K=C3=B6nig --- drivers/gpu/drm/xe/xe_vram.c | 2 +- drivers/pci/iov.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/rebar.c | 4 ++-- include/linux/pci.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 55232dfe2cd8..f18232668810 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -72,7 +72,7 @@ static void resize_vram_bar(struct xe_device *xe) =20 if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, - "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", + "Requested size: %lluMiB is not supported by rebar sizes: 0x%llx. Lea= ving default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, pci_rebar_get_possible_sizes(pdev, LMEM_BAR), (u64)current_size >> 20); diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 02f4e9cd3fbe..c09f7caa49a4 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1375,7 +1375,7 @@ EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) { u64 vf_len =3D pci_resource_len(dev, resno); - u32 sizes; + u64 sizes; =20 if (!num_vfs) return 0; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index af74cf02bb90..cb19983182b5 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1586,7 +1586,7 @@ static ssize_t __resource_resize_show(struct device *= dev, int n, char *buf) pci_config_pm_runtime_get(pdev); =20 ret =3D sysfs_emit(buf, "%016llx\n", - (u64)pci_rebar_get_possible_sizes(pdev, n)); + pci_rebar_get_possible_sizes(pdev, n)); =20 pci_config_pm_runtime_put(pdev); =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 1c30beb80f85..1488769071ed 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -105,7 +105,7 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) * Return: A bitmask of possible sizes (bit 0=3D1MB, bit 31=3D128TB), or %= 0 if * BAR isn't resizable. */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { int pos; u32 cap; @@ -155,7 +155,7 @@ EXPORT_SYMBOL_GPL(pci_rebar_size_supported); */ int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) { - u32 sizes; + u64 sizes; =20 sizes =3D pci_rebar_get_possible_sizes(pdev, bar); if (!sizes) diff --git a/include/linux/pci.h b/include/linux/pci.h index 61dcf5ff7df6..63d98b2a3e06 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1423,7 +1423,7 @@ int pci_release_resource(struct pci_dev *dev, int res= no); /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); --=20 2.39.5