From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4D512F39DA; Wed, 22 Oct 2025 07:05:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116749; cv=none; b=ioIMe4E2BRr9Yu6s7gt84nOY2Ax3rKm5CNY8ptwa9O/PNo3mu5fEVhyhq+V9UirET6WV6K3m8hJRSZlD7aamVuM/8lYZfU1el5eIYxwg9EK/MoaR/XKJo+pjb+8s3ThxAHR7MVd0AMWscKbhTWLyG2UEs4032OQyT67aGxOFnCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116749; c=relaxed/simple; bh=Obpd//VpUN2twV+EMu4LchAWePJkY0WgL7SJD42yqv8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LhLJZjtzmU4QNC2P9SKTz5YqT5qaRmwzpzRXE9cyyby3krZsgchmBtO0cLAM37W0e+M2ESYc47Z3k3SM3WCZzos+kqshIAed4jf04Kq15L3TcNSbB0k6n73U4pHlkyqg6V/vI9FAHxweXXvLHf9VCFHB0viRGt9KeRwyazx6vJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 15:05:43 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 15:05:43 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , CC: Conor Dooley Subject: [PATCH v6 1/6] dt-bindings: arm: aspeed: Add AST2700 board compatible Date: Wed, 22 Oct 2025 15:05:38 +0800 Message-ID: <20251022070543.1169173-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree compatible string for AST2700 based boards ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC board bindings. This allows proper schema validation and enables support for AST2700 platforms. Signed-off-by: Ryan Chen Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..1c1a12fc3a91 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -109,4 +109,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 =20 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true --=20 2.34.1 From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4ADA2F4A16; Wed, 22 Oct 2025 07:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116751; cv=none; b=APtgvJUU9vO08pe1EjzfFM47gtHrjmQuqc2mxUFnJodtKDjstzo7kX0aDRrGo/mT5+aKot08h2EdfET/C/opGJ20d5IyROurFu1E1HlqjiW/ADCVIEF4yib+TAmsU5OnuMZd/TouZEr5ZNJxqDWiYLhWc/LwQTxU+BK2aNIszPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116751; c=relaxed/simple; bh=p+pnkItFDIXvUygT0L+saT3mcdwqFMt1rS497ed4+jI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QviHWzV2gEXZZW2K7eQIAjx08QsZzXiEIT89qLTUNqY4VD0tt4OceQ0ffyktV4jfwDUFE3Fq7nbSpVCvCRtH0iyfX6mEL5vRmUCt0YTsDdWim8YYNniz2yaqi9OEe8uWyVuzAIlO3Xq1FN/LOXFh/Zzo6JKUUUxTOLPIQivh5o8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 15:05:44 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 15:05:44 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v6 2/6] arm64: Kconfig: Add Aspeed SoC family (ast27XX) Kconfig support Date: Wed, 22 Oct 2025 15:05:39 +0800 Message-ID: <20251022070543.1169173-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Aspeed ast27XX 8th generation Aspeed BMCs. Signed-off-by: Ryan Chen --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 13173795c43d..d2746107ceca 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -47,6 +47,12 @@ config ARCH_ARTPEC help This enables support for the ARMv8 based ARTPEC SoC Family. =20 +config ARCH_ASPEED + bool "Aspeed SoC family" + help + Say yes if you intend to run on an Aspeed ast27XX 8th generation + Aspeed BMCs. + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB --=20 2.34.1 From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E8A72F49FF; Wed, 22 Oct 2025 07:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116753; cv=none; b=pLhOod8raDBLpSt+dPDj5h6kq8Cz6G+MGiyS9Zc31RyHMGaMu8W2vVbrMyo6hyZkPOnbrAPZc1EzLMp68ml9VImkzqikZ754sCEHU5pXZI/MtyuXhPICICCIUbb3cVWRyomWSFWRfWvIJLukOJD/bk+t2OAgYTceSc20l8rJeks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116753; c=relaxed/simple; bh=rs4FERLiI6+KC3XRnYw0xK9slbOeK8k0qeO0Ht3DTog=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IGVc32c1AospuDpRhrOlh1GMCIXOEV3j8ywUiHXr+5xiP4MFRk1PxdCgUAebHPwZVQs2VmIlI1g5fL46kmyT9MfgJa2hZLWbmubwLaILQPY/ZZKjaTgyamaFdvK4cx55q9CnNOaSeXAzlsMJbaniE3f4S4Gh2LYS5BDu5UZrf60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 15:05:44 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 15:05:44 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v6 3/6] dt-bindings: mfd: aspeed,ast2x00-scu: allow #size-cells range Date: Wed, 22 Oct 2025 15:05:40 +0800 Message-ID: <20251022070543.1169173-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The #size-cells property in the Aspeed SCU binding is currently fixed to a constant value of 1. However, newer SoCs (ex. AST2700) may require two size cells to describe certain subregions or subdevices. This patch updates the schema to allow #size-cells values in the range of 1 to 2. This makes the binding more flexible while maintaining compatibility with existing platforms. It also resolves dt-binding validation warnings reported by `make dt_binding_check`. Signed-off-by: Ryan Chen --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml = b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index da1887d7a8fe..ee7855845e97 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -38,7 +38,7 @@ properties: maximum: 2 =20 '#size-cells': - const: 1 + enum: [1, 2] =20 '#clock-cells': const: 1 --=20 2.34.1 From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C7F12F5A3F; Wed, 22 Oct 2025 07:05:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116756; cv=none; b=qohrvdURFj/uX/Huh/ehQ7EGHKUnI1ASgSgCpKB66EgCUk0g1GLaeoxgBi/tmIDz4Wjago1tDm2deZe3FCRfCTGFjgMyp0xqhJpahi0dASv3dHxBZazNv2cj9pQCH59c3FGUsbZChIo4v7DoNaJUtoZvOBYau6fRDRYKqKmt/8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116756; c=relaxed/simple; bh=AUAsIfcVrxEwRZrx2jeBinK2+N38/x+qU2mLV27m7M0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hatfdiwqPOXTH8Anqo2sOIxqNXulaMUAnpXqqffPZFl38pW5PoHM1VVxIT/8LNKADE8coRp2UZKIDJgQrRLVCl71cBGJMktYFNte1iIk/iC4+JsUUKsaP6xi+LNHXxlSh/IH7uNAS7qn+NLHfmEwarSefF+6912aKDPIHYBWPFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 15:05:44 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 15:05:44 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree Date: Wed, 22 Oct 2025 15:05:41 +0800 Message-ID: <20251022070543.1169173-5-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree for the ASPEED 8th BMC SoC family. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 516 ++++++++++++++++++++++ 1 file changed, 516 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dt= s/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..be6ca2739958 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include + +/ { + compatible =3D "aspeed,ast2700"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + serial6 =3D &uart6; + serial7 =3D &uart7; + serial8 =3D &uart8; + serial9 =3D &uart9; + serial10 =3D &uart10; + serial11 =3D &uart11; + serial12 =3D &uart12; + serial13 =3D &uart13; + serial14 =3D &uart14; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + }; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg =3D <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg =3D <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + arm-pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + }; + + soc0: soc@10000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x10000000 0x0 0x4000000>; + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0 0x12100000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x12100000 0x4000>; + + intc0_11: interrupt-controller@1b00 { + #interrupt-cells =3D <1>; + interrupt-controller; + compatible =3D "aspeed,ast2700-intc0-ic"; + reg =3D <0x1b00 0x10>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + }; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x12c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg =3D <0x0 0x4>; + }; + + scu_ic0: interrupt-controller@1d0 { + compatible =3D "aspeed,ast2700-scu-ic0"; + reg =3D <0x1d0 0xc>; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@1e0 { + compatible =3D "aspeed,ast2700-scu-ic1"; + reg =3D <0x1e0 0xc>; + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-controller; + }; + }; + + gpio0: gpio@12c11000 { + #gpio-cells =3D <2>; + gpio-controller; + compatible =3D "aspeed,ast2700-gpio"; + reg =3D <0x0 0x12c11000 0x0 0x1000>; + interrupts =3D ; + ngpios =3D <12>; + clocks =3D <&syscon0 SCU0_CLK_APB>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + uart4: serial@12c1a000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x12c1a000 0x0 0x1000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts =3D ; + no-loopback-test; + status =3D "disabled"; + }; + }; + + soc1: soc@14000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x14000000 0x0 0x10000000>; + + mdio0: mdio@14040000 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040000 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + mdio1: mdio@14040008 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040008 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + mdio2: mdio@14040010 { + compatible =3D "aspeed,ast2600-mdio"; + reg =3D <0 0x14040010 0 0x8>; + resets =3D <&syscon1 SCU1_RESET_MII>; + status =3D "disabled"; + }; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg =3D <0x0 0x14c02000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x14c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + scu_ic2: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-scu-ic2"; + reg =3D <0x100 0x8>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc1_5 0>; + interrupt-controller; + }; + + scu_ic3: interrupt-controller@108 { + compatible =3D "aspeed,ast2700-scu-ic3"; + reg =3D <0x108 0x8>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc1_5 26>; + interrupt-controller; + }; + + }; + + gpio1: gpio@14c0b000 { + #gpio-cells =3D <2>; + gpio-controller; + compatible =3D "aspeed,ast2700-gpio"; + reg =3D <0x0 0x14c0b000 0x0 0x1000>; + interrupts-extended =3D <&intc1_2 18>; + ngpios =3D <216>; + clocks =3D <&syscon1 SCU1_CLK_AHB>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0 0x14c18000 0 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x14c18000 0x400>; + + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0>; + }; + + intc1_1: interrupt-controller@110 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x110 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1>; + }; + + intc1_2: interrupt-controller@120 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x120 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 2>; + }; + + intc1_3: interrupt-controller@130 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x130 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 3>; + }; + + intc1_4: interrupt-controller@140 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x140 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 4>; + }; + + intc1_5: interrupt-controller@150 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x150 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 5>; + }; + }; + + uart0: serial@14c33000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART0CLK>; + interrupts-extended =3D <&intc1_4 7>; + no-loopback-test; + status =3D "disabled"; + }; + + uart1: serial@14c33100 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART1CLK>; + interrupts-extended =3D <&intc1_4 8>; + no-loopback-test; + status =3D "disabled"; + }; + + uart2: serial@14c33200 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART2CLK>; + interrupts-extended =3D <&intc1_4 9>; + no-loopback-test; + status =3D "disabled"; + }; + + uart3: serial@14c33300 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART3CLK>; + interrupts-extended =3D <&intc1_4 10>; + no-loopback-test; + status =3D "disabled"; + }; + + uart5: serial@14c33400 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART5CLK>; + interrupts-extended =3D <&intc1_4 11>; + no-loopback-test; + status =3D "disabled"; + }; + + uart6: serial@14c33500 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART6CLK>; + interrupts-extended =3D <&intc1_4 12>; + no-loopback-test; + status =3D "disabled"; + }; + + uart7: serial@14c33600 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART7CLK>; + interrupts-extended =3D <&intc1_4 13>; + no-loopback-test; + status =3D "disabled"; + }; + + uart8: serial@14c33700 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART8CLK>; + interrupts-extended =3D <&intc1_4 14>; + no-loopback-test; + status =3D "disabled"; + }; + + uart9: serial@14c33800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART9CLK>; + interrupts-extended =3D <&intc1_4 15>; + no-loopback-test; + status =3D "disabled"; + }; + + uart10: serial@14c33900 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33900 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART10CLK>; + interrupts-extended =3D <&intc1_4 16>; + no-loopback-test; + status =3D "disabled"; + }; + + uart11: serial@14c33a00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33a00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART11CLK>; + interrupts-extended =3D <&intc1_4 17>; + no-loopback-test; + status =3D "disabled"; + }; + + uart12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended =3D <&intc1_4 18>; + no-loopback-test; + status =3D "disabled"; + }; + + uart13: serial@14c33c00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33c00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART13>; + interrupts-extended =3D <&intc1_0 23>; + no-loopback-test; + status =3D "disabled"; + }; + + uart14: serial@14c33d00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33d00 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&syscon1 SCU1_CLK_UART14>; + interrupts-extended =3D <&intc1_1 23>; + no-loopback-test; + status =3D "disabled"; + }; + }; +}; --=20 2.34.1 From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89E7F2F6182; Wed, 22 Oct 2025 07:05:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116758; cv=none; b=C8fBbIe1NpyJu+8qJ5mpHSFkVxuvM/uKTngiNHCUMWzZWuWemByo/uK0OIhVDsU396t1eRndneI9C6zPAPebahahjchauuGYbIZv71Wnj64rrxRBNkpslii4uc+lXrW/us5Jts1D07Rfli/B3vc07/AdHOQNP0hLFknnOgSmuRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116758; c=relaxed/simple; bh=43IdN5grqab5NtUu5trKBJYwk2qqeBRy9PQwFFafD8k=; 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Wed, 22 Oct 2025 15:05:44 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , Subject: [PATCH v6 5/6] arm64: dts: aspeed: Add AST2700 Evaluation Board Date: Wed, 22 Oct 2025 15:05:42 +0800 Message-ID: <20251022070543.1169173-6-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ASPEED AST2700 EVB is prototype development board based on AST2700 SOC. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 ++++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 22 ++++++++++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1..5b8fbf5b1061 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D aspeed subdir-y +=3D axiado subdir-y +=3D bitmain subdir-y +=3D blaize diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspe= ed/Makefile new file mode 100644 index 000000000000..ffe7e15017cc --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ASPEED) +=3D \ + ast2700-evb.dtb diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/d= ts/aspeed/ast2700-evb.dts new file mode 100644 index 000000000000..654b36ec24de --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g7.dtsi" + +/ { + model =3D "AST2700 EVB"; + compatible =3D "aspeed,ast2700-evb", "aspeed,ast2700"; + + chosen { + stdout-path =3D "serial12:115200n8"; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x0 0x40000000>; + }; +}; + +&uart12 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Sun Dec 14 14:12:13 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C0F52F3C1D; Wed, 22 Oct 2025 07:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116760; cv=none; b=mGrF7H3g5rC6sg5CiWxaTofs0eZi+5oZ7N23oFfJSpCQEHOeqB0lwYdXkaEy0UXYOMklZk4LKw6NfjvmRiQeQzRze++W6z6UGubtzE6w3wD0L0+JSH7bmjteVwQM1ka7jtFlw/seTF5t8+WBlSbuGggvFNFp6dCLRpm7MCnGcJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116760; c=relaxed/simple; bh=ny2XylRjq1EK6h3i/HZ7JxOmnPtg8Rs65J2/1rfDoY8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OosizK3fYvreDNtU1Q3zsmIar9yr/GhEO9QSoT/gwH34Vj5tRm1X0Yi0C1Q42UH9IVpyT5953YOw6ospIVQvrCYTwPqRXL2ckTM3/b0CcIkU7XI0e9FFcLc9LtFLJSRbwHqJ+EiKjBSlIqil008SBa1NWjkzPcG1XzL5Dk+7uRg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 15:05:44 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 15:05:44 +0800 From: Ryan Chen To: ryan_chen , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Lee Jones , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , CC: Krzysztof Kozlowski Subject: [PATCH v6 6/6] arm64: configs: Update defconfig for AST2700 platform support Date: Wed, 22 Oct 2025 15:05:43 +0800 Message-ID: <20251022070543.1169173-7-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> References: <20251022070543.1169173-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable options for ASPEED AST2700 SoC. Signed-off-by: Ryan Chen Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e3a2d37bd104..ca2978dd1ccc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -39,6 +39,7 @@ CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy CONFIG_ARCH_ARTPEC=3Dy +CONFIG_ARCH_ASPEED=3Dy CONFIG_ARCH_AXIADO=3Dy CONFIG_ARCH_BCM=3Dy CONFIG_ARCH_BCM2835=3Dy --=20 2.34.1