From nobody Sun Feb 8 23:25:45 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 429E12F28EA; Wed, 22 Oct 2025 06:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116121; cv=none; b=JA98nQqmiAFumU2CFUUSwDIyh7a7WFfVU0c2NXiASI8HCZBpgceQkObpzwDdg4MpbSudmf8wcML1hZHnUnuiRXme+XRNxPgvyvfaehM+MYRGM+I4b7HlB4BZ2tAaKsYuhzBShyDXF0LjeLUsa1fj29Fz84AS0qK27TgXHsHg11s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116121; c=relaxed/simple; bh=bmb9eM+BZ0fW/zqWpc8eXRBVakRsNbaZfBLvO2ao9oU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r3hiV+L39VO04NEpIaiGtti2T+4PY+FpSDEV/4eIqLTGTU6azruLBUpA0OusXBTPl61Wpa8Oemyp///J7Uh3ruPxS/jmSthl75CQaW30JNTECQOknKMylmZdekeupejEsDRrplD9PSCpaYOzXdjvt3NyeE8x6L7KPz0ivYecqvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 14:55:07 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 14:55:07 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy Date: Wed, 22 Oct 2025 14:55:05 +0800 Message-ID: <20251022065507.1152071-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> References: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 contains two-level interrupt controllers (INTC0 and INTC1), each with its own register space and handling different sets of peripherals. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc0.yaml | 97 +++++++++++++++++++ .../aspeed,ast2700-intc1.yaml | 94 ++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc0.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc1.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc0.yaml b/Documentation/devicetree/bindings/interrupt-controller= /aspeed,ast2700-intc0.yaml new file mode 100644 index 000000000000..93a5b142b0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc0.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Ryan Chen + +title: ASPEED AST2700 Interrupt Controller 0 + +description: + This interrupt controller hardware is first level interrupt controller t= hat + is hooked to the GIC interrupt controller. It's useful to combine multip= le + interrupt sources into 1 interrupt to GIC interrupt controller. + +properties: + compatible: + const: aspeed,ast2700-intc0 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: A child interrupt controller node + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc0-ic + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + minItems: 1 + maxItems: 10 + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0x12100000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x12100000 0x4000>; + + intc0_11: interrupt-controller@1b00 { + #interrupt-cells =3D <1>; + interrupt-controller; + compatible =3D "aspeed,ast2700-intc0-ic"; + reg =3D <0x1b00 0x10>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc1.yaml b/Documentation/devicetree/bindings/interrupt-controller= /aspeed,ast2700-intc1.yaml new file mode 100644 index 000000000000..2f807d074211 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc1.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Ryan Chen + +title: ASPEED AST2700 Interrupt Controller 1 + +description: + This interrupt controller hardware is second level interrupt controller = that + is hooked to a parent interrupt controller. It's useful to combine multi= ple + interrupt sources into 1 interrupt to parent interrupt controller. + +properties: + compatible: + const: aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: A child interrupt controller node + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc1-ic + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 1 + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts-extended + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0x14c18000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x14c18000 0x400>; + + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0>; + }; + + intc1_1: interrupt-controller@110 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x110 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1>; + }; + }; \ No newline at end of file --=20 2.34.1