From nobody Sat Feb 7 18:21:23 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 429E12F28EA; Wed, 22 Oct 2025 06:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116121; cv=none; b=JA98nQqmiAFumU2CFUUSwDIyh7a7WFfVU0c2NXiASI8HCZBpgceQkObpzwDdg4MpbSudmf8wcML1hZHnUnuiRXme+XRNxPgvyvfaehM+MYRGM+I4b7HlB4BZ2tAaKsYuhzBShyDXF0LjeLUsa1fj29Fz84AS0qK27TgXHsHg11s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116121; c=relaxed/simple; bh=bmb9eM+BZ0fW/zqWpc8eXRBVakRsNbaZfBLvO2ao9oU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r3hiV+L39VO04NEpIaiGtti2T+4PY+FpSDEV/4eIqLTGTU6azruLBUpA0OusXBTPl61Wpa8Oemyp///J7Uh3ruPxS/jmSthl75CQaW30JNTECQOknKMylmZdekeupejEsDRrplD9PSCpaYOzXdjvt3NyeE8x6L7KPz0ivYecqvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 14:55:07 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 14:55:07 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy Date: Wed, 22 Oct 2025 14:55:05 +0800 Message-ID: <20251022065507.1152071-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> References: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 contains two-level interrupt controllers (INTC0 and INTC1), each with its own register space and handling different sets of peripherals. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-intc0.yaml | 97 +++++++++++++++++++ .../aspeed,ast2700-intc1.yaml | 94 ++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc0.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc1.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc0.yaml b/Documentation/devicetree/bindings/interrupt-controller= /aspeed,ast2700-intc0.yaml new file mode 100644 index 000000000000..93a5b142b0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc0.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Ryan Chen + +title: ASPEED AST2700 Interrupt Controller 0 + +description: + This interrupt controller hardware is first level interrupt controller t= hat + is hooked to the GIC interrupt controller. It's useful to combine multip= le + interrupt sources into 1 interrupt to GIC interrupt controller. + +properties: + compatible: + const: aspeed,ast2700-intc0 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: A child interrupt controller node + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc0-ic + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts: + minItems: 1 + maxItems: 10 + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0x12100000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x12100000 0x4000>; + + intc0_11: interrupt-controller@1b00 { + #interrupt-cells =3D <1>; + interrupt-controller; + compatible =3D "aspeed,ast2700-intc0-ic"; + reg =3D <0x1b00 0x10>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc1.yaml b/Documentation/devicetree/bindings/interrupt-controller= /aspeed,ast2700-intc1.yaml new file mode 100644 index 000000000000..2f807d074211 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc1.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Ryan Chen + +title: ASPEED AST2700 Interrupt Controller 1 + +description: + This interrupt controller hardware is second level interrupt controller = that + is hooked to a parent interrupt controller. It's useful to combine multi= ple + interrupt sources into 1 interrupt to parent interrupt controller. + +properties: + compatible: + const: aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@": + type: object + description: A child interrupt controller node + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2700-intc1-ic + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 1 + + required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts-extended + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1"; + reg =3D <0x14c18000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x14c18000 0x400>; + + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x100 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 0>; + }; + + intc1_1: interrupt-controller@110 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x110 0x10>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&intc0_11 1>; + }; + }; \ No newline at end of file --=20 2.34.1 From nobody Sat Feb 7 18:21:23 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB96E2F28FA; Wed, 22 Oct 2025 06:55:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116123; cv=none; b=bkcrAG+0ZMWwr5ObdNpbQf1/P3Dft6y9aoJBmJ2/qO8TYzL8h+VxAdmu4PSDx8LV5Q45+KfthbT5lREDPhOmxUSrB5sEob8jS8S+v8DSgBHNv6SJk1oVJtGKyxQFKsZr6vlLE3A75EoTtRZyoKwF4LIdq9lj3IOY9ttSghs1fe4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116123; c=relaxed/simple; bh=BzrCaXKPXbhtCRqARv6HPsWzzxuOToCOtyHrToNQxZ8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=G+js/kCnMuvNu1cyKaxYtwtcF3aqU/O37q60UDsZs/dbYJ8nClWSC7nZBLJo1F97iEIaKoTy+rRaNVdzLb6OhsiMU7lbp/2/fET1qkv3B2hpU8u2D4MPDHNHldukp9JxDkWQ0ZI2a8V35x18gx5Lke4SkU2q6QVFKV5jOM29agY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 14:55:08 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 14:55:08 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for routing/protection display Date: Wed, 22 Oct 2025 14:55:06 +0800 Message-ID: <20251022065507.1152071-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> References: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only include the interrupt controller child node ("aspeed,ast2700-intc-ic"), but also provide interrupt routing and register protection features. Adds debugfs entries for interrupt routing and protection status for AST2700 INTC0/INTC1. Signed-off-by: Ryan Chen --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ast2700-intc.c | 174 +++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/irqchip/irq-ast2700-intc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a61c6dc63c29..75922d5c4da6 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -111,6 +111,12 @@ config AL_FIC help Support Amazon's Annapurna Labs Fabric Interrupt Controller. =20 +config AST2700_INTC + tristate "AST2700 Interrupt Controller" + depends on ARCH_ASPEED + help + Support AST2700 Interrupt Controller. + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 3de083f5484c..055724a9e536 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o +obj-$(CONFIG_AST2700_INTC) +=3D irq-ast2700-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-ast2700-intc.c b/drivers/irqchip/irq-ast27= 00-intc.c new file mode 100644 index 000000000000..7c7241539fe5 --- /dev/null +++ b/drivers/irqchip/irq-ast2700-intc.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AST2700 Interrupt Controller + */ + +#include +#include +#include +#include +#include +#include +#include + +/* INTC0 register layout */ +#define INTC0_PROT_OFFS 0x40 +#define INTC0_ROUTING_SEL0_BASE 0x200 +#define INTC0_ROUTING_GAP 0x100 +#define INTC0_GROUPS 4 + +/* INTC1 register layout */ +#define INTC1_PROT_OFFS 0x00 +#define INTC1_ROUTING_SEL0_BASE 0x80 +#define INTC1_ROUTING_GAP 0x20 +#define INTC1_GROUPS 6 + +struct aspeed_intc_data { + const char *name; + u32 prot_offs; + u32 rout_sel0_base; + u32 rout_gap; + unsigned int groups; +}; + +static const struct aspeed_intc_data aspeed_intc0_data =3D { + .name =3D "INTC0", + .prot_offs =3D INTC0_PROT_OFFS, + .rout_sel0_base =3D INTC0_ROUTING_SEL0_BASE, + .rout_gap =3D INTC0_ROUTING_GAP, + .groups =3D INTC0_GROUPS, +}; + +static const struct aspeed_intc_data aspeed_intc1_data =3D { + .name =3D "INTC1", + .prot_offs =3D INTC1_PROT_OFFS, + .rout_sel0_base =3D INTC1_ROUTING_SEL0_BASE, + .rout_gap =3D INTC1_ROUTING_GAP, + .groups =3D INTC1_GROUPS, +}; + +struct aspeed_intc { + void __iomem *base; + const struct aspeed_intc_data *data; +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_root; +#endif +}; + +#ifdef CONFIG_DEBUG_FS +static int aspeed_intc_regs_show(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + const struct aspeed_intc_data *d =3D intc->data; + void __iomem *base =3D intc->base; + unsigned int i; + + for (i =3D 0; i < d->groups; i++) { + void __iomem *b =3D base + d->rout_sel0_base + i * 4; + u32 r0 =3D readl(b); + u32 r1 =3D readl(b + d->rout_gap); + u32 r2 =3D readl(b + 2 * d->rout_gap); + + seq_printf(s, "ROUTE[%u]: 0x%08x 0x%08x 0x%08x\n", i, r0, r1, r2); + } + return 0; +} + +static int aspeed_intc_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, aspeed_intc_regs_show, inode->i_private); +} + +static const struct file_operations aspeed_intc_regs_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_regs_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static int aspeed_intc_prot_show(struct seq_file *s, void *unused) +{ + struct aspeed_intc *intc =3D s->private; + const struct aspeed_intc_data *d =3D intc->data; + u32 prot =3D readl(intc->base + d->prot_offs); + + seq_printf(s, "%s_PROT: 0x%08x\n", d->name, prot); + return 0; +} + +static int aspeed_intc_prot_open(struct inode *inode, struct file *file) +{ + return single_open(file, aspeed_intc_prot_show, inode->i_private); +} + +static const struct file_operations aspeed_intc_prot_fops =3D { + .owner =3D THIS_MODULE, + .open =3D aspeed_intc_prot_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; +#endif /* CONFIG_DEBUG_FS */ + +static int aspeed_intc_probe(struct platform_device *pdev) +{ + const struct aspeed_intc_data *data; + struct aspeed_intc *intc; + struct resource *res; + + data =3D of_device_get_match_data(&pdev->dev); + if (!data) + return -ENODEV; + + intc =3D devm_kzalloc(&pdev->dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + intc->base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(intc->base)) + return PTR_ERR(intc->base); + + intc->data =3D data; + + platform_set_drvdata(pdev, intc); + +#ifdef CONFIG_DEBUG_FS + intc->dbg_root =3D debugfs_create_dir(dev_name(&pdev->dev), NULL); + if (intc->dbg_root) { + debugfs_create_file("routing", 0400, intc->dbg_root, intc, + &aspeed_intc_regs_fops); + debugfs_create_file("protection", 0400, intc->dbg_root, intc, + &aspeed_intc_prot_fops); + } +#endif + return 0; +} + +static void aspeed_intc_remove(struct platform_device *pdev) +{ +#ifdef CONFIG_DEBUG_FS + struct aspeed_intc *intc =3D platform_get_drvdata(pdev); + + if (intc && intc->dbg_root) + debugfs_remove_recursive(intc->dbg_root); +#endif +} + +static const struct of_device_id aspeed_intc_of_match[] =3D { + { .compatible =3D "aspeed,ast2700-intc0", .data =3D &aspeed_intc0_data }, + { .compatible =3D "aspeed,ast2700-intc1", .data =3D &aspeed_intc1_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, aspeed_intc_of_match); + +static struct platform_driver aspeed_intc_driver =3D { + .probe =3D aspeed_intc_probe, + .remove =3D aspeed_intc_remove, + .driver =3D { + .name =3D "aspeed-ast2700-intc", + .of_match_table =3D aspeed_intc_of_match, + }, +}; +module_platform_driver(aspeed_intc_driver); --=20 2.34.1 From nobody Sat Feb 7 18:21:23 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEFE52F39A8; Wed, 22 Oct 2025 06:55:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 22 Oct 2025 14:55:08 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 22 Oct 2025 14:55:08 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v5 3/3] irqchip: aspeed: add compatible strings for ast2700-intc0-ic and ast2700-intc1-ic Date: Wed, 22 Oct 2025 14:55:07 +0800 Message-ID: <20251022065507.1152071-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> References: <20251022065507.1152071-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2700 SoC defines two parent interrupt controller blocks (INTC0 and INTC1), each containing multiple interrupt-controller child instances ("*-intc-ic"). The existing irqchip driver (irq-aspeed-intc.c) currently only registers a single compatible string: "aspeed,ast2700-intc-ic" To support device trees that describe the INTC0 and INTC1 hierarchy more precisely, this patch adds two additional compatible strings: - "aspeed,ast2700-intc0-ic" - "aspeed,ast2700-intc1-ic" Both map to the same initialization function `aspeed_intc_ic_of_init()`. This allows DTS bindings and drivers for AST2700 INTC0/INTC1 to be matched correctly, while maintaining backward compatibility with the original compatible string. Signed-off-by: Ryan Chen --- drivers/irqchip/irq-aspeed-intc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed= -intc.c index 8330221799a0..a40b406dc8fa 100644 --- a/drivers/irqchip/irq-aspeed-intc.c +++ b/drivers/irqchip/irq-aspeed-intc.c @@ -137,3 +137,5 @@ static int __init aspeed_intc_ic_of_init(struct device_= node *node, } =20 IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_= of_init); +IRQCHIP_DECLARE(ast2700_intc0_ic, "aspeed,ast2700-intc0-ic", aspeed_intc_i= c_of_init); +IRQCHIP_DECLARE(ast2700_intc1_ic, "aspeed,ast2700-intc1-ic", aspeed_intc_i= c_of_init); --=20 2.34.1