From nobody Sun Feb 8 22:01:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03CA2D5927; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116342; cv=none; b=XvxpGi4TKxR25kULslz97GeGurpUTMLcbhuJzZbVcztK+x9VxRoLkI9l2TysqEr9jkdDLTJdf/59Qjnh6o6zGpmYDusmee4L0d64DILSj1DvTA+5FAtN0Pgp3sFWJDAbk3YQrned7QnNLZRAF4woJJ3yQVmBnMQA6mf3sYWJJ54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116342; c=relaxed/simple; bh=I4YsZlslKVYM5XtiEfLCXEYzAjKsoHF2XlksQ5hG6dU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Uz8sCEccbpALBUYyro16xOB2ziDS5LinD8c4CfCS7+W1R//mgfTiOksW6pLo4TqyFWljWXMkVaOads3Fs8/3H5rdvIwtE433F9SkBaIDptJQPzjpAf86dnMBTI8RvFXhJJpofWDRCeohzTFzjilpXEjp53XOdEqwiWMVldDFRi0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Qe99KiEX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Qe99KiEX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6470DC4CEF7; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761116342; bh=I4YsZlslKVYM5XtiEfLCXEYzAjKsoHF2XlksQ5hG6dU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Qe99KiEXbnPS1IW1G/xMz5aP8btVwmr6YKYISN4AXPzR/TrJkaa7rmexGv2Fyhwa+ kyIo81o3EuHgTgNEr0tm3u2lmA/8tEWlWkN5qSSkoyVL1Se0cLkjeIiMMZ1KYhPLmG flxLks8isTfKjeJ0mOYaR+4FoDcZadaPAjZiYF3S/9ekuSeZyiRV9DLJqrjKKcobTA vZJLV4b2I7UE02lmtrDRwb1OTr+49aj93ZG+nIFSAUUkCKx6KW4FRRmhkLRAsZGNFE z0lD8bAts0WBhozTaIq4LySgHtY1Nh9kA836I+l5F2+3aIUFUhbkpxW77odBi4L+3e 3MMV51s72fxbg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 560BECCD1AB; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Wed, 22 Oct 2025 14:58:51 +0800 Subject: [PATCH 1/3] clk: amlogic: Fix out-of-range PLL frequency setting Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251022-optimize_pll_driver-v1-1-a275722fb6f4@amlogic.com> References: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> In-Reply-To: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761116340; l=799; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=p+FnM7SXXWR/Lro1GSMYPZJ+As5vPrIAECBCtFZ7G6Q=; b=ClxCqKi3/e4IxKUNaE1WjlZyjocex3l4YrnDTktPBAF0iswWL7CnwzsCJbhDHBjEFrE9p0UnJ zF2arI+2lxbBlJNKWfslLsxbjOT66SAmuN6iu1Uxvl9WexL9e5nkpts X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu meson_clk_get_pll_range_index incorrectly determines the maximum value of 'm'. Fixes: 8eed1db1adec6 ("clk: meson: pll: update driver for the g12a") Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 1ea6579a760f..b07e1eb19d12 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -191,7 +191,7 @@ static int meson_clk_get_pll_range_index(unsigned long = rate, *m =3D meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); =20 /* the pre-divider gives a multiplier too big - stop */ - if (*m >=3D (1 << pll->m.width)) + if (*m > pll->range->max) return -EINVAL; =20 return 0; --=20 2.42.0 From nobody Sun Feb 8 22:01:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C034F229B38; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116342; cv=none; b=d30ukOeoIOrg9l7Kv9LaNeN3Obe3BcGajqxgYgMhcXVZCPj2HTddfmnmh/7zcxp8En2DIxt2iYU3ZynuLQxrX9JN3R2MSzGIGxu6fKy/Rmp1YBN5yA43lO0fX0qpmtU2MPmpqE6U0PZTa5bZlFOWa2cVEcKo7oswk+hOshwU7FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116342; c=relaxed/simple; bh=tNpHlIQUBTD9AQUIV9HOebg+Mv18j60jJ2qTKmd3Clc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XurN79YkRXBk/JgldsK1l44y3O4EPftX8nIv0yC8ude5p0GbaGab1e/wFie+zS/uKJbOGQxpLDcCP52JEpt9NH8TlsMmtoVxFTUaGLMAAmAWUhRdXW4QbLKc/8LzzTNF1EOyZ+nRNUM+74nE3TkZlGyzlRitg+zQnGdgoIWzQl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f1fLx0De; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f1fLx0De" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7ACB6C113D0; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761116342; bh=tNpHlIQUBTD9AQUIV9HOebg+Mv18j60jJ2qTKmd3Clc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f1fLx0DeQTCDXFzWn9RNlHFljJGeP+4/aI4o4AbDw3WEYh9/dZChmaImw4Avn3otF Tu09h3sQ00nFFvTc95+87SwvpKOq65UPG1MM/SH1ZwSqf9mYhujhYECftsAI7XLHmM 6+PGGSlVeew2zF33q8xTkqWM95445oQxTB4cQVXUYhgYxXtkRzxQTd56moc/X4jic4 +/w97Cw2AHUS4YxWB5sOKMDkafgw48224tYobLD7AVEFK1oBSi/f+Axq0i9ECovy0w KBUN3oJRQZd9g0WJbqzgX8twg8BGvliyDmJxkqulFyjAHXVPf3I20mFcZCqN0Lk6+e TRWveLQqWyDVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E48DCCD1BE; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Wed, 22 Oct 2025 14:58:52 +0800 Subject: [PATCH 2/3] clk: amlogic: Optimize PLL enable timing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251022-optimize_pll_driver-v1-2-a275722fb6f4@amlogic.com> References: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> In-Reply-To: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761116340; l=4402; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=bsdTchbiRzU7fQnKSjIW161Jtz+ZayPt5sUS3k0V7QU=; b=AEy5PXpFUMdDMXW6q9jCnGv15v8j0xAtKltUNJgWlUAFVhON3sKl2AoUsoePKRadfRMVcNgjv Qj49HwbWa0bDBPIE1TIVUT3cZvV2sp/7ONf6SARkAIpNAB4XiYubxvF X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Amlogic PLL locking procedure shall follow this timing sequence: 1 Assert reset signal: Ensures PLL circuits enter known initial state. 2 Deassert lock-detect signal: Avoid lock signal false triggering. 3 Assert enable signal: Powers up PLL supply. 4 udelay(20): Wait for Bandgap and LDO to power up and stabilize. 5 Enable self-adaptation current module (Optional). 6 Deassert reset signal: Releases PLL to begin normal operation. 7 udelay(20): Wait for PLL loop stabilization. 8 Assert lock-detect signal: lock detection circuit starts to work. 9 Monitor lock status signal: Wait for PLL lock completion. 10 If the PLL fails to lock, it should be disabled, This makes the logic more complete, and also helps save unnecessary power consumption when the PLL is malfunctioning. Signed-off-by: Chuan Liu --- drivers/clk/meson/clk-pll.c | 68 ++++++++++++++++++++++++++---------------= ---- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index b07e1eb19d12..26c83db487e8 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw) return -EIO; } =20 +static void meson_clk_pll_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + + /* Put the pll is in reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); + + /* Disable the pll */ + meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); @@ -366,53 +383,48 @@ static int meson_clk_pll_enable(struct clk_hw *hw) if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); =20 + /* Disable the PLL lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 1); + /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); - - /* Take the pll out reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 0); + /* Wait for Bandgap and LDO to power up and stabilize */ + udelay(20); =20 /* * Compared with the previous SoCs, self-adaption current module * is newly added for A1, keep the new power-on sequence to enable the * PLL. The sequence is: - * 1. enable the pll, delay for 10us + * 1. enable the pll, ensure a minimum delay of 10=CE=BCs * 2. enable the pll self-adaption current module, delay for 40us * 3. enable the lock detect module */ if (MESON_PARM_APPLICABLE(&pll->current_en)) { - udelay(10); meson_parm_write(clk->map, &pll->current_en, 1); - udelay(40); - } - - if (MESON_PARM_APPLICABLE(&pll->l_detect)) { - meson_parm_write(clk->map, &pll->l_detect, 1); - meson_parm_write(clk->map, &pll->l_detect, 0); + udelay(20); } =20 - if (meson_clk_pll_wait_lock(hw)) - return -EIO; + /* Take the pll out reset */ + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 0); =20 - return 0; -} + /* Wait for PLL loop stabilization */ + udelay(20); =20 -static void meson_clk_pll_disable(struct clk_hw *hw) -{ - struct clk_regmap *clk =3D to_clk_regmap(hw); - struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + /* Enable the lock-detect module */ + if (MESON_PARM_APPLICABLE(&pll->l_detect)) + meson_parm_write(clk->map, &pll->l_detect, 0); =20 - /* Put the pll is in reset */ - if (MESON_PARM_APPLICABLE(&pll->rst)) - meson_parm_write(clk->map, &pll->rst, 1); + if (meson_clk_pll_wait_lock(hw)) { + /* disable PLL when PLL lock failed. */ + meson_clk_pll_disable(hw); + pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw)); =20 - /* Disable the pll */ - meson_parm_write(clk->map, &pll->en, 0); + return -EIO; + } =20 - /* Disable PLL internal self-adaption current module */ - if (MESON_PARM_APPLICABLE(&pll->current_en)) - meson_parm_write(clk->map, &pll->current_en, 0); + return 0; } =20 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, --=20 2.42.0 From nobody Sun Feb 8 22:01:02 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E24072F25E0; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116343; cv=none; b=bLR3ZZv5zlWc4WFdjIzVfdyupFHqCA7NPLb8v6GCuYpi82SFsWgTa5p047mpReeDt757ku7VRXpG1vozXAFASJbAVcmfe9fBFNMSLTw6ydGGT449UZPYIxK8p9GbIYgd93HPMomZSYgLx67bseyy89TyaXKC87Vclwy1X7sQU4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761116343; c=relaxed/simple; bh=tz1GN08S5uBHLdjHa0/ozlnw2WRGrO+4LkQLFLPDiG8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XCG20QnbT8JOcWC4A6JSKECSYRi4L4ChK5zkvXYWudBwWFikFqn42hjwV9XyOnuUofAvBi+9I2W4Qox0AHJoiG7/kKDAPi2MRZw53bBE34oz4YY8J9cO98+i1YMe0JVnNYCoK8Q2JihKbc900Wnu/19xx3rLQpOWP7mBxws70Uc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r9hurdRu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r9hurdRu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8AEC0C116B1; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761116342; bh=tz1GN08S5uBHLdjHa0/ozlnw2WRGrO+4LkQLFLPDiG8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=r9hurdRub6sjGdNeStvNxLamcg5Bb540sE3Ej4LbE+9a9CKMk7vEQmem67Aoy80vZ t0DNgRy3fMrNbD53L7H7QEgtAxv4d7dz4CsmqJYjZitDRXIfbJ3ZyrdeosV5lNqsVD QG0k8rEUoUsDoqJAnsYTIsf21RGjIJBC14+4h6UOsYzMEV2MRedVKHsRDtnpnxjXQg 7SfRpc1mwq6zs+cL/WX1a8Y5jA1wT1kcToeTteC2njzVlIkm0vK8kRQjFaQWX9uhJt rG8yLaRsefFrhvB2WmucpJv3YVAiVhUafBRqZTdAFasf6rjaAVKx3W6nlMnkxe3OT7 wGK3NrujhwxJg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81C64CCF9E0; Wed, 22 Oct 2025 06:59:02 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Wed, 22 Oct 2025 14:58:53 +0800 Subject: [PATCH 3/3] clk: amlogic: Correct l_detect bit control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251022-optimize_pll_driver-v1-3-a275722fb6f4@amlogic.com> References: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> In-Reply-To: <20251022-optimize_pll_driver-v1-0-a275722fb6f4@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761116340; l=2616; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=Dv3cPzZdf9Puk7bgGlGkCfNCiEdGxmv1X3Nj/+D8POg=; b=BHhN2TDgNFvv/uGPJJpyLvmLNfv+ZEmzL2S9sXilJFfhJvBFD6R+79Z2raY7XQiQGmLbIXNag V96WVa094xKBAJKEsbT4Kw52S5AzhIJN0wziJopr6yAfXB1pIQvlO+K X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu l_detect controls the enable/disable of the PLL lock-detect module. For A1, the l_detect signal is active-low: 0 -> Enable lock-detect module; 1 -> Disable lock-detect module. Signed-off-by: Chuan Liu --- drivers/clk/meson/a1-pll.c | 1 + drivers/clk/meson/clk-pll.c | 16 ++++++++++++---- drivers/clk/meson/clk-pll.h | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 1f82e9c7c14e..bfe559c71402 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll =3D { .range =3D &a1_hifi_pll_range, .init_regs =3D a1_hifi_pll_init_regs, .init_count =3D ARRAY_SIZE(a1_hifi_pll_init_regs), + .flags =3D CLK_MESON_PLL_L_DETECT_N }, .hw.init =3D &(struct clk_init_data){ .name =3D "hifi_pll", diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 26c83db487e8..602c93aba3cc 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) meson_parm_write(clk->map, &pll->rst, 1); =20 /* Disable the PLL lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 1); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 1); + else + meson_parm_write(clk->map, &pll->l_detect, 0); + } =20 /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); @@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw) udelay(20); =20 /* Enable the lock-detect module */ - if (MESON_PARM_APPLICABLE(&pll->l_detect)) - meson_parm_write(clk->map, &pll->l_detect, 0); + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + if (pll->flags & CLK_MESON_PLL_L_DETECT_N) + meson_parm_write(clk->map, &pll->l_detect, 0); + else + meson_parm_write(clk->map, &pll->l_detect, 1); + } =20 if (meson_clk_pll_wait_lock(hw)) { /* disable PLL when PLL lock failed. */ diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 949157fb7bf5..83295a24721f 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -29,6 +29,8 @@ struct pll_mult_range { =20 #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) +/* l_detect signal is active-low */ +#define CLK_MESON_PLL_L_DETECT_N BIT(2) =20 struct meson_clk_pll_data { struct parm en; --=20 2.42.0