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This causes vendor drivers to incorrectly program iATU regions, as they rely on the DBI address for internal accesses. To fix this, avoid overwriting the DBI base when ECAM is enabled. Instead, introduce a custom ECAM PCI ops implementation that accesses the DBI region directly for root bus and uses ECAM for other buses. Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechan= ism using iATU 'CFG Shift Feature'") Reported-by: Ron Economos Closes: https://lore.kernel.org/all/eac81c57-1164-4d74-a1b4-6f353c577731@w6= rz.net/ Suggested-by: Manivannan Sadhasivam Tested-by: Ron Economos Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 28 +++++++++++++++++++= ---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 20c9333bcb1c4812e2fd96047a49944574df1e6f..7d95d8ec9f8190dbde80283db78= ca74925532d2e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -23,6 +23,7 @@ #include "pcie-designware.h" =20 static struct pci_ops dw_pcie_ops; +static struct pci_ops dw_pcie_ecam_ops; static struct pci_ops dw_child_pcie_ops; =20 #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ @@ -471,9 +472,6 @@ static int dw_pcie_create_ecam_window(struct dw_pcie_rp= *pp, struct resource *re if (IS_ERR(pp->cfg)) return PTR_ERR(pp->cfg); =20 - pci->dbi_base =3D pp->cfg->win; - pci->dbi_phys_addr =3D res->start; - return 0; } =20 @@ -529,7 +527,7 @@ static int dw_pcie_host_get_resources(struct dw_pcie_rp= *pp) if (ret) return ret; =20 - pp->bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->ops =3D &dw_pcie_ecam_ops; pp->bridge->sysdata =3D pp->cfg; pp->cfg->priv =3D pp; } else { @@ -842,12 +840,34 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus= *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); =20 +static void __iomem *dw_pcie_ecam_conf_map_bus(struct pci_bus *bus, unsign= ed int devfn, int where) +{ + struct pci_config_window *cfg =3D bus->sysdata; + struct dw_pcie_rp *pp =3D cfg->priv; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + + if (bus =3D=3D pp->bridge->bus) { + if (PCI_SLOT(devfn) > 0) + return NULL; + + return pci->dbi_base + where; + } + + return pci->dbi_base + where; +} + static struct pci_ops dw_pcie_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, }; =20 +static struct pci_ops dw_pcie_ecam_ops =3D { + .map_bus =3D dw_pcie_ecam_conf_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); --=20 2.34.1