From nobody Sat Feb 7 10:08:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D006F31B81B; Wed, 22 Oct 2025 10:10:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127829; cv=none; b=UtrxV7Z7BcQJ86BpWEhcOGWJnNKnQ/XPwQlLpHk8y6CN1HYEUSnnew0UbNMG4mAEQstc8JHnBrfMDqQeFjxU8nHOh90xQ23YpFHrSOwImo6v8wxKbLbMAAzNu9SAYRV8t27O20ifYiroYcbxB5cY/33qZuqFRm/SlA/5ZNXw1c0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127829; c=relaxed/simple; bh=zi3cc7PAuRi6WyofGAEktHm+EAJprbFuiuUU5KX4/w8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n4neuatDaBomeT79dSWCBhJLuOknsQ1X1sTnDOAO24OnXlCDCXPJWAX5WYStp/TnC6/d8uwMEIf+qh4Qi1grlxhC4F8PufIa+nUJ7vnexLX6JhBvrr9O6PEC+LPowjnaNsqR82c5mjW6JtjaXC2+QXe0QJYLtsLuVN3vK3b0jHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kvefmw7h; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kvefmw7h" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 917F6C4CEE7; Wed, 22 Oct 2025 10:10:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761127828; bh=zi3cc7PAuRi6WyofGAEktHm+EAJprbFuiuUU5KX4/w8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kvefmw7h0wabMnDB0vQIBGBeoprFXwKaFBRcK1qp3IQAI7qEaqQAgCp4gVEItRauK p/2HtsFm216b3C/Nb8BM2QbalvGM4mvmHLxz76LNUCc7Bgqa6YCcpFC/I5qs5kgwxP 0aGGxxJF3irR+kKp+Iu4QlfdQAO4UM9ttQjarhwlK2aGOvQFhFm0jbiwTRlYW9pfHU nanhVOfgEK4KM5WpBoeo82YGG/aGO0sEgwCyjrAzLplNIbHVHpAA3QvqWXZtsXQ2Hc Znw8t9OHDlTGBKd04UlqV+oNvrSZMd9UbrNiH1OQJipjU4dFuKuY0tZr/YMtjNrGMj 8pE3yCXJxUv0Q== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v3 1/5] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux Date: Wed, 22 Oct 2025 11:09:09 +0100 Message-ID: <20251022-capably-footage-4ed2dbbf3f4c@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251022-dash-refinance-ac3387657ae4@spud> References: <20251022-dash-refinance-ac3387657ae4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4050; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Jk/6HIrECIVEHfcbYSJ8Aq4OM+MqwbVRsFMTl8kKsNw=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBk/1kb7393+w/ZnQrv18UVy5z03XmE0Y1vIZRSr90K2o WV++pnEjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzEfh8jw5J1x7fZubd935j+ yv/YuqgtD4/9NlvQ2Fq75/IaRlUTNklGho39Z67oeN0y2fPB8cS0nUdv3GBl+VS4JmuZTksq7+6 EXg4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Currently there is no documentation about what each bit actually does that is publicly available, nor (I believe) what pins are affected. That info is as follows: pin role (1/0) Reviewed-by: Rob Herring (Arm) --- ---------- E14 MAC_0_MDC/GPIO_2_0 E15 MAC_0_MDIO/GPIO_2_1 F16 MAC_1_MDC/GPIO_2_2 F17 MAC_1_MDIO/GPIO_2_3 D19 SPI_0_CLK/GPIO_2_4 B18 SPI_0_SS0/GPIO_2_5 B10 CAN_0_RXBUS/GPIO_2_6 C14 PCIE_PERST_2#/GPIO_2_7 E18 PCIE_WAKE#/GPIO_2_8 D18 PCIE_PERST_1#/GPIO_2_9 E19 SPI_0_DO/GPIO_2_10 C7 SPI_0_DI/GPIO_2_11 D6 QSPI_SS0/GPIO_2_12 D7 QSPI_CLK (B)/GPIO_2_13 C9 QSPI_DATA0/GPIO_2_14 C10 QSPI_DATA1/GPIO_2_15 A5 QSPI_DATA2/GPIO_2_16 A6 QSPI_DATA3/GPIO_2_17 D8 MMUART_3_RXD/GPIO_2_18 D9 MMUART_3_TXD/GPIO_2_19 B8 MMUART_4_RXD/GPIO_2_20 A8 MMUART_4_TXD/GPIO_2_21 C12 CAN_1_TXBUS/GPIO_2_22 B12 CAN_1_RXBUS/GPIO_2_23 A11 CAN_0_TX_EBL_N/GPIO_2_24 A10 CAN_1_TX_EBL_N/GPIO_2_25 D11 MMUART_2_RXD/GPIO_2_26 C11 MMUART_2_TXD/GPIO_2_27 B9 CAN_0_TXBUS/GPIO_2_28 Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../microchip,pic64gx-pinctrl-gpio2.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic= 64gx-pinctrl-gpio2.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pi= nctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic6= 4gx-pinctrl-gpio2.yaml new file mode 100644 index 000000000000..07d6befb299c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-g= pio2.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux via iomux0 for settings here to have any impact. + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, = uart2, gpio ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1= , uart2, + gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, + gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2= ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@41000000 { + compatible =3D "microchip,pic64gx-pinctrl-gpio2"; + reg =3D <0x41000000 0x4>; + pinctrl-use-default; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_= gpio2>, + <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gp= io2>, + <&uart2_gpio2>; + + mux-gpio2 { + function =3D "gpio"; + groups =3D "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; + }; + }; + +... --=20 2.51.0 From nobody Sat Feb 7 10:08:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11ED7320A0F; Wed, 22 Oct 2025 10:10:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127831; cv=none; b=kB6Uvv7KtOcbLQ1vE70baNzwE3j7EwheopuC8TqYXa3VZSnMed87PKFd2dFmMMt5X06KR9MwsRXs9t6CHFY8+fANXz3RtOxztvEWAMZSlHpX6rhd9izm3COIH5nfpZNTS+U0fsnGoCvlxyM5kKlm6s4C64MJNfInxzRp0Iib0wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127831; c=relaxed/simple; bh=1RIR6sd/TBREn2myqoXqIybk1h8ttf7pSz2j+UceWT4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CSDGFFaHGLjgdQG76xOOGA0+QE+uFBqloSK4ZukgSP2JhsRfroysxPz/RoxVGfTNcB89HiguP1iXvWb9e/UVe90dJWVxXYIo0dpuJYlFAUv3ON8t1BThoOFIgBuAoKYO2aHptS8D3hYcg+tAF3vtvALRDKj989McSJ+ZRfBJkMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I7zkvD78; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I7zkvD78" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C396CC4CEFF; Wed, 22 Oct 2025 10:10:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761127830; bh=1RIR6sd/TBREn2myqoXqIybk1h8ttf7pSz2j+UceWT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I7zkvD78aBwTx9vSR2qQQ7HKVfQFEnR79loLyNMdOhS4lATSbOZK3G3B8bAbdwekQ QskbCxCfudiJDq+2QtAvM9jgDhtimQKCqZaapJNTlR3HbTFAc5479dBH2KJMLfFzgu PBHjHV4xuZXxt+w2j1IFea0CkB/4PphL8Tr9anLrE6VIpy7E8dAx619r2nd6ADqqFd TShQynBKINLK7Z3GhjJQQy+T7FGkthXlgZ+vsk6P9Hb7JKT+7B03PC2GpRwabOA39u 2CLu7ez64sYsfWGhfLLL5pT+zpw5De9Pfd8DmM3ACBnXgzUpq4Ckl+cUeqqa0Fioqy V5aXdecoBLUuw== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v3 2/5] pinctrl: add pic64gx "gpio2" pinmux driver Date: Wed, 22 Oct 2025 11:09:10 +0100 Message-ID: <20251022-shakily-sinner-7325cdf67463@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251022-dash-refinance-ac3387657ae4@spud> References: <20251022-dash-refinance-ac3387657ae4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12131; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=81hTZ4qEz/0MgkwoUR5e217Jfv2h0ZsKkrTXugpFNag=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBk/1kZXTlz0pn0xy9PAqDSt05Xeu9OXdDJ2rtsSbJxS5 af04ppdRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACaytI/hr9gRR72vNk8cLefu 21Glbr+nw1v0pphC1asntx4VtMtK9TAyXFRQ0u8M7GOyq1PdOOWB/JFjt9tzGWN4uqafnax09/x 9JgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The documentation for the SoC provides no name for this device, but it is used to swap pins between either GPIO controller #2 or select other functions, hence the "gpio2" name. Add a driver for it. Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-pic64gx-gpio2.c | 356 ++++++++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-pic64gx-gpio2.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4f8507ebbdac..e83fda9bf308 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -486,6 +486,14 @@ config PINCTRL_PIC32MZDA def_bool y if PIC32MZDA select PINCTRL_PIC32 =20 +config PINCTRL_PIC64GX + bool "pic64gx gpio2 pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for gpio2 on pic64gx. + config PINCTRL_PISTACHIO bool "IMG Pistachio SoC pinctrl driver" depends on OF && (MIPS || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e0cfb9b7c99b..f33976a6c91b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) +=3D pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_PALMAS) +=3D pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o +obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/pinc= trl-pic64gx-gpio2.c new file mode 100644 index 000000000000..f322bb5e6181 --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define PIC64GX_PINMUX_REG 0x0 + +static const struct regmap_config pic64gx_gpio2_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D 0x0, +}; + +struct pic64gx_gpio2_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct pic64gx_gpio2_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 setting; +}; + +struct pic64gx_gpio2_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const struct pinctrl_pin_desc pic64gx_gpio2_pins[] =3D { + PINCTRL_PIN(0, "E14"), + PINCTRL_PIN(1, "E15"), + PINCTRL_PIN(2, "F16"), + PINCTRL_PIN(3, "F17"), + PINCTRL_PIN(4, "D19"), + PINCTRL_PIN(5, "B18"), + PINCTRL_PIN(6, "B10"), + PINCTRL_PIN(7, "C14"), + PINCTRL_PIN(8, "E18"), + PINCTRL_PIN(9, "D18"), + PINCTRL_PIN(10, "E19"), + PINCTRL_PIN(11, "C7"), + PINCTRL_PIN(12, "D6"), + PINCTRL_PIN(13, "D7"), + PINCTRL_PIN(14, "C9"), + PINCTRL_PIN(15, "C10"), + PINCTRL_PIN(16, "A5"), + PINCTRL_PIN(17, "A6"), + PINCTRL_PIN(18, "D8"), + PINCTRL_PIN(19, "D9"), + PINCTRL_PIN(20, "B8"), + PINCTRL_PIN(21, "A8"), + PINCTRL_PIN(22, "C12"), + PINCTRL_PIN(23, "B12"), + PINCTRL_PIN(24, "A11"), + PINCTRL_PIN(25, "A10"), + PINCTRL_PIN(26, "D11"), + PINCTRL_PIN(27, "C11"), + PINCTRL_PIN(28, "B9"), +}; + +static const unsigned int pic64gx_gpio2_mdio0_pins[] =3D { + 0, 1 +}; + +static const unsigned int pic64gx_gpio2_mdio1_pins[] =3D { + 2, 3 +}; + +static const unsigned int pic64gx_gpio2_spi0_pins[] =3D { + 4, 5, 10, 11 +}; + +static const unsigned int pic64gx_gpio2_can0_pins[] =3D { + 6, 24, 28 +}; + +static const unsigned int pic64gx_gpio2_pcie_pins[] =3D { + 7, 8, 9 +}; + +static const unsigned int pic64gx_gpio2_qspi_pins[] =3D { + 12, 13, 14, 15, 16, 17 +}; + +static const unsigned int pic64gx_gpio2_uart3_pins[] =3D { + 18, 19 +}; + +static const unsigned int pic64gx_gpio2_uart4_pins[] =3D { + 20, 21 +}; + +static const unsigned int pic64gx_gpio2_can1_pins[] =3D { + 22, 23, 25 +}; + +static const unsigned int pic64gx_gpio2_uart2_pins[] =3D { + 26, 27 +}; + +#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \ + .name =3D "gpio_" #_name, \ + .pins =3D pic64gx_gpio2_##_name##_pins, \ + .num_pins =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask =3D _mask, \ + .setting =3D 0x0, \ +}, { \ + .name =3D #_name, \ + .pins =3D pic64gx_gpio2_##_name##_pins, \ + .num_pins =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \ + .mask =3D _mask, \ + .setting =3D _mask, \ +} + +static const struct pic64gx_gpio2_pin_group pic64gx_gpio2_pin_groups[] =3D= { + PIC64GX_PINCTRL_GROUP(mdio0, BIT(0) | BIT(1)), + PIC64GX_PINCTRL_GROUP(mdio1, BIT(2) | BIT(3)), + PIC64GX_PINCTRL_GROUP(spi0, BIT(4) | BIT(5) | BIT(10) | BIT(11)), + PIC64GX_PINCTRL_GROUP(can0, BIT(6) | BIT(24) | BIT(28)), + PIC64GX_PINCTRL_GROUP(pcie, BIT(7) | BIT(8) | BIT(9)), + PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)), + PIC64GX_PINCTRL_GROUP(uart3, BIT(18) | BIT(19)), + PIC64GX_PINCTRL_GROUP(uart4, BIT(20) | BIT(21)), + PIC64GX_PINCTRL_GROUP(can1, BIT(22) | BIT(23) | BIT(25)), + PIC64GX_PINCTRL_GROUP(uart2, BIT(26) | BIT(27)), +}; + +static const char * const pic64gx_gpio2_gpio_groups[] =3D { + "gpio_mdio0", "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1", "gpio_uart2" +}; + +static const char * const pic64gx_gpio2_mdio0_groups[] =3D { + "mdio0" +}; + +static const char * const pic64gx_gpio2_mdio1_groups[] =3D { + "mdio1" +}; + +static const char * const pic64gx_gpio2_spi0_groups[] =3D { + "spi0" +}; + +static const char * const pic64gx_gpio2_can0_groups[] =3D { + "can0" +}; + +static const char * const pic64gx_gpio2_pcie_groups[] =3D { + "pcie" +}; + +static const char * const pic64gx_gpio2_qspi_groups[] =3D { + "qspi" +}; + +static const char * const pic64gx_gpio2_uart3_groups[] =3D { + "uart3" +}; + +static const char * const pic64gx_gpio2_uart4_groups[] =3D { + "uart4" +}; + +static const char * const pic64gx_gpio2_can1_groups[] =3D { + "can1" +}; + +static const char * const pic64gx_gpio2_uart2_groups[] =3D { + "uart2" +}; + +#define PIC64GX_PINCTRL_FUNCTION(_name) { \ + .name =3D #_name, \ + .groups =3D pic64gx_gpio2_##_name##_groups, \ + .num_groups =3D ARRAY_SIZE(pic64gx_gpio2_##_name##_groups), \ +} + +static const struct pic64gx_gpio2_function pic64gx_gpio2_functions[] =3D { + PIC64GX_PINCTRL_FUNCTION(gpio), + PIC64GX_PINCTRL_FUNCTION(mdio0), + PIC64GX_PINCTRL_FUNCTION(mdio1), + PIC64GX_PINCTRL_FUNCTION(spi0), + PIC64GX_PINCTRL_FUNCTION(can0), + PIC64GX_PINCTRL_FUNCTION(pcie), + PIC64GX_PINCTRL_FUNCTION(qspi), + PIC64GX_PINCTRL_FUNCTION(uart3), + PIC64GX_PINCTRL_FUNCTION(uart4), + PIC64GX_PINCTRL_FUNCTION(can1), + PIC64GX_PINCTRL_FUNCTION(uart2), +}; + +static void pic64gx_gpio2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, stru= ct seq_file *seq, + unsigned int pin) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + u32 val; + + regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val); + val =3D (val & BIT(pin)) >> pin; + seq_printf(seq, "pin: %u val: %x\n", pin, val); +} + +static int pic64gx_gpio2_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(pic64gx_gpio2_pin_groups); +} + +static const char *pic64gx_gpio2_group_name(struct pinctrl_dev *pctldev, u= nsigned int selector) +{ + return pic64gx_gpio2_pin_groups[selector].name; +} + +static int pic64gx_gpio2_group_pins(struct pinctrl_dev *pctldev, unsigned = int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins =3D pic64gx_gpio2_pin_groups[selector].pins; + *num_pins =3D pic64gx_gpio2_pin_groups[selector].num_pins; + + return 0; +} + +static const struct pinctrl_ops pic64gx_gpio2_pinctrl_ops =3D { + .get_groups_count =3D pic64gx_gpio2_groups_count, + .get_group_name =3D pic64gx_gpio2_group_name, + .get_group_pins =3D pic64gx_gpio2_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinctrl_utils_free_map, + .pin_dbg_show =3D pic64gx_gpio2_pin_dbg_show, +}; + +static int pic64gx_gpio2_pinmux_get_funcs_count(struct pinctrl_dev *pctlde= v) +{ + return ARRAY_SIZE(pic64gx_gpio2_functions); +} + +static const char *pic64gx_gpio2_pinmux_get_func_name(struct pinctrl_dev *= pctldev, + unsigned int selector) +{ + return pic64gx_gpio2_functions[selector].name; +} + +static int pic64gx_gpio2_pinmux_get_groups(struct pinctrl_dev *pctldev, un= signed int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D pic64gx_gpio2_functions[selector].groups; + *num_groups =3D pic64gx_gpio2_functions[selector].num_groups; + + return 0; +} + +static int pic64gx_gpio2_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, uns= igned int fsel, + unsigned int gsel) +{ + struct pic64gx_gpio2_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev= ); + struct device *dev =3D pctrl->dev; + const struct pic64gx_gpio2_pin_group *group; + const struct pic64gx_gpio2_function *function; + + group =3D &pic64gx_gpio2_pin_groups[gsel]; + function =3D &pic64gx_gpio2_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, PIC64GX_PINMUX_REG, group->mask, group-= >setting); + + return 0; +} + +static const struct pinmux_ops pic64gx_gpio2_pinmux_ops =3D { + .get_functions_count =3D pic64gx_gpio2_pinmux_get_funcs_count, + .get_function_name =3D pic64gx_gpio2_pinmux_get_func_name, + .get_function_groups =3D pic64gx_gpio2_pinmux_get_groups, + .set_mux =3D pic64gx_gpio2_pinmux_set_mux, +}; + +static int pic64gx_gpio2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pic64gx_gpio2_pinctrl *pctrl; + void __iomem *base; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "Failed get resource\n"); + return PTR_ERR(base); + } + + pctrl->regmap =3D devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_regmap_= config); + if (IS_ERR(pctrl->regmap)) { + dev_err(dev, "Failed to map regmap\n"); + return PTR_ERR(pctrl->regmap); + } + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D pic64gx_gpio2_pins; + pctrl->desc.npins =3D ARRAY_SIZE(pic64gx_gpio2_pins); + pctrl->desc.pctlops =3D &pic64gx_gpio2_pinctrl_ops; + pctrl->desc.pmxops =3D &pic64gx_gpio2_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id pic64gx_gpio2_of_match[] =3D { + { .compatible =3D "microchip,pic64gx-pinctrl-gpio2" }, + { } +}; +MODULE_DEVICE_TABLE(of, pic64gx_gpio2_of_match); + +static struct platform_driver pic64gx_gpio2_driver =3D { + .driver =3D { + .name =3D "pic64gx-pinctrl-gpio2", + .of_match_table =3D pic64gx_gpio2_of_match, + }, + .probe =3D pic64gx_gpio2_probe, +}; +module_platform_driver(pic64gx_gpio2_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Sat Feb 7 10:08:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C95C320CC9; Wed, 22 Oct 2025 10:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127833; cv=none; b=Xq2gvnEHJIYgxv/NSmaJ6u6BvoRMEk/Jw76NXA784sUXV0FoROw+aOxarsOi0fEsEnLfe/4jp6L7ryot6qgk3apT9eBN4MMfe3DZNzCpdCXgtqNspv5x8A0aKdq0WYZ7R+cUOMo9RNmW4RinfkeFF1VC6ngQgQ84CR+P2q6+EsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127833; c=relaxed/simple; bh=hcFz4u8+rtY5ddpOS47ADX4pSkG8eSZvmm9rF17SRTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A/IwuLXml04KG9SdtUN8lLxytmF9pEtOc9AVkDrMOoIm/atVEPz0I7f2388+22X180gRqvhVxyuT+W/bfFPNWREPcV3AhlNtWQ9rKm6OQ3/aN9xsVUqFxBeFJjMhmcIxVvqLIXW9fiZPk0fN6xILmDcEMPKwXzOIDZuk5Vz48I0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ma680Yto; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ma680Yto" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01BF3C4CEF5; Wed, 22 Oct 2025 10:10:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761127832; bh=hcFz4u8+rtY5ddpOS47ADX4pSkG8eSZvmm9rF17SRTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ma680YtowsFU/CE5XqhQrcZXRnB3zLOicD/eEonTPkbt7BsoAUFyDJW3PmhlFaq1M ljjwYkmJDZY25ocCPMJK0RDfxua2rStR9N+QD7Kx61q8reSEh/0V15kZ/jL8K4DC3p A0AM98xaHK4onO26R9gxCiGvlYJIJ7aPTsPuQj9Ebe69Gdse1i29J2i599Lpie7Foa Ok3RKGnwuWgu8fgPQrrJUGdQi+NzSwuclO2MtsF4j31kxXFkt7vrIE9BTr+WlzbqfK mKsyos6hF4oHyVB5E4+ZkXXBGRgnpWBom3kNCcAVzW8Wh2cUMPmkuI9Fr0x1RF1Oui 9GC7lJNW359Mg== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux Date: Wed, 22 Oct 2025 11:09:11 +0100 Message-ID: <20251022-caregiver-scrubber-3ad2bc328aea@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251022-dash-refinance-ac3387657ae4@spud> References: <20251022-dash-refinance-ac3387657ae4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4824; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=q3jL7FEIY1rUtQC9fjJwm3OEzGvOXlWYYKQmKkrsuKY=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBk/1kZPv6r26eI8te2/GY9PrOHN/xNWx7y+MOfqwRMTz A89WL0yq6OUhUGMi0FWTJEl8XZfi9T6Py47nHvewsxhZQIZwsDFKQATmSHL8M/c9u7Svc94+1Y/ n53HO/eB523p/6Xevo9Wcc/t4MwtUnnP8L9usuyTHA/3eW4bWI2kVpmG1vxZK9N+ddWHi4wbP8+ /PZkBAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Document it. Reviewed-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../microchip,mpfs-pinctrl-iomux0.yaml | 88 +++++++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 13 ++- 2 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpf= s-pinctrl-iomux0.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinct= rl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-p= inctrl-iomux0.yaml new file mode 100644 index 000000000000..2b718de83a83 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomu= x0.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley + +description: + iomux0 is responsible for routing some functions to either the FPGA fabr= ic, + or to MSSIOs. It only performs muxing, and has no IO configuration role,= as + fabric IOs are configured separately and just routing a function to MSSI= Os is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, ua= rt2, + uart3, uart4, mdio0, mdio1 ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_f= abric, + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_m= ssio, + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio, + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio, + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio, + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio, + mdio1_fabric, mdio1_mssio ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #size-cells =3D <1>; + #address-cells =3D <1>; + + pinctrl@200 { + compatible =3D "microchip,mpfs-pinctrl-iomux0"; + reg =3D <0x200 0x4>; + + mux-spi0-fabric { + function =3D "spi0"; + groups =3D "spi0_fabric"; + }; + + mux-spi1-mssio { + function =3D "spi1"; + groups =3D "spi1_mssio"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml index 1ab691db8795..39987f722411 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -18,10 +18,17 @@ properties: items: - const: microchip,mpfs-mss-top-sysreg - const: syscon + - const: simple-mfd =20 reg: maxItems: 1 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#reset-cells': description: The AHB/AXI peripherals on the PolarFire SoC have reset support, so @@ -31,6 +38,10 @@ properties: of PolarFire clock/reset IDs. const: 1 =20 + pinctrl@200: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + required: - compatible - reg @@ -40,7 +51,7 @@ additionalProperties: false examples: - | syscon@20002000 { - compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mf= d"; reg =3D <0x20002000 0x1000>; #reset-cells =3D <1>; }; --=20 2.51.0 From nobody Sat Feb 7 10:08:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 731A1322A24; Wed, 22 Oct 2025 10:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127835; cv=none; b=SOZvt/gLK7XY/S/o+nU5STkNDNOpjPAOG2z8Nl1B72FnN9KsuTsvfJefpWfc7mYg8FLC+c9HiBaCDq1KLivR6nSynOueG0zlT6Kn1WuoEbyqO2K8cOPvj+Qe20YI6aEm+iWRd3bojuOEhu4q2/j3khh8Co3A1n7ZGKyV+rJu7A8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761127835; c=relaxed/simple; bh=USKbnz/WWtmRAu/WsgpdJwkstKtmlsjlsNtL8jTy6Fw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l+0+MXidQU1dXQmkMv9epbUtda33+XwTU40tW29+ITdxVwcMZfBzrxCQDg4tz4qq7i3e9/tiPmByt316IVRCRjJYOPMabj2+nm+DWWEIqFNQy4Z8UIbUcScTF3MBisKFSexwPPXuRxP3/N40I8JUKCcbnb0BHMjc4EXOznnLiOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RSenboSk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RSenboSk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3361DC113D0; Wed, 22 Oct 2025 10:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761127835; bh=USKbnz/WWtmRAu/WsgpdJwkstKtmlsjlsNtL8jTy6Fw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RSenboSkPXVVBsgZDX0czzmHIXPLI7vF7jgY40p9RdOI9ACB7TKJpqMH7b+tdzLYy DfNJ6asT8p8bEnxU6lzRMpi3Y6DujiwBDbT0ziCfawnw9X4q4JAkJTY7bABuY+TEVU uWgvYQBtfxfTfhB9RI3i+dn+kNvSuaaCaOayrD4qn41iLdz8DDgROpnYEInFzBsWsC 9jkODbxvshmSxyh73638WB6M36afz24JY+6yEp8srfINGdyU5cM0+Zzr4wxsaV5lZy u/uhCIbvN1HQoOeWq4SSF0vFm6/hZuWthkf1Io6p8MHHOSf4/B+2X0a7H32EN6AGV3 aJKnNyZJW5RHA== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v3 4/5] pinctrl: add polarfire soc iomux0 pinmux driver Date: Wed, 22 Oct 2025 11:09:12 +0100 Message-ID: <20251022-cryptic-recede-0968b187fc44@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251022-dash-refinance-ac3387657ae4@spud> References: <20251022-dash-refinance-ac3387657ae4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11389; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=FspkpCwBeD2MbueZeRJsfAuxKRuAcH0xEJ18CVdNA/o=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBk/1kaHLzauXP518QqBx/PShPKlVIQerbhk6PWZNzKuz m9+FaNQRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZiMIOR4e3ZT8u0b9TaHdln f+3EojMzBTgu37IVa+Gy4WdwmJnUsJKRoadiW2vBo/kt6T53l9gd3XN3exnfCefXMm42Gdk7MiR CWQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley On Polarfire SoC, iomux0 is responsible for routing functions to either Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they can either interface with custom RTL or be routed to the FPGA fabric's IOs. Add a driver for it. Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mpfs-iomux0.c | 278 ++++++++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-mpfs-iomux0.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e83fda9bf308..4ec2bb7f67cf 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -505,6 +505,14 @@ config PINCTRL_PISTACHIO help This support pinctrl and GPIO driver for IMG Pistachio SoC. =20 +config PINCTRL_POLARFIRE_SOC + bool "Polarfire SoC pinctrl driver" + depends on ARCH_MICROCHIP || COMPILE_TEST + select GENERIC_PINCONF + default y + help + This selects the pinctrl driver for Microchip Polarfire SoC. + config PINCTRL_RK805 tristate "Pinctrl and GPIO driver for RK805 PMIC" depends on MFD_RK8XX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f33976a6c91b..ea4e890766e1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_PEF2256) +=3D pinctrl-pef2256.o obj-$(CONFIG_PINCTRL_PIC32) +=3D pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PIC64GX) +=3D pinctrl-pic64gx-gpio2.o obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o +obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) +=3D pinctrl-mpfs-iomux0.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RP1) +=3D pinctrl-rp1.o diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctr= l-mpfs-iomux0.c new file mode 100644 index 000000000000..49d9fcec0a16 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" +#include "pinconf.h" +#include "pinmux.h" + +#define MPFS_IOMUX0_REG 0x200 + +struct mpfs_iomux0_pinctrl { + struct pinctrl_dev *pctrl; + struct device *dev; + struct regmap *regmap; + struct pinctrl_desc desc; +}; + +struct mpfs_iomux0_pin_group { + const char *name; + const unsigned int *pins; + u32 mask; + u32 setting; +}; + +struct mpfs_iomux0_function { + const char *name; + const char * const *groups; +}; + +static const struct pinctrl_pin_desc mpfs_iomux0_pins[] =3D { + PINCTRL_PIN(0, "spi0"), + PINCTRL_PIN(1, "spi1"), + PINCTRL_PIN(2, "i2c0"), + PINCTRL_PIN(3, "i2c1"), + PINCTRL_PIN(4, "can0"), + PINCTRL_PIN(5, "can1"), + PINCTRL_PIN(6, "qspi"), + PINCTRL_PIN(7, "uart0"), + PINCTRL_PIN(8, "uart1"), + PINCTRL_PIN(9, "uart2"), + PINCTRL_PIN(10, "uart3"), + PINCTRL_PIN(11, "uart4"), + PINCTRL_PIN(12, "mdio0"), + PINCTRL_PIN(13, "mdio1"), +}; + +static const unsigned int mpfs_iomux0_spi0_pins[] =3D { 0 }; +static const unsigned int mpfs_iomux0_spi1_pins[] =3D { 1 }; +static const unsigned int mpfs_iomux0_i2c0_pins[] =3D { 2 }; +static const unsigned int mpfs_iomux0_i2c1_pins[] =3D { 3 }; +static const unsigned int mpfs_iomux0_can0_pins[] =3D { 4 }; +static const unsigned int mpfs_iomux0_can1_pins[] =3D { 5 }; +static const unsigned int mpfs_iomux0_qspi_pins[] =3D { 6 }; +static const unsigned int mpfs_iomux0_uart0_pins[] =3D { 7 }; +static const unsigned int mpfs_iomux0_uart1_pins[] =3D { 8 }; +static const unsigned int mpfs_iomux0_uart2_pins[] =3D { 9 }; +static const unsigned int mpfs_iomux0_uart3_pins[] =3D { 10 }; +static const unsigned int mpfs_iomux0_uart4_pins[] =3D { 11 }; +static const unsigned int mpfs_iomux0_mdio0_pins[] =3D { 12 }; +static const unsigned int mpfs_iomux0_mdio1_pins[] =3D { 13 }; + +#define MPFS_IOMUX0_GROUP(_name) { \ + .name =3D #_name "_mssio", \ + .pins =3D mpfs_iomux0_##_name##_pins, \ + .mask =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting =3D 0x0, \ +}, { \ + .name =3D #_name "_fabric", \ + .pins =3D mpfs_iomux0_##_name##_pins, \ + .mask =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ + .setting =3D BIT(mpfs_iomux0_##_name##_pins[0]), \ +} + +static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] =3D { + MPFS_IOMUX0_GROUP(spi0), + MPFS_IOMUX0_GROUP(spi1), + MPFS_IOMUX0_GROUP(i2c0), + MPFS_IOMUX0_GROUP(i2c1), + MPFS_IOMUX0_GROUP(can0), + MPFS_IOMUX0_GROUP(can1), + MPFS_IOMUX0_GROUP(qspi), + MPFS_IOMUX0_GROUP(uart0), + MPFS_IOMUX0_GROUP(uart1), + MPFS_IOMUX0_GROUP(uart2), + MPFS_IOMUX0_GROUP(uart3), + MPFS_IOMUX0_GROUP(uart4), + MPFS_IOMUX0_GROUP(mdio0), + MPFS_IOMUX0_GROUP(mdio1), +}; + +static const char * const mpfs_iomux0_spi0_groups[] =3D { "spi0_mssio", "s= pi0_fabric" }; +static const char * const mpfs_iomux0_spi1_groups[] =3D { "spi1_mssio", "s= pi1_fabric" }; +static const char * const mpfs_iomux0_i2c0_groups[] =3D { "i2c0_mssio", "i= 2c0_fabric" }; +static const char * const mpfs_iomux0_i2c1_groups[] =3D { "i2c1_mssio", "i= 2c1_fabric" }; +static const char * const mpfs_iomux0_can0_groups[] =3D { "can0_mssio", "c= an0_fabric" }; +static const char * const mpfs_iomux0_can1_groups[] =3D { "can1_mssio", "c= an1_fabric" }; +static const char * const mpfs_iomux0_qspi_groups[] =3D { "qspi_mssio", "q= spi_fabric" }; +static const char * const mpfs_iomux0_uart0_groups[] =3D { "uart0_mssio", = "uart0_fabric" }; +static const char * const mpfs_iomux0_uart1_groups[] =3D { "uart1_mssio", = "uart1_fabric" }; +static const char * const mpfs_iomux0_uart2_groups[] =3D { "uart2_mssio", = "uart2_fabric" }; +static const char * const mpfs_iomux0_uart3_groups[] =3D { "uart3_mssio", = "uart3_fabric" }; +static const char * const mpfs_iomux0_uart4_groups[] =3D { "uart4_mssio", = "uart4_fabric" }; +static const char * const mpfs_iomux0_mdio0_groups[] =3D { "mdio0_mssio", = "mdio0_fabric" }; +static const char * const mpfs_iomux0_mdio1_groups[] =3D { "mdio1_mssio", = "mdio1_fabric" }; + +#define MPFS_IOMUX0_FUNCTION(_name) { \ + .name =3D #_name, \ + .groups =3D mpfs_iomux0_##_name##_groups, \ +} + +static const struct mpfs_iomux0_function mpfs_iomux0_functions[] =3D { + MPFS_IOMUX0_FUNCTION(spi0), + MPFS_IOMUX0_FUNCTION(spi1), + MPFS_IOMUX0_FUNCTION(i2c0), + MPFS_IOMUX0_FUNCTION(i2c1), + MPFS_IOMUX0_FUNCTION(can0), + MPFS_IOMUX0_FUNCTION(can1), + MPFS_IOMUX0_FUNCTION(qspi), + MPFS_IOMUX0_FUNCTION(uart0), + MPFS_IOMUX0_FUNCTION(uart1), + MPFS_IOMUX0_FUNCTION(uart2), + MPFS_IOMUX0_FUNCTION(uart3), + MPFS_IOMUX0_FUNCTION(uart4), + MPFS_IOMUX0_FUNCTION(mdio0), + MPFS_IOMUX0_FUNCTION(mdio1), +}; + +static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct= seq_file *seq, + unsigned int pin) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + u32 val; + + seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin); + + regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val); + val =3D (val & BIT(pin)) >> pin; + + seq_printf(seq, "val: %x\n", val); +} + +static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_pin_groups); +} + +static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, uns= igned int selector) +{ + return mpfs_iomux0_pin_groups[selector].name; +} + +static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned in= t selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins =3D mpfs_iomux0_pin_groups[selector].pins; + *num_pins =3D 1; + + return 0; +} + +static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops =3D { + .get_groups_count =3D mpfs_iomux0_groups_count, + .get_group_name =3D mpfs_iomux0_group_name, + .get_group_pins =3D mpfs_iomux0_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinctrl_utils_free_map, + .pin_dbg_show =3D mpfs_iomux0_pin_dbg_show, +}; + +static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsig= ned int fsel, + unsigned int gsel) +{ + struct mpfs_iomux0_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctrl_dev); + struct device *dev =3D pctrl->dev; + const struct mpfs_iomux0_pin_group *group; + const struct mpfs_iomux0_function *function; + + group =3D &mpfs_iomux0_pin_groups[gsel]; + function =3D &mpfs_iomux0_functions[fsel]; + + dev_dbg(dev, "Setting func %s mask %x setting %x\n", + function->name, group->mask, group->setting); + regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->se= tting); + + return 0; +} + +static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mpfs_iomux0_functions); +} + +static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pc= tldev, + unsigned int selector) +{ + return mpfs_iomux0_functions[selector].name; +} + +static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsi= gned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D mpfs_iomux0_functions[selector].groups; + *num_groups =3D 2; + + return 0; +} + +static const struct pinmux_ops mpfs_iomux0_pinmux_ops =3D { + .get_functions_count =3D mpfs_iomux0_pinmux_get_funcs_count, + .get_function_name =3D mpfs_iomux0_pinmux_get_func_name, + .get_function_groups =3D mpfs_iomux0_pinmux_get_groups, + .set_mux =3D mpfs_iomux0_pinmux_set_mux, +}; + +static int mpfs_iomux0_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mpfs_iomux0_pinctrl *pctrl; + + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(pctrl->regmap)) + dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap= \n"); + + pctrl->desc.name =3D dev_name(dev); + pctrl->desc.pins =3D mpfs_iomux0_pins; + pctrl->desc.npins =3D ARRAY_SIZE(mpfs_iomux0_pins); + pctrl->desc.pctlops =3D &mpfs_iomux0_pinctrl_ops; + pctrl->desc.pmxops =3D &mpfs_iomux0_pinmux_ops; + pctrl->desc.owner =3D THIS_MODULE; + + pctrl->dev =3D dev; + + platform_set_drvdata(pdev, pctrl); + + pctrl->pctrl =3D devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id mpfs_iomux0_of_match[] =3D { + { .compatible =3D "microchip,mpfs-pinctrl-iomux0" }, + { } +}; +MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match); + +static struct platform_driver mpfs_iomux0_driver =3D { + .driver =3D { + .name =3D "mpfs-pinctrl-iomux0", + .of_match_table =3D mpfs_iomux0_of_match, + }, + .probe =3D mpfs_iomux0_probe, +}; +module_platform_driver(mpfs_iomux0_driver); + +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Sat Feb 7 10:08:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A8493254A4; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H8gNPWJZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 653B8C116B1; Wed, 22 Oct 2025 10:10:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761127837; bh=OUQyFuTsycRdDJyc4s7jio9r2I2Q187UaqN1mLSvjPc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H8gNPWJZQwBKzvcP4FnCj4hHExxhZSd0spquS9jzC8mjck+Ii1bd4jZj6ZyKq6S15 0NnolWXnlgQB3zDO6jUXkQdFuZpCM7uBNA3i15aXr8n3rpLMePClx+GIN1g8MlVZ/z FjnufKVZBMtHmao34aUXg/4jjFYt1ee9LIKLtyBawyyH6rr5iCNaDahHPJnFV48h1P ox2wRhdc3DAEUl+3IT8gKetCO0V+6AJU0Ao35+AFyq+pSN29+jk9m3CoPx0cZOEW2v sR1PqkcAMaITkI+E1LnfvWfyR0IzWtAS6sJCu+IaS/hwL6NDKl6bX8ySzHSuyiP1Pk LlI2vJgCzqonQ== From: Conor Dooley To: linus.walleij@linaro.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Valentina.FernandezAlanis@microchip.com Subject: [PATCH v3 5/5] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry Date: Wed, 22 Oct 2025 11:09:13 +0100 Message-ID: <20251022-bobbed-ladylike-49a4d9b87c54@spud> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251022-dash-refinance-ac3387657ae4@spud> References: <20251022-dash-refinance-ac3387657ae4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1422; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=yIOJ8zWE39Nk9VFv1VjhPf9MABofVWCX3ryvpaofjMU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDBk/1sYsL/hY1fCpf1m70F8fvgcn55x9MO/bXWuV7WXn3 q/bE3ZXuqOUhUGMi0FWTJEl8XZfi9T6Py47nHvewsxhZQIZwsDFKQATUfnA8N9R94/9imv9wY+1 NFoebDKZvc1xxmPTc4tvrns166rLFOX7DP8UNv6I3ei7VU9x/b7+6AKvZMWumJ66v1pceZFMz/f GqfEDAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add the new gpio2 and iomux0 drivers and bindings to the existing entry for Microchip RISC-V devices. Signed-off-by: Conor Dooley --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..5d4825073fcd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22089,6 +22089,8 @@ F: Documentation/devicetree/bindings/gpio/microchip= ,mpfs-gpio.yaml F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0= .yaml +F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpi= o2.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml F: Documentation/devicetree/bindings/riscv/microchip.yaml F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-cont= roller.yaml @@ -22102,6 +22104,8 @@ F: drivers/gpio/gpio-mpfs.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c F: drivers/pci/controller/plda/pcie-microchip-host.c +F: drivers/pinctrl/pinctrl-mpfs-iomux0.c +F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c --=20 2.51.0