From nobody Mon Feb 9 01:46:05 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69ECD32BF59 for ; Tue, 21 Oct 2025 14:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; cv=none; b=DtVjaUzy8GPCA/ECdoXp5uByrcNm8J55jikQUpP0kKjnIu/gZg2kxDkkjSES3QtqW/zkQYioCuuRMORggRKNZYNtU0Cy06hvkcprMSyek7D9BSvhSuGT8v7Gfo2AqY+xkPdg6oHs9OPloQ2Cnju7NE+rHULuPSFpR1/cr/M5Ec4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; c=relaxed/simple; bh=bpGpijdjZAR7OyV2uiqmTwCnTxW/nQi49zgcRxMPFb0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W3gfC3wXWZg/ZiShT0gF/XuhyZod5/N9LDOlczuiH1iKwnQxHkjaI4vESMCk+V/PVNN3kyrJ3K1Fxg+jx8Q1fgZIi2bvbyFam5uZIMlx4GkDePKpv3qw/4Ao4ZUp1GbgVG2mC4ULUGlYk2a4olmYr4bIMMnKtNBKvm6K3X8kJJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=a6AU+z9R; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="a6AU+z9R" Received: from terra.vega.svanheule.net (2a02-1812-162c-8f00-1e2d-b404-3319-eba8.ip6.access.telenet.be [IPv6:2a02:1812:162c:8f00:1e2d:b404:3319:eba8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 5CFF968A1CC; Tue, 21 Oct 2025 16:24:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WeM3dHttDCgxcjOT7kFTiod27po3wdP3a4W2ChFB354=; b=a6AU+z9REHJx9dYxBOXXb1Kp0OmUDm54fZ8We2+iBYlwJN9k7DdpNGrZRtWyzSVV9oI6DW cT4AeLCr2aKs2RpybT0qNVeJiQ7KfUy74mUPrjFcoq9F8Ckb/RcfINJus4J2M65/W/6eel GJPy8q3ZOkBXVgxbrhq3JRiXqjeR7tqRuRn4Ztu5gRgMFId1pOQFgd1ujN3ies5YVX1qOH p2KSRRJBgM0CVYF6kljJ9gC9xPA8EKw9bAUYh55D0slcBwLJR783tPYUo2BxJpRJqtWOSO tZfD+vfJpa+EXeNLHiBi01Ws/jM6iCk72CDTY/vraUIEMmr94AB/DxiD+9jiJA== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 1/8] gpio: regmap: Force writes for aliased data regs Date: Tue, 21 Oct 2025 16:23:56 +0200 Message-ID: <20251021142407.307753-2-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GPIO chips often have data input and output fields aliased to the same offset. Since gpio-regmap performs a value update before the direction update (to prevent glitches), a pin currently configured as input may cause regmap_update_bits() to not perform a write. This may cause unexpected line states when the current input state equals the requested output state: OUT IN OUT DIR ''''''\...|.../'''''' pin ....../'''|'''\...... (1) (2) (3) 1. Line was configurad as out-low, but is reconfigured to input. External logic results in high value. 2. Set output value high. regmap_update_bits() sees the value is already high and discards the register write. 3. Line is switched to output, maintaining the stale output config (low) instead of the requested config (high). By switching to regmap_write_bits(), a write of the requested output value can be forced, irrespective of the read state. Do this only for aliased registers, so the more efficient regmap_update_bits() can still be used for distinct registers. Signed-off-by: Sander Vanheule Reviewed-by: Michael Walle --- drivers/gpio/gpio-regmap.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index ab9e4077fa60..ba3c19206ccf 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -93,7 +93,7 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsign= ed int offset, { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); unsigned int base =3D gpio_regmap_addr(gpio->reg_set_base); - unsigned int reg, mask; + unsigned int reg, mask, mask_val; int ret; =20 ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); @@ -101,9 +101,15 @@ static int gpio_regmap_set(struct gpio_chip *chip, uns= igned int offset, return ret; =20 if (val) - ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask); + mask_val =3D mask; else - ret =3D regmap_update_bits(gpio->regmap, reg, mask, 0); + mask_val =3D 0; + + /* ignore input values which shadow the old output value */ + if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) + ret =3D regmap_write_bits(gpio->regmap, reg, mask, mask_val); + else + ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask_val); =20 return ret; } --=20 2.51.0