From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69ECD32BF59 for ; Tue, 21 Oct 2025 14:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; cv=none; b=DtVjaUzy8GPCA/ECdoXp5uByrcNm8J55jikQUpP0kKjnIu/gZg2kxDkkjSES3QtqW/zkQYioCuuRMORggRKNZYNtU0Cy06hvkcprMSyek7D9BSvhSuGT8v7Gfo2AqY+xkPdg6oHs9OPloQ2Cnju7NE+rHULuPSFpR1/cr/M5Ec4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; c=relaxed/simple; bh=bpGpijdjZAR7OyV2uiqmTwCnTxW/nQi49zgcRxMPFb0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W3gfC3wXWZg/ZiShT0gF/XuhyZod5/N9LDOlczuiH1iKwnQxHkjaI4vESMCk+V/PVNN3kyrJ3K1Fxg+jx8Q1fgZIi2bvbyFam5uZIMlx4GkDePKpv3qw/4Ao4ZUp1GbgVG2mC4ULUGlYk2a4olmYr4bIMMnKtNBKvm6K3X8kJJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=a6AU+z9R; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="a6AU+z9R" Received: from terra.vega.svanheule.net (2a02-1812-162c-8f00-1e2d-b404-3319-eba8.ip6.access.telenet.be [IPv6:2a02:1812:162c:8f00:1e2d:b404:3319:eba8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 5CFF968A1CC; Tue, 21 Oct 2025 16:24:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WeM3dHttDCgxcjOT7kFTiod27po3wdP3a4W2ChFB354=; b=a6AU+z9REHJx9dYxBOXXb1Kp0OmUDm54fZ8We2+iBYlwJN9k7DdpNGrZRtWyzSVV9oI6DW cT4AeLCr2aKs2RpybT0qNVeJiQ7KfUy74mUPrjFcoq9F8Ckb/RcfINJus4J2M65/W/6eel GJPy8q3ZOkBXVgxbrhq3JRiXqjeR7tqRuRn4Ztu5gRgMFId1pOQFgd1ujN3ies5YVX1qOH p2KSRRJBgM0CVYF6kljJ9gC9xPA8EKw9bAUYh55D0slcBwLJR783tPYUo2BxJpRJqtWOSO tZfD+vfJpa+EXeNLHiBi01Ws/jM6iCk72CDTY/vraUIEMmr94AB/DxiD+9jiJA== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 1/8] gpio: regmap: Force writes for aliased data regs Date: Tue, 21 Oct 2025 16:23:56 +0200 Message-ID: <20251021142407.307753-2-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GPIO chips often have data input and output fields aliased to the same offset. Since gpio-regmap performs a value update before the direction update (to prevent glitches), a pin currently configured as input may cause regmap_update_bits() to not perform a write. This may cause unexpected line states when the current input state equals the requested output state: OUT IN OUT DIR ''''''\...|.../'''''' pin ....../'''|'''\...... (1) (2) (3) 1. Line was configurad as out-low, but is reconfigured to input. External logic results in high value. 2. Set output value high. regmap_update_bits() sees the value is already high and discards the register write. 3. Line is switched to output, maintaining the stale output config (low) instead of the requested config (high). By switching to regmap_write_bits(), a write of the requested output value can be forced, irrespective of the read state. Do this only for aliased registers, so the more efficient regmap_update_bits() can still be used for distinct registers. Signed-off-by: Sander Vanheule Reviewed-by: Michael Walle --- drivers/gpio/gpio-regmap.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index ab9e4077fa60..ba3c19206ccf 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -93,7 +93,7 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsign= ed int offset, { struct gpio_regmap *gpio =3D gpiochip_get_data(chip); unsigned int base =3D gpio_regmap_addr(gpio->reg_set_base); - unsigned int reg, mask; + unsigned int reg, mask, mask_val; int ret; =20 ret =3D gpio->reg_mask_xlate(gpio, base, offset, ®, &mask); @@ -101,9 +101,15 @@ static int gpio_regmap_set(struct gpio_chip *chip, uns= igned int offset, return ret; =20 if (val) - ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask); + mask_val =3D mask; else - ret =3D regmap_update_bits(gpio->regmap, reg, mask, 0); + mask_val =3D 0; + + /* ignore input values which shadow the old output value */ + if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) + ret =3D regmap_write_bits(gpio->regmap, reg, mask, mask_val); + else + ret =3D regmap_update_bits(gpio->regmap, reg, mask, mask_val); =20 return ret; } --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA419336EFF for ; Tue, 21 Oct 2025 14:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; cv=none; b=RxRr/Kg4mKW6OyGksNzr1scVVxuPGagw9nQb/bv+yU7ThkccSXdWAjgf9SQ/O/QDl0BF5NUa20C7M+UrqixIVU3GbAmjxanOpWLGF5LJvSrzdcPjBvy+oRPdGjN4SLrlAF3Gvl4CpIFhjSvMSA7BN7lnBmN0rPcJvDCO3HvlZuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056675; c=relaxed/simple; bh=mjMBW4Sxdy9jvKWjdvZDhiiRV/EN4mkroKkKBROPKjY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Tue, 21 Oct 2025 16:24:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056672; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YBL7rt7cVDLBdD6u/8R0OUTQE737shBf+U6nao7w184=; b=5reUCzt3wSy96XoodKBWfC6xC9UwIIZZXqmwANXGxCdEu0yUn7A3EJ84Djpd6pvmB/U787 vWlhxoVtLu/zwa7JWau3KnrLYOPgDIgWWb544H1FKwWkM+PgEahNk9jxBvqPLTSbk2vt7A jA6lpF9BKdvh87g6gsn+chQkQFt1dc6wcxHUhzNqMClHljHp8wcaQIqbVUyqGH7ytwUsnC hCVSLnR8gXhqtmAgkeyxA5aCB+sy6wmzZJ5fXVoUMKYpIuZ3LrwnVpDDD6aYYT+qu50wNa oz9z6gs78cNoa0YAwWU+0fAz7oXOKMfb/ka98J+KXaxzMVJN1uBiBWwGXQfKRA== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 2/8] gpio: regmap: Bypass cache for aliased inputs Date: Tue, 21 Oct 2025 16:23:57 +0200 Message-ID: <20251021142407.307753-3-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GPIO chips often have data input and output registers aliased to the same offset. The output register is non-valitile and could in theory be cached. The input register however is volatile by nature and hence should not be cached, resulting in different requirements for reads and writes. The generic gpio chip implementation stores a shadow value of the pin output data, which is updated and written to hardware on output data changes in bgpio_set(), bgpio_set_set(). Pin input values are always obtained by reading the aliased data register from hardware. For gpio-regmap the situation is more complex as the output data could be in multiple registers, but we can use the regmap cache to shadow the output values when marking the data registers as non-volatile. By using regmap_read_bypassed() we can still treat the input values as volatile, irrespective of the regmap config. This ensures proper functioning of writing the output register with regmap_write_bits(), which will then use and update the cache only on data writes, gaining some performance from the cached output values. Signed-off-by: Sander Vanheule Reviewed-by: Linus Walleij Reviewed-by: Michael Walle -- Changes since RFC: - Add review tags - Slightly reworded the commit message --- drivers/gpio/gpio-regmap.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index ba3c19206ccf..afecacf7607f 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -81,7 +81,11 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsig= ned int offset) if (ret) return ret; =20 - ret =3D regmap_read(gpio->regmap, reg, &val); + /* ensure we don't spoil any register cache with pin input values */ + if (gpio->reg_dat_base =3D=3D gpio->reg_set_base) + ret =3D regmap_read_bypassed(gpio->regmap, reg, &val); + else + ret =3D regmap_read(gpio->regmap, reg, &val); if (ret) return ret; =20 --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46D663385BD for ; Tue, 21 Oct 2025 14:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056676; cv=none; b=dQf+v29NiVRcSL9cSNK/nZDXkJwhlbNPCcZ1GQXWHJkF2GAzwn/a8foQ+YCkIa7659kmScq8xV7hKzJzolveTGfPXOEHffjHZUCz0ddYR+zgb86q3U3KWFxQXcdxLN3HD4r9Z6ejgnf6IoAGASwDPOGPoqkmsPJtB3ayd+tYTck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056676; c=relaxed/simple; bh=ucYzVCWE51NmFx2/BwEBPsUCDxyYgQuvoNjfPTOejAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H55zkdwpL24syDgo0LYpPOVLJEXLjqmWrhK5YbiEjzIV3NmcF38zvUnfjG3J+3zjemg7Pk6OpiBw6Bs2dSzT5UUecFF0hrHAk5hSIPYx1mtryTdEMqpEocok0TiDwTuJyl2sQ22V6vCXmTfOFmyU3KiBp6ySqi25qD3WYynnNsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=F+zhHnzn; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="F+zhHnzn" Received: from terra.vega.svanheule.net (2a02-1812-162c-8f00-1e2d-b404-3319-eba8.ip6.access.telenet.be [IPv6:2a02:1812:162c:8f00:1e2d:b404:3319:eba8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 3A9C168A1CE; Tue, 21 Oct 2025 16:24:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056672; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6urXFWKajG7kcvFel7TUKdKt+O2PPPG68C70YJSu5js=; b=F+zhHnzncWlcMdVdICpMKjG7HOxTgcKwkRwP1k9bJTl5+mXURjl9b+wZ8kB6bBad+2x3gz ydP7XyI3LiVSODo1BhgLzddF4Gj9ya7x6BXvL5mJTQRYxN+G1Fhf6iW6ko0ZHnytfTzrAk aEruKRZK+o5hVZE7QPY2868adoGPFANpqp0gcpAuNKIRJnNs1Uk73vBoj1+UcnK8pQHJiC 1/RgmkBPntkfUCQ3ZzNV7B6OQh7hzUvemRkgwd7q6lTzVZ5LDwRvgl/eM/60UCNHZWicQi fQzEyXgTAwsVjaqHQAwnuB4WSG+wItrFQFPybhgMvNO0KxPzmjk78bibsXGiIQ== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 3/8] dt-bindings: leds: Binding for RTL8231 scan matrix Date: Tue, 21 Oct 2025 16:23:58 +0200 Message-ID: <20251021142407.307753-4-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add a binding description for the Realtek RTL8231's LED support, which consists of up to 88 LEDs arranged in a number of scanning matrices. Signed-off-by: Sander Vanheule --- .../bindings/leds/realtek,rtl8231-leds.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/realtek,rtl8231-= leds.yaml diff --git a/Documentation/devicetree/bindings/leds/realtek,rtl8231-leds.ya= ml b/Documentation/devicetree/bindings/leds/realtek,rtl8231-leds.yaml new file mode 100644 index 000000000000..54e8593f8c06 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/realtek,rtl8231-leds.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/realtek,rtl8231-leds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL8231 LED scan matrix. + +maintainers: + - Sander Vanheule + +description: | + The RTL8231 has support for driving a number of LED matrices, by scanning + over the LEDs pins, alternatingly lighting different columns and/or rows. + + This functionality is available on an RTL8231, when it is configured for= use + as an MDIO device, or SMI device. + + In single color scan mode, 88 LEDs are supported. These are grouped into + three output matrices: + - Group A of 6=C3=976 single color LEDs. Rows and columns are driven b= y GPIO + pins 0-11. + L0[n] L1[n] L2[n] L0[n+6] L1[n+6] L2[n+6] + | | | | | | + P0/P6 --<--------<--------<--------<--------<--------< (3) + | | | | | | + P1/P7 --<--------<--------<--------<--------<--------< (4) + | | | | | | + P2/P8 --<--------<--------<--------<--------<--------< (5) + | | | | | | + P3/P9 --<--------<--------<--------<--------<--------< (6) + | | | | | | + P4/P10 --<--------<--------<--------<--------<--------< (7) + | | | | | | + P5/P11 --<--------<--------<--------<--------<--------< (8) + (0) (1) (2) (9) (10) (11) + - Group B of 6=C3=976 single color LEDs. Rows and columns are driven b= y GPIO + pins 12-23. + L0[n] L1[n] L2[n] L0[n+6] L1[n+6] L2[n+6] + | | | | | | + P12/P18 --<--------<--------<--------<--------<--------< (15) + | | | | | | + P13/P19 --<--------<--------<--------<--------<--------< (16) + | | | | | | + P14/P20 --<--------<--------<--------<--------<--------< (17) + | | | | | | + P15/P21 --<--------<--------<--------<--------<--------< (18) + | | | | | | + P16/P22 --<--------<--------<--------<--------<--------< (19) + | | | | | | + P17/P23 --<--------<--------<--------<--------<--------< (20) + (12) (13) (14) (21) (22) (23) + - Group C of 8 pairs of anti-parallel (or bi-color) LEDs. LED selectio= n is + provided by GPIO pins 24-27 and 29-32, polarity selection by GPIO 28. + P24 P25 ... P30 P31 + | | | | + LED POL --X-------X---/\/---X-------X (28) + (24) (25) ... (31) (32) + + In bi-color scan mode, 72 LEDs are supported. These are grouped into four + output matrices: + - Group A of 12 pairs of anti-parallel LEDs. LED selection is provided + by GPIO pins 0-11, polarity selection by GPIO 12. + - Group B of 6 pairs of anti-parallel LEDs. LED selection is provided + by GPIO pins 23-28, polarity selection by GPIO 21. + - Group C of 6 pairs of anti-parallel LEDs. LED selection is provided + by GPIO pins 29-34, polarity selection by GPIO 22. + - Group of 4=C3=976 single color LEDs. Rows are driven by GPIO pins 15= -20, + columns by GPIO pins 13-14 and 21-22 (shared with groups B and C). + L2[n] L2[n+6] L2[n+12] L2[n+18] + | | | | + +0 --<--------<---------<---------< (15) + | | | | + +1 --<--------<---------<---------< (16) + | | | | + +2 --<--------<---------<---------< (17) + | | | | + +3 --<--------<---------<---------< (18) + | | | | + +4 --<--------<---------<---------< (19) + | | | | + +6 --<--------<---------<---------< (20) + (13) (14) (21) (22) + + This node must always be a child of a 'realtek,rtl8231' node. + +properties: + $nodename: + const: led-controller + + compatible: + const: realtek,rtl8231-leds + + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + realtek,led-scan-mode: + $ref: /schemas/types.yaml#/definitions/string + description: | + Specify the scanning mode the chip should run in. See general descri= ption + for how the scanning matrices are wired up. + enum: [single-color, bi-color] + +patternProperties: + "^led@": + description: | + LEDs are addressed by their port index and led index. Ports 0-23 alw= ays + support three LEDs. Additionally, but only when used in single color= scan + mode, ports 24-31 support two LEDs. + type: object + + properties: + reg: + items: + - items: + - description: port index + maximum: 31 + - description: led index + maximum: 2 + + allOf: + - $ref: ../leds/common.yaml# + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + - realtek,led-scan-mode + +additionalProperties: false + +examples: + - | + #include + led-controller { + compatible =3D "realtek,rtl8231-leds"; + #address-cells =3D <2>; + #size-cells =3D <0>; + + realtek,led-scan-mode =3D "single-color"; + + led@0,0 { + reg =3D <0 0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + }; + + led@0,1 { + reg =3D <0 1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + }; + + led@0,2 { + reg =3D <0 2>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + }; + }; --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4008A339B5F for ; Tue, 21 Oct 2025 14:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056677; cv=none; b=lrDzfMoLHbXNVecmMNLv16/FNtiZkphvWCaZYLzyQ9tpclqydylCGIHcAJJ0cPpAXPnz/sqM+k67VTzQpc3gen61P8PWkr2TYUJw56v2poDTDDcKmTjYVpv+4RoMdJwIk0r0JAYLmf4xJqi0+ZPH7PuiVbLLjon+QSBrZwhvSNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056677; c=relaxed/simple; bh=4kgPjhejE638xsnJLHUTspe2ww25YGHD2oc94/jTMJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E+DOR1HL3z45bGBgFbtizca6vEJC3hqQ3y50Ae4h4TXF9QrFEXIWHgeq3zgehHYYIhw1SUjSM/fH7BqFot5mur0uo59ehCeN4Iam/AY0RcG8KailVJ8I3KwXjS5u9svj4X1J4DW3kHJ92vlQuCZBaIGUYbjShdZ6mUbdhk8PBm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net; spf=pass smtp.mailfrom=svanheule.net; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b=9v2hwmEO; arc=none smtp.client-ip=84.16.241.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=svanheule.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=svanheule.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=svanheule.net header.i=@svanheule.net header.b="9v2hwmEO" Received: from terra.vega.svanheule.net (2a02-1812-162c-8f00-1e2d-b404-3319-eba8.ip6.access.telenet.be [IPv6:2a02:1812:162c:8f00:1e2d:b404:3319:eba8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id B15F168A1CF; Tue, 21 Oct 2025 16:24:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056673; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SWCzc9suvc+MIRi8yExM5Q2XTScDHfdPzlpR2UwQaEw=; b=9v2hwmEOhhMdm9EjJCEkjmp9zvHWGG67mMEqZKnterI1VFh/ecYUHrFIvexCZ88f/IiKXb W83ii9++ZnpBsDUeVSTp1VlFSrlOlJPfxp2lTdY89xn6L7zhfjZ7dWBqQyLUxgjfUazmcT KtX2pd5SusyH+ulm3g0opPgDEJ6p5hDg5QfEafee/nsIEcRpR5bU6TioLs/RMB10qVp5B1 FAcRPGUY1hIdm/PFhAGwODnD/xIdoWYhVq3WMYUC5UJfUFLO7Ds8CasmRjmetWoNUscXcV 6nc9ZaxzTl+oiT2SgQgfzmIqW8I4Vy1Njs0ksmUo0Ji6QPUt6F2tmKQWo443Vw== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 4/8] dt-bindings: mfd: Binding for RTL8231 Date: Tue, 21 Oct 2025 16:23:59 +0200 Message-ID: <20251021142407.307753-5-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a binding description for the Realtek RTL8231, a GPIO and LED expander chip commonly used in ethernet switches based on a Realtek switch SoC. These chips can be addressed via an MDIO or SMI bus, or used as a plain 36-bit shift register. This binding only describes the feature set provided by the MDIO/SMI configuration, and covers the GPIO, PWM, and pin control properties. The LED properties are defined in a separate binding. Signed-off-by: Sander Vanheule --- .../bindings/mfd/realtek,rtl8231.yaml | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/realtek,rtl8231.y= aml diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml b/D= ocumentation/devicetree/bindings/mfd/realtek,rtl8231.yaml new file mode 100644 index 000000000000..25135917d3f2 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/realtek,rtl8231.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL8231 GPIO and LED expander. + +maintainers: + - Sander Vanheule + +description: | + The RTL8231 is a GPIO and LED expander chip, providing up to 37 GPIOs, u= p to + 88 LEDs, and up to one PWM output. This device is frequently used alongs= ide + Realtek switch SoCs, to provide additional I/O capabilities. + + To manage the RTL8231's features, its strapping pins can be used to conf= igure + it in one of three modes: shift register, MDIO device, or SMI device. The + shift register mode does not need special support. In MDIO or SMI mode, = most + pins can be configured as a GPIO output or LED matrix scan line/column. = One + pin can be used as PWM output. + + The GPIO, PWM, and pin control are part of the main node. LED support is + configured as a sub-node. + +properties: + compatible: + const: realtek,rtl8231 + + reg: + description: MDIO or SMI device address. + maxItems: 1 + + # GPIO support + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is the pin number and the second cell is used to spec= ify + the GPIO active state. + + gpio-ranges: + description: | + Must reference itself, and provide a zero-based mapping for 37 pins. + maxItems: 1 + + # Pin muxing and configuration + drive-strength: + description: | + Common drive strength used for all GPIO output pins, must be 4mA or = 8mA. + On reset, this value will default to 8mA. + enum: [4, 8] + + # LED scanning matrix + led-controller: + $ref: ../leds/realtek,rtl8231-leds.yaml# + + # PWM output + "#pwm-cells": + description: | + Twos cells with PWM index (must be 0) and PWM frequency in Hz. To use + the PWM output, gpio35 must be muxed to its 'pwm' function. Valid + frequency values for consumers are 1200, 1600, 2000, 2400, 2800, 320= 0, + 4000, and 4800. + const: 2 + +patternProperties: + "-pins$": + type: object + $ref: ../pinctrl/pinmux-node.yaml# + + properties: + pins: + items: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpi= o15, + gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, g= pio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, g= pio31, + gpio32, gpio33, gpio34, gpio35, gpio36] + minItems: 1 + maxItems: 37 + function: + description: | + Select which function to use. "gpio" is supported for all pins, = "led" is supported + for pins 0-34, "pwm" is supported for pin 35. + enum: [gpio, led, pwm] + + required: + - pins + - function + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + // Minimal example + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + expander0: expander@0 { + compatible =3D "realtek,rtl8231"; + reg =3D <0>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&expander0 0 0 37>; + }; + }; + - | + // All bells and whistles included + #include + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + expander1: expander@1 { + compatible =3D "realtek,rtl8231"; + reg =3D <1>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&expander1 0 0 37>; + + #pwm-cells =3D <2>; + + drive-strength =3D <4>; + + button-pins { + pins =3D "gpio36"; + function =3D "gpio"; + input-debounce =3D <100000>; + }; + + pwm-pins { + pins =3D "gpio35"; + function =3D "pwm"; + }; + + led-pins { + pins =3D "gpio0", "gpio1", "gpio3", "gpio4"; + function =3D "led"; + }; + + led-controller { + compatible =3D "realtek,rtl8231-leds"; + #address-cells =3D <2>; + #size-cells =3D <0>; + + realtek,led-scan-mode =3D "single-color"; + + led@0,0 { + reg =3D <0 0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + }; + + led@0,1 { + reg =3D <0 1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + }; + + led@1,0 { + reg =3D <1 0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + }; + + led@1,1 { + reg =3D <1 1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + }; + }; + }; + }; --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EF1933C504 for ; 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bh=oX3xu74JavTeHeufry9oqW2UCGbaS+twS6lg3QCcc/c=; b=opoCB//YH8FLw6HFlk32scFSAjvzJUqZ0fwYpyOEJdmAGaMENIWm76saM8NU+ZxLhuAZm1 STI6MJqoZT8r10UQem5DIcAks8EmHx0ilAmbpreJ5uxChPKCBm95PaoipGt6uCAQ9uML+l 8HdqGlnnff8v4J9M/7e6YOiKSucmd8VNvG6Tw6vwaFgrR3dmGmZlkrXgH3sU7ar/QHgYzf tSoZKY3cAAuIiEgMkZTShfm5zG1InDs7Tft5VkfJo1aM2AigC0N2BOrMCC/3UZasel9BAV VedTfniMoxUCSMU8BQVDnnLL4KPArg+J7ERKvqWpwvzzSFjvyojbHNYKFGBHVw== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 5/8] mfd: Add RTL8231 core device Date: Tue, 21 Oct 2025 16:24:00 +0200 Message-ID: <20251021142407.307753-6-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RTL8231 is implemented as an MDIO device, and provides a regmap interface for register access by the core and child devices. The chip can also be a device on an SMI bus, an I2C-like bus by Realtek. Since kernel support for SMI is limited, and no real-world SMI implementations have been encountered for this device, this is currently unimplemented. The use of the regmap interface should make any future support relatively straightforward. After a soft reset, all pins are muxed to GPIO inputs before the pin drivers are enabled. This is done to prevent accidental system resets, when a pin is connected to the main SoC's reset line. Signed-off-by: Sander Vanheule --- drivers/mfd/Kconfig | 9 ++ drivers/mfd/Makefile | 1 + drivers/mfd/rtl8231.c | 193 ++++++++++++++++++++++++++++++++++++ include/linux/mfd/rtl8231.h | 71 +++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 drivers/mfd/rtl8231.c create mode 100644 include/linux/mfd/rtl8231.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6cec1858947b..e13e2df63fee 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1301,6 +1301,15 @@ config MFD_RDC321X southbridge which provides access to GPIOs and Watchdog using the southbridge PCI device configuration space. =20 +config MFD_RTL8231 + tristate "Realtek RTL8231 GPIO and LED expander" + select MFD_CORE + select REGMAP_MDIO + help + Support for the Realtek RTL8231 GPIO and LED expander. + Provides up to 37 GPIOs, 88 LEDs, and one PWM output. + When built as a module, this module will be named rtl8231. + config MFD_RT4831 tristate "Richtek RT4831 four channel WLED and Display Bias Voltage" depends on I2C diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 865e9f12faff..ba973382a20f 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -252,6 +252,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC) +=3D hi6421-pmic-core.o obj-$(CONFIG_MFD_HI6421_SPMI) +=3D hi6421-spmi-pmic.o obj-$(CONFIG_MFD_HI655X_PMIC) +=3D hi655x-pmic.o obj-$(CONFIG_MFD_DLN2) +=3D dln2.o +obj-$(CONFIG_MFD_RTL8231) +=3D rtl8231.o obj-$(CONFIG_MFD_RT4831) +=3D rt4831.o obj-$(CONFIG_MFD_RT5033) +=3D rt5033.o obj-$(CONFIG_MFD_RT5120) +=3D rt5120.o diff --git a/drivers/mfd/rtl8231.c b/drivers/mfd/rtl8231.c new file mode 100644 index 000000000000..60d4a0feea5c --- /dev/null +++ b/drivers/mfd/rtl8231.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static bool rtl8231_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + /* + * Registers with self-clearing bits, strapping pin values. + * Don't mark the data registers as volatile, since we need + * caching for the output values. + */ + case RTL8231_REG_FUNC0: + case RTL8231_REG_FUNC1: + case RTL8231_REG_PIN_HI_CFG: + case RTL8231_REG_LED_END: + return true; + default: + return false; + } +} + +static const struct reg_field RTL8231_FIELD_LED_START =3D REG_FIELD(RTL823= 1_REG_FUNC0, 1, 1); + +static const struct mfd_cell rtl8231_cells[] =3D { + { + .name =3D "rtl8231-pinctrl", + }, + { + .name =3D "rtl8231-leds", + .of_compatible =3D "realtek,rtl8231-leds", + }, +}; + +static int rtl8231_soft_reset(struct regmap *map) +{ + const unsigned int all_pins_mask =3D GENMASK(RTL8231_BITS_VAL - 1, 0); + unsigned int val; + int err; + + /* SOFT_RESET bit self-clears when done */ + regmap_write_bits(map, RTL8231_REG_PIN_HI_CFG, + RTL8231_PIN_HI_CFG_SOFT_RESET, RTL8231_PIN_HI_CFG_SOFT_RESET); + err =3D regmap_read_poll_timeout(map, RTL8231_REG_PIN_HI_CFG, val, + !(val & RTL8231_PIN_HI_CFG_SOFT_RESET), 50, 1000); + if (err) + return err; + + regcache_mark_dirty(map); + + /* + * Chip reset results in a pin configuration that is a mix of LED and GPI= O outputs. + * Select GPI functionality for all pins before enabling pin outputs. + */ + regmap_write(map, RTL8231_REG_PIN_MODE0, all_pins_mask); + regmap_write(map, RTL8231_REG_GPIO_DIR0, all_pins_mask); + regmap_write(map, RTL8231_REG_PIN_MODE1, all_pins_mask); + regmap_write(map, RTL8231_REG_GPIO_DIR1, all_pins_mask); + regmap_write(map, RTL8231_REG_PIN_HI_CFG, + RTL8231_PIN_HI_CFG_MODE_MASK | RTL8231_PIN_HI_CFG_DIR_MASK); + + return 0; +} + +static int rtl8231_init(struct device *dev, struct regmap *map) +{ + struct regmap_field *led_start; + unsigned int started; + unsigned int val; + int err; + + err =3D regmap_read(map, RTL8231_REG_FUNC1, &val); + if (err) { + dev_err(dev, "failed to read READY_CODE\n"); + return err; + } + + val =3D FIELD_GET(RTL8231_FUNC1_READY_CODE_MASK, val); + if (val !=3D RTL8231_FUNC1_READY_CODE_VALUE) { + dev_err(dev, "RTL8231 not present or ready 0x%x !=3D 0x%x\n", + val, RTL8231_FUNC1_READY_CODE_VALUE); + return -ENODEV; + } + + led_start =3D dev_get_drvdata(dev); + err =3D regmap_field_read(led_start, &started); + if (err) + return err; + + if (!started) { + err =3D rtl8231_soft_reset(map); + if (err) + return err; + /* LED_START enables power to output pins, and starts the LED engine */ + err =3D regmap_field_force_write(led_start, 1); + } + + return err; +} + +static const struct regmap_config rtl8231_mdio_regmap_config =3D { + .val_bits =3D RTL8231_BITS_VAL, + .reg_bits =3D RTL8231_BITS_REG, + .volatile_reg =3D rtl8231_volatile_reg, + .max_register =3D RTL8231_REG_COUNT - 1, + .use_single_read =3D true, + .use_single_write =3D true, + .reg_format_endian =3D REGMAP_ENDIAN_BIG, + .val_format_endian =3D REGMAP_ENDIAN_BIG, + /* Cannot use REGCACHE_FLAT because it's not smart enough about cache inv= alidation */ + .cache_type =3D REGCACHE_MAPLE, +}; + +static int rtl8231_mdio_probe(struct mdio_device *mdiodev) +{ + struct device *dev =3D &mdiodev->dev; + struct regmap_field *led_start; + struct regmap *map; + int err; + + map =3D devm_regmap_init_mdio(mdiodev, &rtl8231_mdio_regmap_config); + if (IS_ERR(map)) { + dev_err(dev, "failed to init regmap\n"); + return PTR_ERR(map); + } + + led_start =3D devm_regmap_field_alloc(dev, map, RTL8231_FIELD_LED_START); + if (IS_ERR(led_start)) + return PTR_ERR(led_start); + + dev_set_drvdata(dev, led_start); + + mdiodev->reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_L= OW); + if (IS_ERR(mdiodev->reset_gpio)) + return PTR_ERR(mdiodev->reset_gpio); + + device_property_read_u32(dev, "reset-assert-delay", &mdiodev->reset_asser= t_delay); + device_property_read_u32(dev, "reset-deassert-delay", &mdiodev->reset_dea= ssert_delay); + + err =3D rtl8231_init(dev, map); + if (err) + return err; + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, rtl8231_cells, + ARRAY_SIZE(rtl8231_cells), NULL, 0, NULL); +} + +__maybe_unused static int rtl8231_suspend(struct device *dev) +{ + struct regmap_field *led_start =3D dev_get_drvdata(dev); + + return regmap_field_force_write(led_start, 0); +} + +__maybe_unused static int rtl8231_resume(struct device *dev) +{ + struct regmap_field *led_start =3D dev_get_drvdata(dev); + + return regmap_field_force_write(led_start, 1); +} + +static SIMPLE_DEV_PM_OPS(rtl8231_pm_ops, rtl8231_suspend, rtl8231_resume); + +static const struct of_device_id rtl8231_of_match[] =3D { + { .compatible =3D "realtek,rtl8231" }, + {} +}; +MODULE_DEVICE_TABLE(of, rtl8231_of_match); + +static struct mdio_driver rtl8231_mdio_driver =3D { + .mdiodrv.driver =3D { + .name =3D "rtl8231-expander", + .of_match_table =3D rtl8231_of_match, + .pm =3D pm_ptr(&rtl8231_pm_ops), + }, + .probe =3D rtl8231_mdio_probe, +}; +mdio_module_driver(rtl8231_mdio_driver); + +MODULE_AUTHOR("Sander Vanheule "); +MODULE_DESCRIPTION("Realtek RTL8231 GPIO and LED expander"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/rtl8231.h b/include/linux/mfd/rtl8231.h new file mode 100644 index 000000000000..003eda3797a3 --- /dev/null +++ b/include/linux/mfd/rtl8231.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions the RTL8231 GPIO and LED expander chip + */ + +#ifndef __LINUX_MFD_RTL8231_H +#define __LINUX_MFD_RTL8231_H + +#include + +/* + * Registers addresses are 5 bit, values are 16 bit + * Also define a duplicated range of virtual addresses, to enable + * different read/write behaviour on the GPIO data registers + */ +#define RTL8231_BITS_VAL 16 +#define RTL8231_BITS_REG 5 + +/* Chip control */ +#define RTL8231_REG_FUNC0 0x00 +#define RTL8231_FUNC0_SCAN_MODE BIT(0) +#define RTL8231_FUNC0_SCAN_SINGLE 0 +#define RTL8231_FUNC0_SCAN_BICOLOR BIT(0) + +#define RTL8231_REG_FUNC1 0x01 +#define RTL8231_FUNC1_READY_CODE_VALUE 0x37 +#define RTL8231_FUNC1_READY_CODE_MASK GENMASK(9, 4) +#define RTL8231_FUNC1_DEBOUNCE_MASK GENMASK(15, 10) + +/* Pin control */ +#define RTL8231_REG_PIN_MODE0 0x02 +#define RTL8231_REG_PIN_MODE1 0x03 + +#define RTL8231_PIN_MODE_LED 0 +#define RTL8231_PIN_MODE_GPIO 1 + +/* Pin high config: pin and GPIO control for pins 32-26 */ +#define RTL8231_REG_PIN_HI_CFG 0x04 +#define RTL8231_PIN_HI_CFG_MODE_MASK GENMASK(4, 0) +#define RTL8231_PIN_HI_CFG_DIR_MASK GENMASK(9, 5) +#define RTL8231_PIN_HI_CFG_INV_MASK GENMASK(14, 10) +#define RTL8231_PIN_HI_CFG_SOFT_RESET BIT(15) + +/* GPIO control registers */ +#define RTL8231_REG_GPIO_DIR0 0x05 +#define RTL8231_REG_GPIO_DIR1 0x06 +#define RTL8231_REG_GPIO_INVERT0 0x07 +#define RTL8231_REG_GPIO_INVERT1 0x08 + +#define RTL8231_GPIO_DIR_IN 1 +#define RTL8231_GPIO_DIR_OUT 0 + +/* + * GPIO data registers + * Only the output data can be written to these registers, and only the in= put + * data can be read. + */ +#define RTL8231_REG_GPIO_DATA0 0x1c +#define RTL8231_REG_GPIO_DATA1 0x1d +#define RTL8231_REG_GPIO_DATA2 0x1e +#define RTL8231_PIN_HI_DATA_MASK GENMASK(4, 0) + +/* LED control base registers */ +#define RTL8231_REG_LED0_BASE 0x09 +#define RTL8231_REG_LED1_BASE 0x10 +#define RTL8231_REG_LED2_BASE 0x17 +#define RTL8231_REG_LED_END 0x1b + +#define RTL8231_REG_COUNT 0x1f + +#endif /* __LINUX_MFD_RTL8231_H */ --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B486F33C53E for ; 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bh=OLSr/MY5EaUsOMNq6fEoM/rtAZz4+5R/mn5dXqSjfmU=; b=zZPdsizyy1Yz+EON4CtN3bFLKObXuDu66AjoIbBLlOWvfWJyNiS3J5s/s/c7GnUU4fgjYS vhpRPuOSbAg26iU5n1aGCWShAkEJPQ+3K/sTyR8VX8mUCun1A3OKCwq/G0KSDQClwT9v80 tUp9PJ9WqB4XQ32k09o8TGvY07Q5qJBiHqhUEijjjdo8IaIwMHJ1vr3FdinVuYmdUBzG9H 0sHa2BLA2mJkl2egtVq9qDe6hX/Q9ToP6YRCyswLmsxFo8X/lNmzS16ih6WWwsXkfG7KK0 JXXed+7SDbhHTSyHfSuIh1vECYSnMNSVjjJxxKuR9vr+4sUg83eN8dixB9efUw== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 6/8] pinctrl: Add RTL8231 pin control and GPIO support Date: Tue, 21 Oct 2025 16:24:01 +0200 Message-ID: <20251021142407.307753-7-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This driver implements the GPIO and pin muxing features provided by the RTL8231. The device should be instantiated as an MFD child, where the parent device has already configured the regmap used for register access. Debouncing is only available for the six highest GPIOs, and must be emulated when other pins are used for (button) inputs. Although described in the bindings, drive strength selection is currently not implemented. Signed-off-by: Sander Vanheule Reviewed-by: Linus Walleij --- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rtl8231.c | 538 ++++++++++++++++++++++++++++++ 3 files changed, 550 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-rtl8231.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4f8507ebbdac..75007ba7b80e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -520,6 +520,17 @@ config PINCTRL_ROCKCHIP help This support pinctrl and GPIO driver for Rockchip SoCs. =20 +config PINCTRL_RTL8231 + tristate "Realtek RTL8231 GPIO expander's pin controller" + depends on MFD_RTL8231 + default MFD_RTL8231 + select GPIO_REGMAP + select GENERIC_PINCONF + select GENERIC_PINMUX_FUNCTIONS + help + Support for RTL8231 expander's GPIOs and pin controller. + When built as a module, the module will be called pinctrl-rtl8231. + config PINCTRL_SCMI tristate "Pinctrl driver using SCMI protocol interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e0cfb9b7c99b..ded51723d452 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PINCTRL_PISTACHIO) +=3D pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) +=3D pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) +=3D pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_RP1) +=3D pinctrl-rp1.o +obj-$(CONFIG_PINCTRL_RTL8231) +=3D pinctrl-rtl8231.o obj-$(CONFIG_PINCTRL_SCMI) +=3D pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) +=3D pinctrl-single.o obj-$(CONFIG_PINCTRL_ST) +=3D pinctrl-st.o diff --git a/drivers/pinctrl/pinctrl-rtl8231.c b/drivers/pinctrl/pinctrl-rt= l8231.c new file mode 100644 index 000000000000..e562259d9ffd --- /dev/null +++ b/drivers/pinctrl/pinctrl-rtl8231.c @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include + +#define RTL8231_NUM_GPIOS 37 +#define RTL8231_DEBOUNCE_USEC 100000 +#define RTL8231_DEBOUNCE_MIN_OFFSET 31 + +struct rtl8231_pin_ctrl { + struct regmap *map; +}; + +/* + * Pin controller functionality + */ +enum rtl8231_pin_function { + RTL8231_PIN_FUNCTION_GPIO =3D BIT(0), + RTL8231_PIN_FUNCTION_LED =3D BIT(1), + RTL8231_PIN_FUNCTION_PWM =3D BIT(2), +}; + +struct rtl8231_function_info { + enum rtl8231_pin_function flag; + const char *name; +}; + +#define RTL8231_FUNCTION(_name, _flag) \ +((struct rtl8231_function_info) { \ + .flag =3D (_flag), \ + .name =3D (_name), \ + }) + +static const struct rtl8231_function_info rtl8231_pin_functions[] =3D { + RTL8231_FUNCTION("gpio", RTL8231_PIN_FUNCTION_GPIO), + RTL8231_FUNCTION("led", RTL8231_PIN_FUNCTION_LED), + RTL8231_FUNCTION("pwm", RTL8231_PIN_FUNCTION_PWM), +}; + +struct rtl8231_pin_desc { + enum rtl8231_pin_function functions:8; + u8 reg; + u8 offset; + u8 gpio_function_value; +}; + +#define RTL8231_PIN_DESC(_num, _func, _reg, _fld, _val) \ + [(_num)] =3D ((struct rtl8231_pin_desc) { \ + .functions =3D RTL8231_PIN_FUNCTION_GPIO | (_func), \ + .reg =3D (_reg), \ + .offset =3D (_fld), \ + .gpio_function_value =3D (_val), \ + }) +#define RTL8231_GPIO_PIN_DESC(_num, _reg, _fld) \ + RTL8231_PIN_DESC(_num, 0, _reg, _fld, RTL8231_PIN_MODE_GPIO) +#define RTL8231_LED_PIN_DESC(_num, _reg, _fld) \ + RTL8231_PIN_DESC(_num, RTL8231_PIN_FUNCTION_LED, _reg, _fld, RTL8231_PIN_= MODE_GPIO) +#define RTL8231_PWM_PIN_DESC(_num, _reg, _fld) \ + RTL8231_PIN_DESC(_num, RTL8231_PIN_FUNCTION_PWM, _reg, _fld, 0) + +/* + * All pins have a GPIO/LED mux bit, but the bits for pins 35/36 are read-= only. Use this bit + * for the GPIO-only pin instead of a placeholder, so the rest of the logi= c can stay generic. + */ +static const struct rtl8231_pin_desc rtl8231_pin_data[RTL8231_NUM_GPIOS] = =3D { + RTL8231_LED_PIN_DESC(0, RTL8231_REG_PIN_MODE0, 0), + RTL8231_LED_PIN_DESC(1, RTL8231_REG_PIN_MODE0, 1), + RTL8231_LED_PIN_DESC(2, RTL8231_REG_PIN_MODE0, 2), + RTL8231_LED_PIN_DESC(3, RTL8231_REG_PIN_MODE0, 3), + RTL8231_LED_PIN_DESC(4, RTL8231_REG_PIN_MODE0, 4), + RTL8231_LED_PIN_DESC(5, RTL8231_REG_PIN_MODE0, 5), + RTL8231_LED_PIN_DESC(6, RTL8231_REG_PIN_MODE0, 6), + RTL8231_LED_PIN_DESC(7, RTL8231_REG_PIN_MODE0, 7), + RTL8231_LED_PIN_DESC(8, RTL8231_REG_PIN_MODE0, 8), + RTL8231_LED_PIN_DESC(9, RTL8231_REG_PIN_MODE0, 9), + RTL8231_LED_PIN_DESC(10, RTL8231_REG_PIN_MODE0, 10), + RTL8231_LED_PIN_DESC(11, RTL8231_REG_PIN_MODE0, 11), + RTL8231_LED_PIN_DESC(12, RTL8231_REG_PIN_MODE0, 12), + RTL8231_LED_PIN_DESC(13, RTL8231_REG_PIN_MODE0, 13), + RTL8231_LED_PIN_DESC(14, RTL8231_REG_PIN_MODE0, 14), + RTL8231_LED_PIN_DESC(15, RTL8231_REG_PIN_MODE0, 15), + RTL8231_LED_PIN_DESC(16, RTL8231_REG_PIN_MODE1, 0), + RTL8231_LED_PIN_DESC(17, RTL8231_REG_PIN_MODE1, 1), + RTL8231_LED_PIN_DESC(18, RTL8231_REG_PIN_MODE1, 2), + RTL8231_LED_PIN_DESC(19, RTL8231_REG_PIN_MODE1, 3), + RTL8231_LED_PIN_DESC(20, RTL8231_REG_PIN_MODE1, 4), + RTL8231_LED_PIN_DESC(21, RTL8231_REG_PIN_MODE1, 5), + RTL8231_LED_PIN_DESC(22, RTL8231_REG_PIN_MODE1, 6), + RTL8231_LED_PIN_DESC(23, RTL8231_REG_PIN_MODE1, 7), + RTL8231_LED_PIN_DESC(24, RTL8231_REG_PIN_MODE1, 8), + RTL8231_LED_PIN_DESC(25, RTL8231_REG_PIN_MODE1, 9), + RTL8231_LED_PIN_DESC(26, RTL8231_REG_PIN_MODE1, 10), + RTL8231_LED_PIN_DESC(27, RTL8231_REG_PIN_MODE1, 11), + RTL8231_LED_PIN_DESC(28, RTL8231_REG_PIN_MODE1, 12), + RTL8231_LED_PIN_DESC(29, RTL8231_REG_PIN_MODE1, 13), + RTL8231_LED_PIN_DESC(30, RTL8231_REG_PIN_MODE1, 14), + RTL8231_LED_PIN_DESC(31, RTL8231_REG_PIN_MODE1, 15), + RTL8231_LED_PIN_DESC(32, RTL8231_REG_PIN_HI_CFG, 0), + RTL8231_LED_PIN_DESC(33, RTL8231_REG_PIN_HI_CFG, 1), + RTL8231_LED_PIN_DESC(34, RTL8231_REG_PIN_HI_CFG, 2), + RTL8231_PWM_PIN_DESC(35, RTL8231_REG_FUNC1, 3), + RTL8231_GPIO_PIN_DESC(36, RTL8231_REG_PIN_HI_CFG, 4), +}; +static const unsigned int PWM_PIN =3D 35; + +#define RTL8231_PIN(_num) \ + ((struct pinctrl_pin_desc) { \ + .number =3D (_num), \ + .name =3D "gpio" #_num, \ + .drv_data =3D (void *) &rtl8231_pin_data[(_num)] \ + }) + +static const struct pinctrl_pin_desc rtl8231_pins[RTL8231_NUM_GPIOS] =3D { + RTL8231_PIN(0), + RTL8231_PIN(1), + RTL8231_PIN(2), + RTL8231_PIN(3), + RTL8231_PIN(4), + RTL8231_PIN(5), + RTL8231_PIN(6), + RTL8231_PIN(7), + RTL8231_PIN(8), + RTL8231_PIN(9), + RTL8231_PIN(10), + RTL8231_PIN(11), + RTL8231_PIN(12), + RTL8231_PIN(13), + RTL8231_PIN(14), + RTL8231_PIN(15), + RTL8231_PIN(16), + RTL8231_PIN(17), + RTL8231_PIN(18), + RTL8231_PIN(19), + RTL8231_PIN(20), + RTL8231_PIN(21), + RTL8231_PIN(22), + RTL8231_PIN(23), + RTL8231_PIN(24), + RTL8231_PIN(25), + RTL8231_PIN(26), + RTL8231_PIN(27), + RTL8231_PIN(28), + RTL8231_PIN(29), + RTL8231_PIN(30), + RTL8231_PIN(31), + RTL8231_PIN(32), + RTL8231_PIN(33), + RTL8231_PIN(34), + RTL8231_PIN(35), + RTL8231_PIN(36), +}; + +static int rtl8231_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(rtl8231_pins); +} + +static const char *rtl8231_get_group_name(struct pinctrl_dev *pctldev, uns= igned int selector) +{ + return rtl8231_pins[selector].name; +} + +static int rtl8231_get_group_pins(struct pinctrl_dev *pctldev, unsigned in= t selector, + const unsigned int **pins, unsigned int *num_pins) +{ + if (selector >=3D ARRAY_SIZE(rtl8231_pins)) + return -EINVAL; + + *pins =3D &rtl8231_pins[selector].number; + *num_pins =3D 1; + + return 0; +} + +static const struct pinctrl_ops rtl8231_pinctrl_ops =3D { + .get_groups_count =3D rtl8231_get_groups_count, + .get_group_name =3D rtl8231_get_group_name, + .get_group_pins =3D rtl8231_get_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +static int rtl8231_set_mux(struct pinctrl_dev *pctldev, unsigned int func_= selector, + unsigned int group_selector) +{ + const struct function_desc *func =3D pinmux_generic_get_function(pctldev,= func_selector); + const struct rtl8231_pin_desc *desc =3D rtl8231_pins[group_selector].drv_= data; + const struct rtl8231_pin_ctrl *ctrl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int func_flag =3D (uintptr_t) func->data; + unsigned int function_mask; + unsigned int gpio_function; + + if (!(desc->functions & func_flag)) + return -EINVAL; + + function_mask =3D BIT(desc->offset); + gpio_function =3D desc->gpio_function_value << desc->offset; + + if (func_flag =3D=3D RTL8231_PIN_FUNCTION_GPIO) + return regmap_update_bits(ctrl->map, desc->reg, function_mask, gpio_func= tion); + else + return regmap_update_bits(ctrl->map, desc->reg, function_mask, ~gpio_fun= ction); +} + +static int rtl8231_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + const struct rtl8231_pin_desc *desc =3D rtl8231_pins[offset].drv_data; + const struct rtl8231_pin_ctrl *ctrl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int function_mask; + unsigned int gpio_function; + + function_mask =3D BIT(desc->offset); + gpio_function =3D desc->gpio_function_value << desc->offset; + + return regmap_update_bits(ctrl->map, desc->reg, function_mask, gpio_funct= ion); +} + +static const struct pinmux_ops rtl8231_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .function_is_gpio =3D pinmux_generic_function_is_gpio, + .set_mux =3D rtl8231_set_mux, + .gpio_request_enable =3D rtl8231_gpio_request_enable, + .strict =3D true, +}; + +static int rtl8231_pin_config_get(struct pinctrl_dev *pctldev, unsigned in= t offset, + unsigned long *config) +{ + const struct rtl8231_pin_ctrl *ctrl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int param =3D pinconf_to_config_param(*config); + unsigned int arg; + int err; + int v; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + if (offset < RTL8231_DEBOUNCE_MIN_OFFSET) + return -EINVAL; + + err =3D regmap_read(ctrl->map, RTL8231_REG_FUNC1, &v); + if (err) + return err; + + v =3D FIELD_GET(RTL8231_FUNC1_DEBOUNCE_MASK, v); + if (v & BIT(offset - RTL8231_DEBOUNCE_MIN_OFFSET)) + arg =3D RTL8231_DEBOUNCE_USEC; + else + arg =3D 0; + break; + default: + return -ENOTSUPP; + } + + *config =3D pinconf_to_config_packed(param, arg); + + return 0; +} + +static int rtl8231_pin_config_set(struct pinctrl_dev *pctldev, unsigned in= t offset, + unsigned long *configs, unsigned int num_configs) +{ + const struct rtl8231_pin_ctrl *ctrl =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int param, arg; + unsigned int pin_mask; + int err; + int i; + + for (i =3D 0; i < num_configs; i++) { + param =3D pinconf_to_config_param(configs[i]); + arg =3D pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + if (offset < RTL8231_DEBOUNCE_MIN_OFFSET) + return -EINVAL; + + pin_mask =3D FIELD_PREP(RTL8231_FUNC1_DEBOUNCE_MASK, + BIT(offset - RTL8231_DEBOUNCE_MIN_OFFSET)); + + switch (arg) { + case 0: + err =3D regmap_update_bits(ctrl->map, RTL8231_REG_FUNC1, + pin_mask, 0); + break; + case RTL8231_DEBOUNCE_USEC: + err =3D regmap_update_bits(ctrl->map, RTL8231_REG_FUNC1, + pin_mask, pin_mask); + break; + default: + return -EINVAL; + } + + break; + default: + return -ENOTSUPP; + } + } + + return err; +} + +static const struct pinconf_ops rtl8231_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D rtl8231_pin_config_get, + .pin_config_set =3D rtl8231_pin_config_set, +}; + +static int rtl8231_pinctrl_init_functions(struct pinctrl_dev *pctl, + const struct pinctrl_desc *pctl_desc) +{ + struct pinfunction func; + const char **groups; + unsigned int f_idx; + unsigned int flag; + const char *name; + unsigned int pin; + int num_groups; + int err; + + for (f_idx =3D 0; f_idx < ARRAY_SIZE(rtl8231_pin_functions); f_idx++) { + name =3D rtl8231_pin_functions[f_idx].name; + flag =3D rtl8231_pin_functions[f_idx].flag; + + for (pin =3D 0, num_groups =3D 0; pin < pctl_desc->npins; pin++) + if (rtl8231_pin_data[pin].functions & flag) + num_groups++; + + groups =3D devm_kcalloc(pctl->dev, num_groups, sizeof(*groups), GFP_KERN= EL); + if (!groups) + return -ENOMEM; + + for (pin =3D 0, num_groups =3D 0; pin < pctl_desc->npins; pin++) + if (rtl8231_pin_data[pin].functions & flag) + groups[num_groups++] =3D rtl8231_pins[pin].name; + + func =3D PINCTRL_PINFUNCTION(name, groups, num_groups); + if (flag =3D=3D RTL8231_PIN_FUNCTION_GPIO) + func.flags |=3D PINFUNCTION_FLAG_GPIO; + + err =3D pinmux_generic_add_pinfunction(pctl, &func, (void *) flag); + if (err < 0) + return err; + } + + return 0; +} + +struct pin_field_info { + const struct reg_field gpio_dir; + const struct reg_field mode; +}; + +static const struct pin_field_info pin_fields[] =3D { + { + .gpio_dir =3D REG_FIELD(RTL8231_REG_GPIO_DIR0, 0, 15), + .mode =3D REG_FIELD(RTL8231_REG_PIN_MODE0, 0, 15), + }, + { + .gpio_dir =3D REG_FIELD(RTL8231_REG_GPIO_DIR1, 0, 15), + .mode =3D REG_FIELD(RTL8231_REG_PIN_MODE1, 0, 15), + }, + { + .gpio_dir =3D REG_FIELD(RTL8231_REG_PIN_HI_CFG, 5, 9), + .mode =3D REG_FIELD(RTL8231_REG_PIN_HI_CFG, 0, 4), + }, +}; + +static int rtl8231_configure_safe(struct device *dev, struct regmap *map) +{ + struct regmap_field *field_mode; + struct regmap_field *field_dir; + unsigned int is_output; + unsigned int is_gpio; + unsigned int mode; + unsigned int dir; + int err; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(pin_fields); i++) { + field_dir =3D devm_regmap_field_alloc(dev, map, pin_fields[i].gpio_dir); + if (IS_ERR(field_dir)) + return PTR_ERR(field_dir); + + field_mode =3D devm_regmap_field_alloc(dev, map, pin_fields[i].mode); + if (IS_ERR(field_mode)) + return PTR_ERR(field_mode); + + err =3D regmap_field_read(field_dir, &dir); + if (err) + return err; + + err =3D regmap_field_read(field_mode, &mode); + if (err) + return err; + + /* + * Set every pin that is configured as gpio-output but muxed for the alt= ernative + * (LED) function to gpio-in. That way the pin will be high impedance wh= en it is + * muxed to GPIO, preventing unwanted glitches. + */ + is_gpio =3D mode; + is_output =3D ~dir; + + /* Enable field for PWM (on GPIO35) is in another register */ + if (pin_fields[i].mode.reg =3D=3D RTL8231_REG_PIN_HI_CFG) { + err =3D regmap_test_bits(map, rtl8231_pin_data[PWM_PIN].reg, + BIT(rtl8231_pin_data[PWM_PIN].offset)); + if (err < 0) + return err; + + if (err) + is_gpio &=3D ~BIT(PWM_PIN % RTL8231_BITS_VAL); + } + + /* The pin muxes are left as-is, so there are no signal changes. */ + regmap_field_write(field_dir, dir | (~is_gpio & is_output)); + + devm_regmap_field_free(dev, field_dir); + devm_regmap_field_free(dev, field_mode); + } + + return 0; +} + +static const struct pinctrl_desc rtl8231_pctl_desc =3D { + .name =3D "rtl8231-pinctrl", + .owner =3D THIS_MODULE, + .confops =3D &rtl8231_pinconf_ops, + .pctlops =3D &rtl8231_pinctrl_ops, + .pmxops =3D &rtl8231_pinmux_ops, + .npins =3D ARRAY_SIZE(rtl8231_pins), + .pins =3D rtl8231_pins, +}; + +static int rtl8231_pinctrl_init(struct device *dev, struct rtl8231_pin_ctr= l *ctrl) +{ + struct pinctrl_dev *pctldev; + int err; + + err =3D devm_pinctrl_register_and_init(dev->parent, &rtl8231_pctl_desc, c= trl, &pctldev); + if (err) { + dev_err(dev, "failed to register pin controller\n"); + return err; + } + + err =3D rtl8231_pinctrl_init_functions(pctldev, &rtl8231_pctl_desc); + if (err) + return err; + + err =3D pinctrl_enable(pctldev); + if (err) + dev_err(dev, "failed to enable pin controller\n"); + + return err; +} + +/* + * GPIO controller functionality + */ +static int rtl8231_gpio_reg_mask_xlate(struct gpio_regmap *gpio, unsigned = int base, + unsigned int offset, unsigned int *reg, unsigned int *mask) +{ + unsigned int pin_mask =3D BIT(offset % RTL8231_BITS_VAL); + + if (base =3D=3D RTL8231_REG_GPIO_DATA0 || offset < 32) { + *reg =3D base + offset / RTL8231_BITS_VAL; + *mask =3D pin_mask; + } else if (base =3D=3D RTL8231_REG_GPIO_DIR0) { + *reg =3D RTL8231_REG_PIN_HI_CFG; + *mask =3D FIELD_PREP(RTL8231_PIN_HI_CFG_DIR_MASK, pin_mask); + } else { + return -EINVAL; + } + + return 0; +} + +static int rtl8231_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rtl8231_pin_ctrl *ctrl; + struct gpio_regmap_config gpio_cfg =3D {}; + int err; + + ctrl =3D devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->map =3D dev_get_regmap(dev->parent, NULL); + if (!ctrl->map) + return -ENODEV; + + err =3D rtl8231_configure_safe(dev, ctrl->map); + if (err) + return err; + + err =3D rtl8231_pinctrl_init(dev, ctrl); + if (err) + return err; + + gpio_cfg.regmap =3D ctrl->map; + gpio_cfg.parent =3D dev->parent; + gpio_cfg.ngpio =3D RTL8231_NUM_GPIOS; + gpio_cfg.ngpio_per_reg =3D RTL8231_BITS_VAL; + + gpio_cfg.reg_dat_base =3D GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DATA0); + gpio_cfg.reg_set_base =3D GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DATA0); + gpio_cfg.reg_dir_in_base =3D GPIO_REGMAP_ADDR(RTL8231_REG_GPIO_DIR0); + + gpio_cfg.reg_mask_xlate =3D rtl8231_gpio_reg_mask_xlate; + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_cfg)); +} + +static struct platform_driver rtl8231_pinctrl_driver =3D { + .driver =3D { + .name =3D "rtl8231-pinctrl", + }, + .probe =3D rtl8231_pinctrl_probe, +}; +module_platform_driver(rtl8231_pinctrl_driver); + +MODULE_AUTHOR("Sander Vanheule "); +MODULE_DESCRIPTION("Realtek RTL8231 pin control and GPIO support"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F95338F38 for ; Tue, 21 Oct 2025 14:24:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056680; cv=none; b=Eb9K8HrdjJgo9BOyyI8hCrAWBXVGNNheqmRjMifta8nBceP6gtb5RolJYk95AyCLyAePDHmaSD01mxRpmn/nR/mohd5Ag9kFm7Y7jTK+QmO0NgpWoMQ49nLI/yHVpIvhYuElZ8iYVdfhx4UX83hll6yvJ/3RidUW+DUuZJ+GF1Y= ARC-Message-Signature: i=1; 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Tue, 21 Oct 2025 16:24:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056674; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vAVzl5ebpIdvsx38MJiBPaPb5S38CGc5k4Fc3m1pGoc=; b=NaBmV5EPmindUwDzs5002ttSHZSiQK9XbWSQfBk6pgdrvqwmy5NNgq+PDnbYDSXpohbuqw DrA9GnmpF0XVQOI8nh9IfLNYWq9YnOCBS0/p2m6uJyhB96/YxrWlA946/B/rt/WXa0/MnQ HDNvBjJJrWavuHmt6y7uPGlH8/aqwV6D1dJPJgZbDAMIarAWJ2r+lKDryUulTGDjNSjMRx BEXoSQJ7qgFslQkiObN60AsVHUPREh5AjSuDyrQ7ZWNfcp0OwvzQ8IS/ctSHvlgIeZOaCO Uxwyr7nshUIGe8C/zt0OSPFj5N0Il4iyhKEPM3aj2WndM1uqw/HeoH0XoX+thw== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 7/8] leds: Add support for RTL8231 LED scan matrix Date: Tue, 21 Oct 2025 16:24:02 +0200 Message-ID: <20251021142407.307753-8-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both single and bi-color scanning modes are supported. The driver will verify that the addresses are valid for the current mode, before registering the LEDs. LEDs can be turned on, off, or toggled at one of six predefined rates from 40ms to 1280ms. Implements a platform device for use as a child device with RTL8231 MFD, and uses the parent regmap to access the required registers. Signed-off-by: Sander Vanheule --- drivers/leds/Kconfig | 10 ++ drivers/leds/Makefile | 1 + drivers/leds/leds-rtl8231.c | 285 ++++++++++++++++++++++++++++++++++++ 3 files changed, 296 insertions(+) create mode 100644 drivers/leds/leds-rtl8231.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 06e6291be11b..bb4429bcd7a2 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -666,6 +666,16 @@ config LEDS_REGULATOR help This option enables support for regulator driven LEDs. =20 +config LEDS_RTL8231 + tristate "RTL8231 LED matrix support" + depends on LEDS_CLASS + depends on MFD_RTL8231 + default MFD_RTL8231 + help + This option enables support for using the LED scanning matrix output + of the RTL8231 GPIO and LED expander chip. + When built as a module, this module will be named leds-rtl8231. + config LEDS_BD2606MVV tristate "LED driver for BD2606MVV" depends on LEDS_CLASS diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 9a0333ec1a86..27c32204aebc 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_LEDS_POWERNV) +=3D leds-powernv.o obj-$(CONFIG_LEDS_PWM) +=3D leds-pwm.o obj-$(CONFIG_LEDS_QNAP_MCU) +=3D leds-qnap-mcu.o obj-$(CONFIG_LEDS_REGULATOR) +=3D leds-regulator.o +obj-$(CONFIG_LEDS_RTL8231) +=3D leds-rtl8231.o obj-$(CONFIG_LEDS_SC27XX_BLTC) +=3D leds-sc27xx-bltc.o obj-$(CONFIG_LEDS_ST1202) +=3D leds-st1202.o obj-$(CONFIG_LEDS_SUN50I_A100) +=3D leds-sun50i-a100.o diff --git a/drivers/leds/leds-rtl8231.c b/drivers/leds/leds-rtl8231.c new file mode 100644 index 000000000000..8ff20cc7ea98 --- /dev/null +++ b/drivers/leds/leds-rtl8231.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#include + +/** + * struct led_toggle_rate - description of an LED blinking mode + * @interval_ms: LED toggle rate in milliseconds + * @mode: Register field value used to activate this mode + * + * For LED hardware accelerated blinking, with equal on and off delay. + * Both delays are given by @interval, so the interval at which the LED bl= inks + * (i.e. turn on and off once) is double this value. + */ +struct led_toggle_rate { + u16 interval_ms; + u8 mode; +}; + +/** + * struct led_modes - description of all LED modes + * @toggle_rates: Array of led_toggle_rate values, sorted by ascending int= erval + * @num_toggle_rates: Number of elements in @led_toggle_rate + * @off: Register field value to turn LED off + * @on: Register field value to turn LED on + */ +struct led_modes { + const struct led_toggle_rate *toggle_rates; + unsigned int num_toggle_rates; + u8 off; + u8 on; +}; + +struct rtl8231_led { + struct led_classdev led; + const struct led_modes *modes; + struct regmap_field *reg_field; +}; +#define to_rtl8231_led(_cdev) container_of(_cdev, struct rtl8231_led, led) + +#define RTL8231_NUM_LEDS 3 +#define RTL8231_LED_PER_REG 5 +#define RTL8231_BITS_PER_LED 3 + +static const unsigned int rtl8231_led_port_counts_single[RTL8231_NUM_LEDS]= =3D {32, 32, 24}; +static const unsigned int rtl8231_led_port_counts_bicolor[RTL8231_NUM_LEDS= ] =3D {24, 24, 24}; + +static const unsigned int rtl8231_led_base[RTL8231_NUM_LEDS] =3D { + RTL8231_REG_LED0_BASE, + RTL8231_REG_LED1_BASE, + RTL8231_REG_LED2_BASE, +}; + +#define RTL8231_DEFAULT_TOGGLE_INTERVAL_MS 500 + +static const struct led_toggle_rate rtl8231_toggle_rates[] =3D { + { 40, 1}, + { 80, 2}, + { 160, 3}, + { 320, 4}, + { 640, 5}, + {1280, 6}, +}; + +static const struct led_modes rtl8231_led_modes =3D { + .off =3D 0, + .on =3D 7, + .num_toggle_rates =3D ARRAY_SIZE(rtl8231_toggle_rates), + .toggle_rates =3D rtl8231_toggle_rates, +}; + +static void rtl8231_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8231_led *pled =3D to_rtl8231_led(led_cdev); + + if (brightness) + regmap_field_write(pled->reg_field, pled->modes->on); + else + regmap_field_write(pled->reg_field, pled->modes->off); +} + +static enum led_brightness rtl8231_led_brightness_get(struct led_classdev = *led_cdev) +{ + struct rtl8231_led *pled =3D to_rtl8231_led(led_cdev); + u32 current_mode =3D pled->modes->off; + + regmap_field_read(pled->reg_field, ¤t_mode); + + if (current_mode =3D=3D pled->modes->off) + return LED_OFF; + else + return LED_ON; +} + +static unsigned int rtl8231_led_current_interval(struct rtl8231_led *pled) +{ + unsigned int mode; + unsigned int i; + + if (regmap_field_read(pled->reg_field, &mode)) + return 0; + + for (i =3D 0; i < pled->modes->num_toggle_rates; i++) + if (mode =3D=3D pled->modes->toggle_rates[i].mode) + return pled->modes->toggle_rates[i].interval_ms; + + return 0; +} + +static int rtl8231_led_blink_set(struct led_classdev *led_cdev, unsigned l= ong *delay_on, + unsigned long *delay_off) +{ + struct rtl8231_led *pled =3D to_rtl8231_led(led_cdev); + const struct led_toggle_rate *rates =3D pled->modes->toggle_rates; + unsigned int num_rates =3D pled->modes->num_toggle_rates; + unsigned int interval_ms; + unsigned int i; + int err; + + if (*delay_on =3D=3D 0 && *delay_off =3D=3D 0) { + interval_ms =3D RTL8231_DEFAULT_TOGGLE_INTERVAL_MS; + } else { + /* + * If the current mode is blinking, choose the delay that (likely) chang= ed. + * Otherwise, choose the interval that would have the same total delay. + */ + interval_ms =3D rtl8231_led_current_interval(pled); + if (interval_ms > 0 && interval_ms =3D=3D *delay_off) + interval_ms =3D *delay_on; + else if (interval_ms > 0 && interval_ms =3D=3D *delay_on) + interval_ms =3D *delay_off; + else + interval_ms =3D (*delay_on + *delay_off) / 2; + } + + /* Find clamped toggle interval */ + for (i =3D 0; i < (num_rates - 1); i++) + if (interval_ms > rates[i].interval_ms) + break; + + interval_ms =3D rates[i].interval_ms; + + err =3D regmap_field_write(pled->reg_field, rates[i].mode); + if (err) + return err; + + *delay_on =3D interval_ms; + *delay_off =3D interval_ms; + + return 0; +} + +static int rtl8231_led_read_address(struct fwnode_handle *fwnode, unsigned= int *addr_port, + unsigned int *addr_led) +{ + u32 addr[2]; + int err; + + err =3D fwnode_property_count_u32(fwnode, "reg"); + if (err < 0) + return err; + if (err !=3D ARRAY_SIZE(addr)) + return -EINVAL; + + err =3D fwnode_property_read_u32_array(fwnode, "reg", addr, ARRAY_SIZE(ad= dr)); + if (err) + return err; + + *addr_port =3D addr[0]; + *addr_led =3D addr[1]; + + return 0; +} + +static struct regmap_field *rtl8231_led_get_field(struct device *dev, stru= ct regmap *map, + unsigned int port_index, unsigned int led_index) +{ + unsigned int offset =3D port_index / RTL8231_LED_PER_REG; + unsigned int shift =3D (port_index % RTL8231_LED_PER_REG) * RTL8231_BITS_= PER_LED; + const struct reg_field field =3D REG_FIELD(rtl8231_led_base[led_index] + = offset, shift, + shift + RTL8231_BITS_PER_LED - 1); + + return devm_regmap_field_alloc(dev, map, field); +} + +static int rtl8231_led_probe_single(struct device *dev, struct regmap *map, + const unsigned int *port_counts, struct fwnode_handle *fwnode) +{ + struct led_init_data init_data =3D {}; + struct rtl8231_led *pled; + unsigned int port_index; + unsigned int led_index; + int err; + + pled =3D devm_kzalloc(dev, sizeof(*pled), GFP_KERNEL); + if (!pled) + return -ENOMEM; + + err =3D rtl8231_led_read_address(fwnode, &port_index, &led_index); + if (err) { + dev_err(dev, "LED address invalid"); + return err; + } + + if (led_index >=3D RTL8231_NUM_LEDS || port_index >=3D port_counts[led_in= dex]) { + dev_err(dev, "LED address (%d.%d) invalid", port_index, led_index); + return -EINVAL; + } + + pled->reg_field =3D rtl8231_led_get_field(dev, map, port_index, led_index= ); + if (IS_ERR(pled->reg_field)) + return PTR_ERR(pled->reg_field); + + pled->modes =3D &rtl8231_led_modes; + + pled->led.max_brightness =3D 1; + pled->led.brightness_get =3D rtl8231_led_brightness_get; + pled->led.brightness_set =3D rtl8231_led_brightness_set; + pled->led.blink_set =3D rtl8231_led_blink_set; + + init_data.fwnode =3D fwnode; + + return devm_led_classdev_register_ext(dev, &pled->led, &init_data); +} + +static int rtl8231_led_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const unsigned int *port_counts; + struct fwnode_handle *child; + struct regmap *map; + int err; + + map =3D dev_get_regmap(dev->parent, NULL); + if (!map) + return -ENODEV; + + if (device_property_match_string(dev, "realtek,led-scan-mode", "single-co= lor") >=3D 0) { + port_counts =3D rtl8231_led_port_counts_single; + regmap_update_bits(map, RTL8231_REG_FUNC0, + RTL8231_FUNC0_SCAN_MODE, RTL8231_FUNC0_SCAN_SINGLE); + } else if (device_property_match_string(dev, "realtek,led-scan-mode", "bi= -color") >=3D 0) { + port_counts =3D rtl8231_led_port_counts_bicolor; + regmap_update_bits(map, RTL8231_REG_FUNC0, + RTL8231_FUNC0_SCAN_MODE, RTL8231_FUNC0_SCAN_BICOLOR); + } else { + dev_err(dev, "scan mode missing or invalid"); + return -EINVAL; + } + + fwnode_for_each_available_child_node(dev->fwnode, child) { + err =3D rtl8231_led_probe_single(dev, map, port_counts, child); + if (err) + dev_warn(dev, "failed to register LED %pfwP", child); + } + + return 0; +} + +static const struct of_device_id of_rtl8231_led_match[] =3D { + { .compatible =3D "realtek,rtl8231-leds" }, + {} +}; +MODULE_DEVICE_TABLE(of, of_rtl8231_led_match); + +static struct platform_driver rtl8231_led_driver =3D { + .driver =3D { + .name =3D "rtl8231-leds", + .of_match_table =3D of_rtl8231_led_match, + }, + .probe =3D rtl8231_led_probe, +}; +module_platform_driver(rtl8231_led_driver); + +MODULE_AUTHOR("Sander Vanheule "); +MODULE_DESCRIPTION("Realtek RTL8231 LED support"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Sat Feb 7 19:04:18 2026 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A01D433DEE7 for ; Tue, 21 Oct 2025 14:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.241.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056681; cv=none; b=SaQ2V8BRHvtz+7/o7+JfqShGksT+tOO4JhitYni3extD/7xOgZraiW8Qodl33v3P0SXP0MFqHry2/yoz1M7uwr/aWziNlgQrV7DSX6bDtbYr7BJgVyJ3x4+2ZQE7LyMQqkkZwO8nTDL/DAWP6qH8KGeenWM+EEuQ7s3qYeU8uKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761056681; c=relaxed/simple; bh=Fez7uS8AbScs89gfdW78iX7P7jEs/X0KZa5sFOKAbRo=; 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Tue, 21 Oct 2025 16:24:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1761056674; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hi27ZSmrR6t0dm+4AwHvX71F/u/ISlzchGx+6AIwVJI=; b=RR2SygYhLgA7AsiICg78fI1XTrOUI9zPfQMoIGqRW5Ex0wbXQgF28cq/dyK8xNeE/Vnp1x Qnqpr3R1rXuykdB0cvpkVO6Y3zyKRj+3o8sIH2O+TvmTUFz5YdNpFi20xcBw03obsoM2Kl Gx24igIctmBhXDveVXSZKpBDGHPqtNdkq48SLS3zxKkY7Xd1hHzgfQo0TQcpTkpMjRdH22 mK89xXHgdwkiyRXm2sdoUqybLjGpcT6gA6MN7qBP2/38Kr/wFnGfQPGKTG/SxCG+MS1C11 bDCRNcWE5kAzgGRdf7xsdlLsveU2y/OZaBG5BzII8vOFRI1VJ9YQsgih+QHXaQ== From: Sander Vanheule To: Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-leds@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v6 8/8] MAINTAINERS: Add RTL8231 MFD driver Date: Tue, 21 Oct 2025 16:24:03 +0200 Message-ID: <20251021142407.307753-9-sander@svanheule.net> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251021142407.307753-1-sander@svanheule.net> References: <20251021142407.307753-1-sander@svanheule.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the files associated with the RTL8231 support, and list Sander Vanheule (myself) as maintainer. Signed-off-by: Sander Vanheule --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..a83c57091a9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21630,6 +21630,16 @@ S: Maintained F: Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml F: drivers/watchdog/realtek_otto_wdt.c =20 +REALTEK RTL8231 MFD DRIVER +M: Sander Vanheule +S: Maintained +F: Documentation/devicetree/bindings/leds/realtek,rtl8231-leds.yaml +F: Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml +F: drivers/leds/leds-rtl8231.c +F: drivers/mfd/rtl8231.c +F: drivers/pinctrl/pinctrl-rtl8231.c +F: include/linux/mfd/rtl8231.h + REALTEK RTL83xx SMI DSA ROUTER CHIPS M: Linus Walleij M: Alvin =C5=A0ipraga --=20 2.51.0