From nobody Sun Feb 8 12:20:48 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0834330C37B for ; Tue, 21 Oct 2025 08:35:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761035752; cv=none; b=EbWDRFXmZGX7uHIz3Fv92qyMT3+d/iHgONk9vI9xvUBH7ofG95iE5hcwv7r44/pl1vgJ1urNkolPcVrLRJPc3TKcJKSdwqs5UTqwuQLFIRslQ0pdrUQgKy6dLZqdapgi5NV18eMithbZv9qN/xqhmihw0GxEzNyatd/BB2HRpXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761035752; c=relaxed/simple; bh=FlosaNiHGpEDQzKGrkVj0yU5+dHfFwwNLg7K+/7VJlU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=WKVpyHQm1YGlgK8UHH/eabAZVw9ioLf+PtAKw9TsbFeE0sYvxjzc6QDBllO2pdTCtCh6KBV0p9mxGoS3Qm6os76APRoWXUIJ+J2rHLpCpTcRTU/ynf1t2lN+Tx34FqkaSIYseoDvmWaub3QkfeV/pZCxHwK6XXq3INtHEOspD1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 59L8VrpO071964 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Tue, 21 Oct 2025 16:31:53 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 21 Oct 2025 16:31:53 +0800 From: Hui Min Mina Chou To: , , , , , CC: , , , , , , , Subject: [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries Date: Tue, 21 Oct 2025 16:31:05 +0800 Message-ID: <20251021083105.4029305-1-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 59L8VrpO071964 From: Hui Min Mina Chou If multiple VCPUs of the same Guest/VM run on the same Host CPU, hfence.vvma only flushes that Host CPU=E2=80=99s VS-stage TLB. Other Host C= PUs may retain stale VS-stage entries. When a VCPU later migrates to a different Host CPU, it can hit these stale GVA to GPA mappings, causing unexpected faults in the Guest. To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU. This ensures that no stale VS-stage mappings remain after VCPU migration. Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CPU = changes") Signed-off-by: Hui Min Mina Chou Signed-off-by: Ben Zong-You Xie Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- Changes in v2: - Updated Fixes commit to 92e450507d56 - Renamed function to kvm_riscv_local_tlb_sanitize arch/riscv/kvm/vmid.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c index 3b426c800480..6323f5383d36 100644 --- a/arch/riscv/kvm/vmid.c +++ b/arch/riscv/kvm/vmid.c @@ -125,7 +125,7 @@ void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu) kvm_make_request(KVM_REQ_UPDATE_HGATP, v); } =20 -void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu) +void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu) { unsigned long vmid; =20 @@ -146,4 +146,10 @@ void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *v= cpu) =20 vmid =3D READ_ONCE(vcpu->kvm->arch.vmid.vmid); kvm_riscv_local_hfence_gvma_vmid_all(vmid); + + /* + * Flush VS-stage TLBs entry after VCPU migration to avoid using + * stale entries. + */ + kvm_riscv_local_hfence_vvma_all(vmid); } --=20 2.34.1