From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEB5B22579E; Tue, 21 Oct 2025 07:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032611; cv=none; b=j9J7TwVuBKlFi2nRrlTJNqsiBM5iM3Rhj1+3tFDk7aDxET8YwZkiddLiJ5FTaAwSyqPvXYJU83p+BCOK+A1WJw8ipeeCoHmZa6GeeLjykCeiI07kftisWBG/5AeNwfNPkVmAaJB1ovlb19xuggmR1VbcFKhEXzxvFfdgbEyx7pU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032611; c=relaxed/simple; bh=g9ZHrtgCu19pxECRrEzDTMEJRWQ2BNx9AdxH6gqHpF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jcvejEpqfJMA+xH85WhWpsPFFXGFBAy0lGlbF4QDgz37TY/+tLUKoty2v2RtDCV3qg2Z3nAOk+YpJxDOjqeD2gX+Vxt6STVvr84oVKblOGRDd8EuKrG+MynFTKCSGNzNhiuq9f7PggfZWLnLx9IlHNjwVCLyyGnfjEnyEFVA2kI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=zzlF/GQw; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="zzlF/GQw" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=AP5GZTY+6u3putkH9wiit+MCCXjcLlm9TffEsIJtyyg=; b=zzlF/GQwOQQvsH29acgbHn7dAx ACbGisNDNz3tl3h2hrkFyVvLWA7oGx+H+Mjp9DE5lsHALp/RE3JLcsKaUW0c41i9v1/4crFVVedG2 AlMSHCTLWmg0ZUJiaGLcwNPRcaW+pIXnCMdDKCKMjz0bNglzD62Dy9PAE9AYVWanGk4uF3AsL08f9 MCkKHHAX6WVwftxB2eModVhyUOeW9OlIqjeUIJljygAa8bS7J7I4H4CN8alGbp8VIRwOlTCk95b97 GzbLFTjxfpAMAwe3p1gEhed5lRb6+VwZJGuv+dES2UvxABVI9HXUFrUFAevlrxM54coSPlW7qmrR/ AecrvQkg==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71M-0000uy-Mp; Tue, 21 Oct 2025 09:43:04 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner , Conor Dooley Subject: [PATCH v2 1/9] dt-bindings: display: rockchip: dw-hdmi: Add compatible for RK3368 HDMI Date: Tue, 21 Oct 2025 09:42:46 +0200 Message-ID: <20251021074254.87065-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Define a new compatible for RK3368 HDMI. The RK3368 HDMI also uses a PHY internal to the controller, so works similar to other controllers, with the exception that the RK3368 only has one VOP, so there is no source selection needed. Acked-by: Conor Dooley Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw= -hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw= -hdmi.yaml index 9d096856a79a..29716764413a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.y= aml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.y= aml @@ -23,6 +23,7 @@ properties: - rockchip,rk3228-dw-hdmi - rockchip,rk3288-dw-hdmi - rockchip,rk3328-dw-hdmi + - rockchip,rk3368-dw-hdmi - rockchip,rk3399-dw-hdmi - rockchip,rk3568-dw-hdmi =20 --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34DCD280CFB; Tue, 21 Oct 2025 07:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032612; cv=none; b=ZJn3ls/onK8b63gxTVUFE7639W2hIcQGQNG2WtPjqjfCbFcnbLScNnTz30Tas0Bp7e9eD1viy0lCbkSZc1+1PiNTU94UkWEwjLfS0KWZ71UFGqSOIcvlwjNt3MIaiFNnzIGUOVrudULmXFBUGSGAkCbVf0ge55uD7oOtL4cmbuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032612; c=relaxed/simple; bh=VRhiyPyyKDnX9z2ZdRGv8JRlIhCWSif+N76png4X5E0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dVd+4tysXtSE7MoWeiUZGAefzUDXw1RTB/7b+OPAzsNcWjHCIWCbgr1atYCvTYCGbz9ETXMjbDldZ50F4DL/LigJFjAgOoM/F2AxmcYumAfH7ol/XawL5dYEEYQbYUBN8SaGtpyacX2C1dLEVTVto4icO4bz7FohIE0CGDraTPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=QCpsxy9c; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="QCpsxy9c" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=FS4dERJDFsHCnVZ76N6RaaiZZW7ln6HmoGA7DcqZWmQ=; b=QCpsxy9cZFNcyN9fqhpFFoyzIU GLVWRogS3VEDnMPTV8IPVtHV7fz8uqB/C3C43KKxi1Rvh7kYoAGMVo+HKCP31BbcYRn9XN5y5+E2D utJ1RiHVoWLeLUt+aW2K4cG9+1NPtWRDCWAKa8GBNDrA0fU6KKs+yuMUeagUtcPRlUfHlusR0FpLe oG6vxv7zv6UbAke9k2lqVFaIyR/K1fYp968iaIyHNPTurlad1Xqcw2J3djCsdEaNpLyD0wMqtsHs3 BcIHvNvAchMJliCvGSrc020sgzMjL1sWvMzjhnfJOvPq2MvRaNUd8VN0VGhBlxkBNL2ECwWX5M4ve RRVsz1hg==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71N-0000uy-BF; Tue, 21 Oct 2025 09:43:05 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 2/9] drm/rockchip: hdmi: add RK3368 controller variant Date: Tue, 21 Oct 2025 09:42:47 +0200 Message-ID: <20251021074254.87065-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The RK3368 has only one VOP, so there is no source selection happening and the controller uses an internal PHY for the HDMI output. Signed-off-by: Heiko Stuebner Reviewed-by: Andy Yan --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/= rockchip/dw_hdmi-rockchip.c index 7b613997bb50..95ff3fce97a3 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -467,6 +467,19 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_= data =3D { .use_drm_infoframe =3D true, }; =20 +static struct rockchip_hdmi_chip_data rk3368_chip_data =3D { + .lcdsel_grf_reg =3D -1, +}; + +static const struct dw_hdmi_plat_data rk3368_hdmi_drv_data =3D { + .mode_valid =3D dw_hdmi_rockchip_mode_valid, + .mpll_cfg =3D rockchip_mpll_cfg, + .cur_ctr =3D rockchip_cur_ctr, + .phy_config =3D rockchip_phy_config, + .phy_data =3D &rk3368_chip_data, + .use_drm_infoframe =3D true, +}; + static struct rockchip_hdmi_chip_data rk3399_chip_data =3D { .lcdsel_grf_reg =3D RK3399_GRF_SOC_CON20, .lcdsel_big =3D FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 0), @@ -507,6 +520,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_id= s[] =3D { { .compatible =3D "rockchip,rk3328-dw-hdmi", .data =3D &rk3328_hdmi_drv_data }, + { .compatible =3D "rockchip,rk3368-dw-hdmi", + .data =3D &rk3368_hdmi_drv_data + }, { .compatible =3D "rockchip,rk3399-dw-hdmi", .data =3D &rk3399_hdmi_drv_data }, --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A892B2737F9; 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Tue, 21 Oct 2025 09:43:05 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 3/9] soc: rockchip: grf: Add select correct PWM implementation on RK3368 Date: Tue, 21 Oct 2025 09:42:48 +0200 Message-ID: <20251021074254.87065-4-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Similar to the RK3288, the RK3368 has two different implementations of the PWM block inside the SoC - the newer ones that we have a driver for and that is used on every SoC and a previous variant that was likely left as a fallback if the new one creates problems. The devicetree is already set up for the new variant, so make sure we actually use it - similar to the RK3288. Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/grf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c index 344870da7675..963cdea01ce7 100644 --- a/drivers/soc/rockchip/grf.c +++ b/drivers/soc/rockchip/grf.c @@ -91,6 +91,7 @@ static const struct rockchip_grf_info rk3328_grf __initco= nst =3D { =20 static const struct rockchip_grf_value rk3368_defaults[] __initconst =3D { { "jtag switching", RK3368_GRF_SOC_CON15, FIELD_PREP_WM16_CONST(BIT(13), = 0) }, + { "pwm select", RK3368_GRF_SOC_CON15, FIELD_PREP_WM16_CONST(BIT(12), 1) }, }; =20 static const struct rockchip_grf_info rk3368_grf __initconst =3D { --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3377C24729A; Tue, 21 Oct 2025 07:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032611; cv=none; b=QaA0iT3JpU9OrVN9gW8vgRu70DwWNR8bgtaYSfNV6GhFEHBFjU7F3jJWFkuESscY/EI/u2FTKmnrr1D5f0Acheasse1uncp9F7AzP19UpT830HBw0zqL1Pe6NyfXZ+5TZt33cO7mdlXXhmqf8LOfFQ5KKDFFz3VB4eo9VW6UPbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032611; c=relaxed/simple; bh=rHbR+j8S8tXqpeLLjUh47e1ekryf3X4jzfjFx7zr+t0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gq5s5jlJRU66zq9XHT+Mkg9yZwcA9Vq3vUmPmeH+slbaleME0M49sBOUFz2BCSrDXXrSVgQLq4sk7X6XeKHNtFjCiforXlEmJKfDoBK2W3MeSDfQlYBKRW7yDt0hOaauE+DNboumFUolTnh2txyu0THXT/rpVakzno+MHwEm7OM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=hGigLLHz; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="hGigLLHz" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=DQiFTA1Zb0f+PltH60opSgxEGjud3fhNqO/a6P7cdMQ=; b=hGigLLHzRgtp20dwA8JjHs7izb OSAtKM6CvnKyn2qGGhTEgzXKtVgwieG5XeDqSRKz3Lpiwc6jXQXVm18YL/QiHwSTg2NRY1QBCYrgp Vv0adkWzqEuMnuqGSSc4xWt0s60GpXcxRETJNaYSDdwOiInDYVa6WERFcBjFzNV3HAA9ee6PGWHJS vpd7v9TOwOAPuSlhN2i9xWkK1YeMrBh8mcikpksA+enGOlEGDUXXVptYF+kjCkMiJtcYuKerS9xfN om6qupUiMEL5YZIviWcgozizaR4b9od+LoObXwACthEjFOECfWTNzPLdtUALJro6iWKBWKf33/nBw m+AvKbqg==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71O-0000uy-4v; Tue, 21 Oct 2025 09:43:06 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 4/9] arm64: dts: rockchip: Add power-domain to RK3368 DSI controller Date: Tue, 21 Oct 2025 09:42:49 +0200 Message-ID: <20251021074254.87065-5-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The DSI controller is also part of the VIO power-domain and it definitely needs to be on when accessing it to not cause SError faults, so add the power-domains property to it. Fixes: 5023d0cd6183 ("arm64: dts: rockchip: Add DSI for RK3368") Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts= /rockchip/rk3368.dtsi index 8f0216203241..5b2cbb3003b6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -896,6 +896,7 @@ mipi_dsi: dsi@ff960000 { clock-names =3D "pclk"; phys =3D <&dphy>; phy-names =3D "dphy"; + power-domains =3D <&power RK3368_PD_VIO>; resets =3D <&cru SRST_MIPIDSI0>; reset-names =3D "apb"; rockchip,grf =3D <&grf>; --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EA75263C69; Tue, 21 Oct 2025 07:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032612; cv=none; b=HCzqMlpzDe+YLODGbuXz6DTSa5RqtGc2Z4yVXCjjQhe3I6o+H03Z3/xare1hCjldwjhCZ98/1jl2p1OmaWfwWQFipuQdsVohkK/x2YK/Ccr8KUbChrxFI4599cG0V9GGULB1atxXEkGVRSW4G0JEg2WI6Wbi0dNNWFQgEaeXydo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032612; c=relaxed/simple; bh=NYtGpFUqxfCvceJbUCP/XQAGwrV3WJO9yfm1U9sVb+A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ac1+bA03p2oXT7Ln2wSe/DbCxRvO6hrFaMb66xMBNypxKaOW9SIp98oqAa3eoCP/TFFP36O/GX1yuWNm+uZHYZgfrYKBFQOKWjYPKMbrzENPPgfXlmN3gYJtXI1ZuHqBkPfG11HCD6a/tmXFf2DlA4MjaOcOKHKFqC2hQsLrstk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=jlUVEXvA; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="jlUVEXvA" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=mmlHMPWedKZa3b5lspADk1yGjz374S0SlNnfit98E9I=; b=jlUVEXvAHh3IXoI8CaQJLnkll7 5haUWO+poWoQMwL+eZ9FT43Z/c7uyRa4kqt4q24UWF52y0cu+tyeIuuC2ATYVEc1184y5zq4w3Bmt lcagqGU3K2VaYMpbxfNVsdyldDdFxjx64j8xlC+KQk2Ar6ThZUxzgOfQRpKKQEq10hb0yjROERpxH WSLuYet96m6Mb0btNwUpuEg4UA29Z20lLnoTR9jHmPyNVJxUAsuEZ9xuqU8Hq8g7mXhEK6/7/yuDK YVOEwpVjjKkcd2o1NprP4CQl1Oiu+KRJK6ycUlI66jikfW5avzwZHQbVUdU81fRTKcgt64QfqLuGO i2ao6vpA==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71O-0000uy-Hl; Tue, 21 Oct 2025 09:43:06 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 5/9] arm64: dts: rockchip: Add power-domain to RK3368 VOP controller Date: Tue, 21 Oct 2025 09:42:50 +0200 Message-ID: <20251021074254.87065-6-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The VOP is also part of the VIO power-domain and it definitely needs to be on when accessing it to not cause SError faults, so add the power-domains property to it. Fixes: ef06b5ddee1e ("arm64: dts: rockchip: Add display subsystem for RK336= 8") Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts= /rockchip/rk3368.dtsi index 5b2cbb3003b6..ce4b112b082b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -862,6 +862,7 @@ vop: vop@ff930000 { clocks =3D <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; clock-names =3D "aclk_vop", "dclk_vop", "hclk_vop"; iommus =3D <&vop_mmu>; + power-domains =3D <&power RK3368_PD_VIO>; resets =3D <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC= 0_DCLK>; reset-names =3D "axi", "ahb", "dclk"; status =3D "disabled"; --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DAA4281356; Tue, 21 Oct 2025 07:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032613; cv=none; b=sdRKwpHuQq81zEnfJIX7Ns0Ub5c+ZaTTaFxYD6/zu3ShEHM211u8o0ySa2bFqSRggrg9PSx6INyPnQiWvilC0Tglv1GlaA/9UZkdLzKLwPEDvyaEdcxUGtinxS8122V9sUlUQ6GoZA24T5wOfzjB5MwRy83wLPwNwjq0DxDdGN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032613; c=relaxed/simple; bh=e1PwJ4bzI7YJDCEyLHU66rcxl7aC6DVUx7j4bhy+xHU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E3Vz4N3dmxEYbfDXwScnOAJh4oHD4ElVOdKJMVtvh6OF+tZ+aTroohxTnjeNyga+RhR/ohPky3GuMzSK1t9AKBowybZOBHjXNXH2GnvG10ANWfQVnVSIV2DdcarpRaHcLY6bYsRpN2NlekZXqB0+J/g/Iu02xdJS9lPGKSos9uk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=o3JiK/qO; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="o3JiK/qO" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=eRts01yY6wbXoZJiKV8EilNEez97RUtFkZlyQpaiO4k=; b=o3JiK/qO0Q1QURZtQaMB92OVLg KcQi0S6p76uT0t7rrAqusF7W6eDq3ykTRx0KvDUS4QKZFHliSmQtCizSAq0hyER6kPZ//8tuQCjBr C6SEHhEdr3NW30ccK+RexkPd2SteNu86isiZi7OC4iCKN7LHCf0T+6RsKswlpLLkAVs8crd99U/we 26UUU0ScevKW0l84TnFae557F8GV5W8FzLY9fhza2GRgODxucHkUVpbFSqtJ2GuN08mNmpO5YVi2Z KRzCizW1diu9kFScYxZttCUAu/FjfVQceAnizjykbuALdMyaIaiPEvSSHkFPGWwa9BIyK9v334Wp2 hIkidzNw==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71O-0000uy-Uj; Tue, 21 Oct 2025 09:43:06 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 6/9] arm64: dts: rockchip: Use phandle for i2c_lvds_blc on rk3368-lion haikou Date: Tue, 21 Oct 2025 09:42:51 +0200 Message-ID: <20251021074254.87065-7-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner i2c@0 on i2cmux2 does already have a phandle i2c_lvds_blc defined. Use this one instead of replicating the hierarchy again, as this might result in strange errors if the lion dtsi is changed at some point in the future. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- .../boot/dts/rockchip/rk3368-lion-haikou.dts | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm= 64/boot/dts/rockchip/rk3368-lion-haikou.dts index ab70ee5f561a..abd1af97456a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -18,16 +18,6 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 - i2cmux2 { - i2c@0 { - eeprom: eeprom@50 { - compatible =3D "atmel,24c01"; - pagesize =3D <8>; - reg =3D <0x50>; - }; - }; - }; - leds { pinctrl-0 =3D <&module_led_pins>, <&sd_card_led_pin>; =20 @@ -68,6 +58,14 @@ vcc5v0_otg: regulator-vcc5v0-otg { }; }; =20 +&i2c_lvds_blc { + eeprom: eeprom@50 { + compatible =3D "atmel,24c01"; + pagesize =3D <8>; + reg =3D <0x50>; + }; +}; + &sdmmc { bus-width =3D <4>; cap-mmc-highspeed; --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A35A8283FCF; Tue, 21 Oct 2025 07:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032613; cv=none; b=aZxcUVmqEw+Bs+JOCc/ZEgj4/DVXFz552q2biHOZMSo/xYh7rmQqu+AG6EmKSVdcoy9nTHsEncqHI+6gvOIalqL9MkFWQwM3pDwUvxsr+d2sb2H1Sf/Ttg2i+mH9NOVJCvKcZ8/Up4vuklukrjRST27veEgc419ChKFlDJcj/OM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032613; c=relaxed/simple; bh=6SOtHTHhC12bQGW74b8/HTVTvTP4IULGQQ3G+otiX/I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XkhUeTH8UqVxFJJN/de65tm/jFwpvdsRVJbJICg3y8g3yg29ObGtpApv1c1ZUJcSwLcRR3dpmyyWEV5yXHakbmldwqkoTkvcnaZa0zXx3WaQiA98IRjOLiKUNAWZpdod+R+Tk2KNJ/RLh+dNvVw7p9NSawhvzqZHbjQU0ocY8e0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=tiN9QwSh; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="tiN9QwSh" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=Cc1STdILGLg5BzAaHuh5zXaUjmHX9akYX2GxkMZPRDo=; b=tiN9QwShaieVMZNJTQ68si1pga Zxp8KYENwm/k4gjxvACQYAYGBpU8bsxOR6KJmC+BJttX9VsNBOppu3fXQ/SUy8a2rGmc2fRaZKYwf /uo/dACxUSuoYoulrbvNvAteTskJtqPb0E7Fozfm1ZPTBcgIG3C8R8WbqOaZ+5ZNWFkVQGxggtbOh X8kIs6BShjydMCC+amlR84XBKw1Y2eOwlR0QA+HXHY4iFbC3Seb3Y3ntwlJeIdU7Z0ucqdEy+tTqt UYz8TuPkSPOATWKnueiw+X0xKpqilGOSh13xt0xmD9OdCsRLtQghAt1Bb8s3kvzfpKc/WSRHRdK16 kg6vvl7Q==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71P-0000uy-Bm; Tue, 21 Oct 2025 09:43:07 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 7/9] arm64: dts: rockchip: Add HDMI node to RK3368 Date: Tue, 21 Oct 2025 09:42:52 +0200 Message-ID: <20251021074254.87065-8-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Add the HDMI controller node to the main SoC devicetree and hook it into the VOP. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts= /rockchip/rk3368.dtsi index ce4b112b082b..892d35242259 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -875,6 +875,11 @@ vop_out_dsi: endpoint@0 { reg =3D <0>; remote-endpoint =3D <&dsi_in_vop>; }; + + vop_out_hdmi: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&hdmi_in_vop>; + }; }; }; =20 @@ -933,6 +938,37 @@ dphy: phy@ff968000 { status =3D "disabled"; }; =20 + hdmi: hdmi@ff980000 { + compatible =3D "rockchip,rk3368-dw-hdmi"; + reg =3D <0x0 0xff980000 0x0 0x20000>; + interrupts =3D ; + clocks =3D <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI= _CEC>; + clock-names =3D "iahb", "isfr", "cec"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_i2c_xfer>; + power-domains =3D <&power RK3368_PD_VIO>; + reg-io-width =3D <4>; + rockchip,grf =3D <&grf>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi_in: port@0 { + reg =3D <0>; + + hdmi_in_vop: endpoint { + remote-endpoint =3D <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg =3D <1>; + }; + }; + }; + hevc_mmu: iommu@ff9a0440 { compatible =3D "rockchip,iommu"; reg =3D <0x0 0xff9a0440 0x0 0x40>, @@ -1196,6 +1232,13 @@ rmii_pins: rmii-pins { }; }; =20 + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins =3D <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins =3D <0 RK_PA6 1 &pcfg_pull_none>, --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F978F4FA; Tue, 21 Oct 2025 07:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 21 Oct 2025 09:43:07 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 8/9] arm64: dts: rockchip: Enable HDMI output on RK3368-Lion-Haikou Date: Tue, 21 Oct 2025 09:42:53 +0200 Message-ID: <20251021074254.87065-9-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Enable the VOP and HDMI controller on the Lion-Haikou board. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz --- .../boot/dts/rockchip/rk3368-lion-haikou.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm= 64/boot/dts/rockchip/rk3368-lion-haikou.dts index abd1af97456a..a8eb4e9c2778 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -58,6 +58,16 @@ vcc5v0_otg: regulator-vcc5v0-otg { }; }; =20 +&display_subsystem { + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdd10_video>; + avdd-1v8-supply =3D <&vcc18_video>; + status =3D "okay"; +}; + &i2c_lvds_blc { eeprom: eeprom@50 { compatible =3D "atmel,24c01"; @@ -101,6 +111,14 @@ &uart1 { status =3D "disabled"; }; =20 +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + &pinctrl { pinctrl-names =3D "default"; pinctrl-0 =3D <&haikou_pin_hog>; --=20 2.47.2 From nobody Sun Feb 8 07:08:34 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07F5128488D; Tue, 21 Oct 2025 07:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032614; cv=none; b=SAE/uZ3VXOXWNrmI9ML+PDP/Q8M8ymdKV+hFQAPJ2gvx1v5Xhw0wHBi67ieH0+lk+A6F53Njf3S1N6dFuBA+YDDECEmHYW425a63d/2rrCrsBmaFvkC1ZiAys6+B99ZOffhfayvnyjzr3rsD10XEyuelU3cQQJjCKg4IxQS/olI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761032614; c=relaxed/simple; bh=YjVPqwonj1/rJ828kwmhAUxbBCmMqwjbewzqyVCGYiM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PDH8vctvSGoctUWg05F9J9ShEKoOuhVoVUn75Id1h0KFBkKOvw8hbYUmmrD+ATxD2WpXtw9UjL+DUBtg+j1m/J7uj2busHOdjM95a1+9f3eq7wXgIlyTlYxYnm5tNOaK6FOI57HsjukN8MJIT9gKUNuhPhjGEnqemm/xdvofkWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=FknXXbVc; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="FknXXbVc" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=OUNye3HxeUTkEv5mR8T9fjHeXru/yz+Ueb4MLuCjw/U=; b=FknXXbVc+AL84Jf0OleZjxYmRq 25eomfdtP+fEGs33x3mvXmhvS019aKYeMy9GK9b6FlMkkh5I05TD8FpM209gLcqvFzpLREUxqtgEH 2VwR9I21xYiqe4AWMSmerkE+WMdf/AMPRmtOAlrmGV3N7gwsmue9HNml+g3VhFvaGGvDB3PIXELzq Q0rwvy4UrbUUhHY7JeqEv5iok+MkeI3vcOLk/hBPyu87mAp73+NYMPVHbYagFHI8P250DzKy9UQfb HAkcPYsfCJ3VH4aYFJ8tFyLKptc9KTv+d+UzHBTPJ27/k6jNAYyEw6s5/J+t1CiydgVCMxWIB2JbU QPKbWVLQ==; Received: from [212.111.240.218] (helo=phil.guestnet.ukdd.de) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vB71Q-0000uy-70; Tue, 21 Oct 2025 09:43:08 +0200 From: Heiko Stuebner To: heiko@sntech.de Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quentin.schulz@cherry.de, andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cn.liweihao@gmail.com, Heiko Stuebner Subject: [PATCH v2 9/9] arm64: dts: rockchip: Add the Video-Demo overlay for Lion Haikou Date: Tue, 21 Oct 2025 09:42:54 +0200 Message-ID: <20251021074254.87065-10-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251021074254.87065-1-heiko@sntech.de> References: <20251021074254.87065-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner The video-demo adapter also works on the Lion SoM when running on a Haikou baseboard, so add an overlay for it. Signed-off-by: Heiko Stuebner Tested-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3368-lion-haikou-video-demo.dtso | 174 ++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-d= emo.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index ad684e3831bc..494fdd685a5c 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-lba3368.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-lion-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-lion-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-r88.dtb @@ -231,6 +232,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D px30-ringneck-haikou-= haikou-video-demo.dtb px30-ringneck-haikou-haikou-video-demo-dtbs :=3D px30-ringneck-haikou.dtb \ px30-ringneck-haikou-video-demo.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3368-lion-haikou-haikou-video-demo.dtb +rk3368-lion-haikou-haikou-video-demo-dtbs :=3D rk3368-lion-haikou.dtb \ + rk3368-lion-haikou-video-demo.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399-puma-haikou-haikou-video-demo.dtb rk3399-puma-haikou-haikou-video-demo-dtbs :=3D rk3399-puma-haikou.dtb \ rk3399-puma-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dts= o b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso new file mode 100644 index 000000000000..e7767c008144 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&dc_12v>; + pwms =3D <&pwm1 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-afvdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "cam-avdd-2v8"; + vin-supply =3D <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible =3D "regulator-fixed"; + gpio =3D <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "cam-dovdd-1v8"; + vin-supply =3D <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <1200000>; + regulator-min-microvolt =3D <1200000>; + regulator-name =3D "cam-dvdd-1v2"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <2800000>; + regulator-min-microvolt =3D <2800000>; + regulator-name =3D "vcc2v8-video"; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible =3D "gpio-leds"; + + video-adapter-led { + color =3D ; + gpios =3D <&pca9670 7 GPIO_ACTIVE_HIGH>; + label =3D "video-adapter-led"; + linux,default-trigger =3D "none"; + }; + }; +}; + +&dphy { + status =3D "okay"; +}; + +&i2c_gp2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency =3D <400000>; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + irq-gpios =3D <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&touch_int>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc2v8_video>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible =3D "nxp,pca9670"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-0 =3D <&pca9670_resetn>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc1v8_video>; + reset-gpios =3D <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins =3D <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins =3D <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status =3D "okay"; +}; \ No newline at end of file --=20 2.47.2