From nobody Sun Feb 8 09:13:10 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C4DA1DE2B4; Tue, 21 Oct 2025 05:39:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761025162; cv=none; b=jWzTf46uvH0+XcikZCE0FaxfI89OP8nnhf862NVoHSujUYMZ+MlnJ9PWjss/Pqdfncb9mIfwbEgtg6QtzvhlaaNpSqJlXBKETxUfKyxJ633hMbcChg9sOa2JULPBkGeMQP75yfNoOo0NikY7/2ZXY5ahypDBCA+T3cvSy6DcexI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761025162; c=relaxed/simple; bh=OvzrEI7sg0zU/mFMC42ov6jMitVx+MGcHE6d4uj/2oM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=SHsLHaNAeab/CTtsQm+9uRoBmHED2jAwRVLR1zs+AVUID2zlXeFFOSx/SNBzEr+mxi8g3Njlii0jMbfWhSnBc5ongfvokTAwx2Z+mFnzgyMflIpLuyROipGZd4IxigRwGFNW/PMkg6CVJHO/TeOIHol5mTQT6LJ8slnOQSbNsoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 21 Oct 2025 13:39:18 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 21 Oct 2025 13:39:18 +0800 From: Billy Tsai To: , , , , , , , , , , Subject: [PATCH v1] iio: adc: clear reference voltage bits before configuring vref Date: Tue, 21 Oct 2025 13:39:18 +0800 Message-ID: <20251021053918.3008654-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ensures the reference voltage bits are cleared in the ADC engine control register before configuring the voltage reference. This avoids potential misconfigurations caused by residual bits. Change-Id: I03c036436f376ced8a19fa5d407b7bbb377ae721 Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 1d5fd5f534b8..8ab29948214a 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -415,6 +415,7 @@ static int aspeed_adc_vref_config(struct iio_dev *indio= _dev) } adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTROL); + adc_engine_control_reg_val &=3D ~ASPEED_ADC_REF_VOLTAGE; =20 ret =3D devm_regulator_get_enable_read_voltage(data->dev, "vref"); if (ret < 0 && ret !=3D -ENODEV) --=20 2.25.1